Abstract: A semiconductor device includes a package 1, a block-module 2, and a control board 3 for controlling power semiconductor elements 11a. The block-module 2 has embedded power semiconductor elements 11a and second leads 4b and first leads 4a that are drawn from the block-module 2. The package 1 has external connection terminals 6a in contact with the first leads 4a of the block-module 2. The second leads 4b are connected to the control board 3 while the first leads 4a are joined to the external connection terminals 6a.

Abstract: A method of dissipating heat from a heat source includes providing a plurality of heat flux paths in a plane of the heat source to remove heat from the heat source.

Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: A flexible printed circuit board, in particular for the spatial connection of electronic components, includes a carrier foil (1), several bonding surfaces (10) arranged on a solder side (4) of the carrier foil (1), and several soldering surfaces (2) arranged on a bonding side (12) of the carrier foil (1) opposite the solder side. The soldering surfaces (2) are connected to the bonding surfaces (10) via electrical strip conductors, and a stiffening plate (3) is inseparably connected to the carrier foil (1) on the solder side thereof.

Abstract: A semiconductor device includes a metallic plate, a bonding layer, a semiconductor chip, and a resin molding. The semiconductor chip is fixed to the metallic plate with the bonding layer. The resin molding is in contact with the metallic plate, and covers the semiconductor chip. In the semiconductor device, a dent is provided in the metallic plate so that the dent is located next to an edge of a fillet of the bonding layer, in a plan view of the metallic plate.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: An electric power semiconductor device includes a power module and a heat dissipating member connected to the power module through a heat-conductive insulating resin sheet in which a mold resin part included in the power module has a protruding part in its peripheral part to prevent the heat-conductive insulating resin sheet from expanding in a planar direction. The heat-conductive insulating resin sheet is slightly thicker than the protruding part and has a resin exuding part exuded from a small gap between the protruding part and the heat dissipating member while the power module and the heat dissipating member are heated and pressurized to be bonded.

Abstract: A semiconductor module is disclosed having at least one power semiconductor device, wherein the at least one power semiconductor device has first and second planar sides; a first thermally conductive substrate in thermal contact with the first planar side of the power semiconductor device; a first cooling module defining a first cavity, the first cavity in thermal contact with the first thermally conductive substrate, and the first cooling module in mechanical connection with the first thermally conductive substrate; a first inlet provided in the first cavity for receiving a coolant; a first outlet provided in the first cavity for discharging said coolant; wherein the power semiconductor device is in coolant-proof isolation from the cavity.

Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

Abstract: A semiconductor element housing package includes a substrate, a frame body disposed on the substrate; an insulating substrate disposed in a frame-body-surrounded region of the substrate; a first mounting member disposed on the insulating substrate, for mounting a power semiconductor element thereon; a second mounting member disposed on the insulating substrate so as to be spaced away from the first mounting member; a first lead member having a first bend; and a second lead member having a second bend. The first lead member is disposed so as to pass through the frame body from an exterior thereof and extend over the first mounting member and makes connection therewith through the first bend. The second lead member is disposed so as to pass through the frame body from the exterior thereof and extend over the second mounting member and makes connection therewith through the second bend.

Abstract: A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region

Abstract: A method of making a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry is disclosed. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device.

Abstract: A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.

Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract: Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract: According to one embodiment, a semiconductor module includes a substrate, which has a first surface and a second surface opposite to the first surface, a controller device and a memory device formed on the first surface, and a metal plate bonded on the second surface. The metal plate is formed at least at a portion of the second surface corresponding to the controller device so that heat generated at the controller device conducts away from the memory device.

Abstract: Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.

Abstract: A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

Abstract: The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

Abstract: The present invention is an improvement in a molded semiconductor package and the method for its manufacture. The package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, a lid on the molding compound, and a heat pipe extending between the semiconductor die and the lid. Preferably, the heat pipe is formed so that it encircles the die. The package is assembled by mounting the die on the substrate, applying the molding compound to the substrate while a channel is formed in the molding compound adjacent the semiconductor die, inserting a heat pipe material in the channel, and mounting the lid on the molding compound and the heat pipe material.

Abstract: A packaged semiconductor device has opposing first and second main surfaces and a sidewall connecting the first and second main surfaces. A semiconductor die is embedded in the package and has a first main surface facing the first main surface of the package and an opposing second main surface facing the second main surface of the package. Conductive leads are electrically coupled to the semiconductor die, each of which is partially embedded within the package and extends outside of the package from the package sidewall. At least one tie bar is partially embedded within the package and has an exposed segment extending outside of the package from the sidewall. A portion of the exposed segment is in contact with the first main surface of the package. The tie bar forms a heat sink to dissipate heat generated by the semiconductor die.

Abstract: A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and one or more heat conductors in the molding compound that are thermally coupled to the substrate. Advantageously, the heat conductors are mounted in the molding compound near one or more of the corners of the die. The package may also include a lid. The heat conductors produce a more uniform distribution of heat in the substrate. The package is assembled by mounting the die on the substrate, mounting the heat conductors on the substrate and applying the molding compound to the substrate, the die, and the heat conductors mounted on the substrate. For packages that use a lid, the lid is then secured to the package and coupled to the heat conductors.

Abstract: An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives.

Abstract: A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween.

Abstract: A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost.

Abstract: A semiconductor device (1) includes: a semiconductor chip (2) having a first main surface and a second main surface opposite to the first main surface; a heat dissipating plate (3) opposed to the first main surface; a first electrode (5) disposed between the first main surface and the heat dissipating plate (3) so as to be electrically connected to the semiconductor chip (2); a pressure contact member (4) opposed to the second main surface; a second electrode (6) disposed between the second main surface and the pressure contact member (4) so as to be electrically connected to the semiconductor chip (2); and a pressure generating mechanism that generates a pressure for pressing the first electrode (5) into contact with the heat dissipating plate (3) and the semiconductor chip (2) and pressing the second electrode (6) into contact with the pressure contact member (4) and the semiconductor chip (2).

Abstract: Thermally regulated semiconductor devices having reduced thermally induced defects are provided, including associated methods. Such a device can include a heat spreader having a monolayer of diamond particles within a thin metal matrix and a semiconductor material thermally coupled to the heat spreader. In one aspect, the coefficient of thermal expansion difference between the heat spreader and the semiconductor material is less than or equal to about 50%.

Abstract: An electronic device is disclosed. One embodiment provides a metallic body. A first electrically insulating layer is applied over the metallic body and having a thickness of less than 100 ?m. A first thermally conductive layer is applied over the first electrically insulating layer and having a thermal conductivity of more than 50 W/(m·K). A second electrically insulating layer is applied over the first thermally conductive layer and having a thickness of less than 100 ?m.

Abstract: A structure, comprising: a semiconductor structure having an electrically and thermally conductive layer disposed on one surface of the semiconductor structure; an electrically and thermally conductive heat sink; a electrically and thermally conductive carrier layer; a plurality of electrically and thermally nano-tubes, a first portion of the plurality of nano-tubes having proximal ends disposed on a first surface of the carrier layer and a second portion of the plurality of nano-tubes having proximal ends disposed on an opposite surface of the carrier layer; and a plurality of electrically and thermally conductive heat conductive tips disposed on distal ends of the plurality of nano-tubes, the plurality of heat conductive tips on the first portion of the plurality of nano-tubes being attached to the conductive layer, the plurality of heat conductive tips on the second portion of the plurality of nano-tubes being attached to the heat sink.

Abstract: A method for producing luminous means proposes providing a carrier serving as a heat sink, said carrier comprising a planar chip mounting region. The planar chip mounting region is structured for the purpose of producing a first partial region and at least one second partial region. In this case, the first partial region has a solder-repellent property after structuring. Afterward, a solder is applied to the planar chip mounting region, such that said solder wets the at least one second partial region. At least one optoelectronic body is fixed into the at least one second partial region with the solder at the carrier. Finally, contact-connections are formed for the purpose of feeding electrical energy to the optoelectronic luminous body.

Abstract: Some implementations provide an apparatus that includes a package substrate, a first die coupled to the package substrate, and a second die coupled to the first die. The die package also includes a heat spreader coupled to the second die, the heat spreader configured to (i) dissipate heat from the second die, and (ii) provide an electrical path for a power signal to the second die. In some implementations, the die package also includes a molding surrounding the first die and the second die. The die package also includes several through mold vias (TMVs) coupled to the heat spreader. The TMVs are configured to provide an electrical path for the power signal to the second die through the heat spreader. In some implementations, the TMVs traverse the molding.

Abstract: A semiconductor device according to the present invention has a semiconductor module 2; a cooling unit 3, the semiconductor module 2 being joined to an upper surface of the cooling unit 3, and a pipe 14, 15 for circulating a refrigerant being fixed to a side surface 20, 22 of the cooling unit 3; and a resin mold layer 4 that covers outer peripheries of the semiconductor module 2 and the cooling unit 3 . Further, a protruding portion 25, 26 that protrudes from the side surface 20, 22 of the cooling unit 3 and surrounds the pipe 14, 15 is provided on the side surface 20, 22 of the cooling unit 3.

Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.

Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.

Abstract: The present invention relates to an apparatus for manufacturing an integrated circuit (10) having a thick film metal layer (14). A layer of metal paste (14) is applied via an application means (24) onto a heat-conducting substrate (12). The metal paste (14) includes metal particles of a predetermined size. An RF generator (16) selectively inductively couples RF energy (18) into the metal paste (14). The predetermined size of the metal particles of the metal paste (14) corresponds to a coupling frequency of the RF energy (18), for heating the metal particles. In this way the metal particles of the metal paste (14) are heated with only a small fraction of the power of conventional processes, and without the need to pre-sinter the metal paste (14).

Abstract: The present specification relates to a semiconductor device in which a metal plate is attached onto a surface of a resin package, and provides a structure in which the metal plate is not easy to separate. The semiconductor device disclosed in the present specification includes semiconductor chips (IGBT, diode), a resin package molding the semiconductor chips, and metal plates fixed onto the surface of the resin package. An anchoring member is bridged between two points on a back face of the metal plate. A space between one of the metal plates and the anchoring member is filled with a molding resin of the resin package. The anchoring member firmly bites the resin package, and therefore, the metal plate is difficult to be released from the resin package.

Abstract: A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.

Abstract: A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (IC) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor IC chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides. The respective second opposing sides of each of the first and second semiconductor IC chips are coupled to first and second respective portions of a sacrificial thermal spreader material, the sacrificial thermal spreader material comprising a material that is thermally conductive. The first and second portions of the sacrificial thermal spreader material are planarized to substantially equalize a respective first height of the first semiconductor chip and a respective second height of the second semiconductor chip.

Abstract: An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

Abstract: An L.E.D. lamp assembly (20) includes an electrically insulative coating (24) disposed on a thermally conductive substrate (22). A plurality of light emitting diodes (26) are secured to the coating (24) and a circuit (40) is adhesively secured to the coating (24) in predetermined spaced lengths (42) along the coating (24) to establish discrete and electrically conductive spaced lengths (42) with the light emitting diodes (26) disposed between the spaced lengths (42). LED electrical leads (32) are secured to the spaced lengths (42) of the circuit (40) to electrically interconnect the light emitting diodes (26). The circuit (40) includes a foil tape (46) having an electrically conductive tape portion (48) and a coupling portion (50) disposed on the tape portion (48) for securing the foil tape (46) to the insulated substrate (22).

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: The production method of a cooler includes a laminated material production step S1 and a brazing joining step. In the laminated material production step, a laminated material is formed by integrally joining a Ni layer made of Ni or a Ni alloy having an upper surface to which a member to be cooled is to be joined by soldering, a Ti layer made of Ti or a Ti alloy and arranged on a lower surface side of the Ni layer, and an Al layer made of Al or an Al alloy and arranged on a lower surface side of the Ti layer in a laminated manner. In the brazing joining step, a lower surface of the Al layer of the laminated material and a cooling surface of a cooler main body are joined by brazing.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device has a substrate having a first surface and a second surface opposite the first surface. Also, the substrate has a first hole. A plurality of leads is disposed over the first surface of the substrate and a die paddle is disposed in the first hole. Additionally, an encapsulant is disposed on the die paddle and the plurality of leads.