Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

Abstract: Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material.

Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.

Abstract: A MEMS package structure, including a substrate, an interconnecting structure, an upper metallic layer, a deposition element and a packaging element is provided. The interconnecting structure is disposed on the substrate. The MEMS structure is disposed on the substrate and within a first cavity. The upper metallic layer is disposed above the MEMS structure and the interconnecting structure, so as to form a second cavity located between the upper metallic layer and the interconnecting structure and communicates with the first cavity. The upper metallic layer has at least a first opening located above the interconnecting structure and at least a second opening located above the MEMS structure. Area of the first opening is greater than that of the second opening. The deposition element is disposed above the upper metallic layer to seal the second opening. The packaging element is disposed above the upper metallic layer to seal the first opening.

Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.

Abstract: A manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, wherein: at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed.

Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.

Abstract: Disclosed are a flip-chip carrier having individual pad masks (IPMs) and a fabricating method of a MPS-C2 package utilized from the same. The flip-chip carrier primarily comprises a substrate and a plurality of the IPMs. The substrate has a top surface and a plurality of connecting pads on the top surface. The IPMs cover the corresponding connecting pads in one-on-one alignment where each IPM consists of a photo-sensitive adhesive layer on the corresponding connecting pad and a pick-and-place body pervious to light formed on the photo-sensitive adhesive layer. After the photo-sensitive adhesive layers are irradiated by light penetrating through the pick-and-place bodies, the pick-and-place bodies can be pulled out by a pick-and-place process to expose the connecting pads from an encapsulant. The issues of solder bridging and package warpage can easily be solved in conventional MPS-C2 packages.

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Abstract: An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body surrounding the semiconductor die and having openings therein receiving respective ones of the conductive pillars. A first interconnect layer is on the LCP body and contacts the openings. Conductive bodies are in the openings to connect the conductive pillars to the first interconnect layer.

Abstract: Compositions containing a divinylarene dioxide and a hydroxy-substituted dioxide compound and having relatively low viscosity and reduced volatility are used as underfills in the manufacture of electronic assemblies.

Abstract: A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.

Abstract: Disclosed herein are a semiconductor package, a method of manufacturing a semiconductor package, and a stack type semiconductor package. The semiconductor package according to a preferred embodiment of the present invention includes: a base substrate on which a first circuit layer is formed; a semiconductor device formed on the base substrate; a molding part formed on the base substrate and formed to enclose the first circuit layer and the semiconductor device; a first via formed on the first circuit layer and formed to penetrate through the molding part; and a second circuit layer formed on an upper surface of the molding part and integrally formed with the first via.

Abstract: The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

Abstract: A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design.

Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.

Abstract: A circuit module includes a circuit substrate, at least one mount component, sealing bodies, and a shield. The circuit substrate includes a mount surface. The mount component is mounted on the mount surface. The sealing body is formed on the mount surface, covers the mount component and has a first sealing body section having a first thickness and a second sealing body section having a second thickness larger than the first thickness. The shield covers the sealing body and has a first shield section formed on the first sealing body section and having a third thickness and a second shield section formed on the second sealing body section and having a fourth thickness smaller than the third thickness. The sum of the fourth thickness and the second thickness equals to the sum of the first thickness and the third thickness.

Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract: Disclosed is a light emitting apparatus. The light emitting apparatus includes a package body; first and second electrodes; a light emitting device electrically connected to the first and second electrodes and including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; and a lens supported on the package body and at least a part of the lens including a reflective structure. The package body includes a first cavity, one ends of the first and second electrodes are exposed in the first cavity and other ends of the first and second electrodes are exposed at lateral sides of the package body, and a second cavity is formed at a predetermined portion of the first electrode exposed in the first cavity.

Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.

Abstract: A method for manufacturing an LED (light emitting diode) is disclosed wherein a metal substrate is provided. A chip fastening area with a depression and two wire fixing areas on the first metal substrate are defined on the metal substrate. The chip fastening area and the wire fixing areas are separated by a plurality of first grooves. An LED chip is provided in the depression of the chip fastening area and electrically connected to the wire fixing areas by wires. An encapsulant is formed to cover and connect the chip fastening area and the wire fixing areas. Portions of the metal substrate except the chip fastening area and the wire fixing areas are removed.

Abstract: An integrated passives package includes an encapsulation compound and a plurality of electrically conductive pads embedded in the encapsulation compound. Each of the pads has opposing first and second sides. The first side of the pads is uncovered by the encapsulation compound and forms array of external electrical connections at a first side of the package. The integrated passives package further includes a plurality of passive components embedded in the encapsulation compound. Each of the passive components has a first terminal attached to one of the pads and a second terminal attached to a different one the pads at the second side of the pads. Corresponding semiconductor modules and methods of manufacturing are also provided.

Abstract: A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling.

Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip disposed within an encapsulant, and a first coil disposed in the semiconductor chip. A dielectric layer is disposed above the encapsulant and the semiconductor chip. A second coil is disposed above the dielectric layer. The first coil is magnetically coupled to the second coil.

Abstract: A semiconductor package includes a lead spaced apart from a semiconductor die. The die includes a diaphragm disposed at a first side of the die and is configured to change an electrical parameter responsive to a pressure difference across the diaphragm. The die further includes a second side opposite the first side, a lateral edge extending between the first and second sides and a terminal at the first side. An electrical conductor connects the terminal to the lead. An encapsulant is disposed along the lateral edge of the die so that the terminal and the electrical conductor are spaced apart from the encapsulant. The encapsulant has an elastic modulus of less 10 MPa at room temperature. A molding compound covers and contacts the lead, the electrical conductor, the encapsulant, the terminal and part of the first side of the die so that the diaphragm is uncovered by the molding compound.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.

Abstract: A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of encapsulating at least part of the connection portions with an adhesive for a semiconductor containing a compound having a group represented by the following formula (1-1) or (1-2): wherein R1 represents an electron-donating group; and a plurality of R1 may be identical or different from each other.

Abstract: The purpose is to provide a fin-integrated type semiconductor device that is a simple structure and has a high heat dissipating characteristic, and to provide a manufacturing method therefor. The semiconductor device includes a base plate having a first major plane and a second major plane opposite to each other, and having a plurality of fins held upright on the first plane and a bulge portion formed thereon to encircle the plurality of fins; an insulation layer formed on the second major plane of the base plate; a circuit pattern fixed to the insulation layer; a semiconductor element connected to the circuit pattern; and a sealing resin sealing the insulation layer, the circuit pattern, and the semiconductor element. The bulge portion formed on the first major plane continuously encircles the plurality of fins.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements.

Abstract: A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow.

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip having a bonding pad, a metal line electrically connected to the semiconductor chip and having a terminal contacting an external terminal, an insulation layer covering the metal line and having an opening that defines the terminal, and a molding layer molding the semiconductor chip, wherein the molding layer includes a recess pattern exposing the bonding pad and extending from the bonding pad to the terminal, and the metal line is embedded in the recess pattern to contact the bonding pad.

Abstract: A thermosetting encapsulation adhesive sheet which is used for encapsulating a chip type device (1) having connection electrodes (bumps) (3) and mounted on a wiring circuit board (2). The thermosetting encapsulation adhesive sheet is composed of an epoxy resin composition having a viscosity of 5×104 to 5×106 Pa·s as measured at a temperature of 80 to 120° C. before thermosetting thereof. The thermosetting encapsulation adhesive sheet makes it possible to conveniently encapsulate a hollow device with an improved yield.

Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor package having a first semiconductor die, which is disposed in a first encapsulant. An opening is disposed in the first encapsulant. A second semiconductor package including a second semiconductor die is disposed in a second encapsulant. The second semiconductor package is disposed at least partially within the opening in the first encapsulant.

Abstract: A novel die seal design, and method for utilization thereof, controls contact of a mold material with the surfaces of a semiconductor die during application, reducing stresses due to a mismatch of the coefficient of thermal expansion of the mold material and the semiconductor die, thereby reducing cracking of the semiconductor die, resulting in increased yields and lower costs, and permits reuse of elements of a mold tool over a range of die sizes.