Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Abstract: An electronic package has a cover or lid mounted onto a substrate to enclose an electronic device, and a liquid thermal interface material is subsequently inserted (through dispensing, injection molding or printing through apertures in the cover or lid) between the surface of the electronic device and the cover, and cured to a solid state.

Abstract: Reducing effects of thermal expansion in electronic components. An electronic device can include a support, such as a leadframe. An electronic component can be supported by the support. A first flexible layer can cover the electronic component. A second more rigid layer can cover the first layer. The first layer can be made from a material that is more flexible than the second layer thereby creating a mechanical buffer layer between the second layer and the electronic component such that the electronic component is protected from thermal expansion of the second portion caused by changes in temperature. The electronic component can be a laser. The first and second materials can be selected to disperse an optical emission from the optical transmitter.

Abstract: The method for filling a liquid material, and the apparatus and the program make it possible, without changing a moving speed of an ejection device, to correct a change in ejection amount and to stabilize an application shape. The method fills a liquid material into a gap between a substrate and a work by using the capillary action. The method includes the steps of: generating an application pattern consisting of a plurality of application areas continuous to one another; assigning a plurality of ejection cycles, each obtained by combining the number of ejection pulses and the number of pause pulses at a predetermined ratio therebetween, to each of the application areas; and measuring an ejection amount at correction intervals and calculating a correction amount for the ejection amount.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: Provided is an RFID tag, wherein a communication distance of several centimeter or more can be secured and the cost of which can be reduced in comparison to conventional on-chip antennas, even when being compact in size (square shaped with a side of 1.9 to 13 mm). The RFID tag (80) comprises an antenna (20), an IC chip (30) connected to the antenna (20), and a sealing material (10) that seals the IC chip (30) and the antenna (20). The antenna (20) is a coil antenna or a loop antenna, and the resonance frequency (f0) of an electric circuit constituted by the inductance (L) of the antenna (20) and the capacitance (C) of the IC chip (30) is equal to the operation frequency of the IC chip (30), or in the vicinity thereof.

Abstract: A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle, having paddle projections along a paddle peripheral side; forming a lead terminal having a lead extension with the lead extension extending towards the paddle peripheral side and between the paddle projections; mounting an integrated circuit over the die paddle; connecting the integrated circuit and the lead extension; and forming an encapsulation over the die paddle and covering the integrated circuit and lead extension.

Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable silicone composition which is fed into the space between the mold and the unsealed semiconductor device to compression molding, the method being characterized by the fact that the aforementioned curable silicone composition comprises at least the following components: (A) an epoxy-containing silicone and (B) a curing agent for an epoxy resin; can reduce warping of the semiconductor chips and circuit board, and improve surface resistance to scratching.

Abstract: An LED package with an extended top electrode and an extended bottom electrode is formed from a first metal and a second metal. An LED is on an inner end of the first metal. An outer end of the first metal has been bent upward twice 90 degrees to form a top flat as an extended top electrode of the package. An outer end of the second metal has been bent downward twice 90 degrees to form a bottom flat as an extended bottom electrode of the package. The LED and a bonding wire may be encapsulated with glue.

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract: A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of electronic components mounted on the top surface of the substrate and electrically connected to the substrate; an encapsulant formed on the top surface of the substrate for encapsulating the electronic components and the axial tube; and an impeller axially coupled to the axial tube via the bottom surface of the substrate. In the semiconductor package, the stator set is formed in the substrate by a patterning process. Therefore, the thickness of the semiconductor package is reduced significantly.

Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; attaching a first integrated circuit die to the bottom substrate; forming an interposer including: forming an intermediate substrate; forming a shield on the intermediate substrate; and applying a wire-in-film adhesive to the shield; and attaching the interposer to the first integrated circuit die with the wire-in-film adhesive.

Abstract: A semiconductor package is provided, including a carrier having electrical connecting pads, a semiconductor element disposed on the carrier and having electrode pads, conductive elements electrically connected to the electrode pads and the electrical connecting pads, fluorine ions formed between the conductive elements and the electrode pads or between the conductive elements and the electrical connecting pads, and an encapsulant formed on the carrier and the conductive elements, wherein the electrode pads or the electrical connecting pads are formed by aluminum materials to form fluorine aluminum by way of packaging the fluorine ions after the completion of the packaging process. Accordingly, the corrosion resistance of the semiconductor package is increased.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A chip package structure including a leadframe, a chip, bonding wires and an encapsulant is provided. The leadframe includes a die pad, leads and an insulating layer. The die pad includes a chip mounting portion and a periphery portion. At the periphery portion, the die pad has a second upper surface lying between a first upper surface and a lower surface of the die pad. Each lead includes a suspending portion and a terminal portion. The suspending portion connects to the terminal portion and extends from the terminal portion towards the die pad. The insulating layer is disposed on the second upper surface of the periphery portion and connects the suspending portions to the die pad. The chip is disposed on the chip mounting portion. The bonding wires electrically connect the chip to the suspending portions. The encapsulant covers the chip, the bonding wires, the insulating layer, and the leadframe.

Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.

Abstract: A semiconductor device includes: leads (5) in each of which a cutout (5a) is formed; a die pad (11); a power element (1) held on the die pad (11); and a package (6) made of a resin material, and configured to encapsulate inner end portions of the leads (5), and the die pad (11) including the power element (1). The cutout (5a) is located in a region of each of the leads (5) including a portion of the lead (5) located at a boundary between the lead (5) and the package (6), and is filled with a resin material.

Abstract: Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

Abstract: This semiconductor device, which has electronic components provided in a cavity of a module having a cavity structure, can be prevented from being increased in size. In the device, the module having the cavity structure is provided with a plurality of components, for instance, an IC (3) and chip components (6a, 6b), on one surface facing a motherboard (9), said one surface being on the cavity side. The motherboard (9) is provided with the chip components (6c, 6d) on parts of one surface facing the module having the cavity structure, said parts not having the components provided on the module surface having the components provided thereon.

Abstract: A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap.

Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.

Abstract: A method for manufacturing an LED package includes following steps. A plate is provided. The plate defines a plurality of the through holes extending from an upper surface to a bottom surface of the plate. A blue film is attached to the bottom surface of the plate and covers openings of the through holes. The blue film and an inner wall of the plate defining the through hole cooperatively define a groove. Glue doped with phosphor particle is injected into the groove. The phosphor particles are condensed to a bottom surface of the glue adjacent to the blue film. The LED chips are embedded in the grooves and positioned at upper ends of the grooves. Finally, the blue film is removed and the plate is severed to obtain a plurality of individual LED packages each including a corresponding LED chip.

Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

Abstract: A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material.

Abstract: A radio frequency (RF) module comprises a conductive top layer configured to improve RF interference-shielding functionality with respect to one or more RF devices disposed on the module. The conductive top layer may be segmented as to form one or more segments of the top layer that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated, top conductive layers correspond to different devices of the module. The top layer may be etched or cut to achieve such segmentation.

Abstract: A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate.

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract: Provided is a photosensitive adhesive composition comprising (A) an alkali-soluble polyimide having particular structural unit(s) and having a particular structure at at least one end of the main chain, (B) a glycidylamine type epoxy compound of a particular structure, (C) a photopolymerizable compound, and (D) a photoinitiator, wherein (A) the alkali-soluble polyimide has a glass transition temperature of 160° C. or higher. The photosensitive adhesive composition has the ability to form patterns with an alkaline developer, excellent thermocompressibility at a low temperature to an irregular substrate after exposure, and a high adhesive strength even at a high temperature.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.

Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip.

Abstract: In the production of a light emitting device, in which a plurality of light emitting element parts carrying LED elements are formed on a substrate, and the substrate is diced, generation of shaving dusts is suppressed at the time of the dicing, and breakage of the substrate during the production process can be prevented. In the process of forming a slit crossing a region for forming a light emitting element part in a metal substrate, a recess which serves as a resin reservoir can be formed so as to cross the slit. The slit can be filled with an insulating material, the recess can be filled with a resin, and they both can be cured. A light emitting element part can be formed in the region for forming the light emitting element part, the metal substrate can be cut into units comprising one or a plurality of the light emitting element parts, and can be mounted on a printed circuit board on which a pattern is formed.

Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.

Abstract: A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin.

Abstract: A semiconductor device lead frame having enhanced mold locking features is provided. The lead frame has a flag with bendable edge features along the edge of the flag. Each edge feature is shaped to resist movement against encapsulating mold material in a plane of the edge feature. By bending a portion of the edge feature, improved mold locking of the flag is provided in multiple planes.

Abstract: Disclosed herein are an electronic component package and a method of manufacturing the same. The electronic component package includes: a substrate; a connection member provided on at least one surface of the substrate; an active element coupled to the substrate by the connection member; and a molding part covering an exposed surface of the active element, wherein the molding part is formed of a first material having a coefficient of thermal expansion of 8 to 15 ppm/° C. and thermal conductivity of 1 to 5 W/m° C. Therefore, warpage may be significantly decreased and heat radiation performance of the active element may be improved, as compared with the case of implementing the molding part using an EMC according to the related art.

Abstract: A method of packaging power devices at a wafer level is disclosed. The method includes preparing a wafer having a plurality of nitride power devices thereon, each of the plurality of nitride power devices having a plurality of electrodes thereon; forming a polymer layer on the plurality of nitride power devices; exposing each of the electrodes from the polymer layer; forming a solder bump on the exposed electrodes; forming a molding layer covering the solder bump on the polymer layer; and removing the wafer and exposing the solder bump.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract: An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device.

Abstract: A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.

Abstract: The invention refers to method for packaging an integrated circuit (IC) comprising steps of: attaching at least one die on a substrate; attaching bond-wires from the die(s) to package terminal pads; mold or dispense a thermo-degradable material on the substrate, die(s) and bond-wires; mold an encapsulant material; decompose the thermo-degradable materials by temperature treatment.