Insulative Housing Or Support Patents (Class 438/125)
  • Publication number: 20140329362
    Abstract: A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventor: Andreas Alfred Hase
  • Publication number: 20140327135
    Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventors: Soo Won Lee, Kyu Won Lee, Eun Jin Jeong
  • Patent number: 8877566
    Abstract: A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Maurice McGlashan-Powell, Soojae Park, Edward J. Yarmchuk
  • Patent number: 8878356
    Abstract: A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: November 4, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Cheng-Hsiang Liu, Kuang-Wei Huang, Chun-Hung Lin, Hsin-Yi Liao
  • Patent number: 8877565
    Abstract: A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy
  • Publication number: 20140322868
    Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Omar James Bchir, Milind Pravin Shah, Houssam Wafic Jomaa, Manuel Aldrete, Chin-Kwan Kim
  • Publication number: 20140319667
    Abstract: A semiconductor apparatus includes: a package substrate on which a semiconductor device is disposed; a mounting board over which the package substrate is mounted; a first restraint that penetrates through the mounting board and the package substrate, and restrains deformation of the mounting board and the package substrate in a direction in which the mounting board and the package substrate are separated from each other; and a second restraint that is disposed between the mounting board and the package substrate, and restrains deformation of the mounting board and the package substrate in a direction in which the mounting board and the package substrate are closer to each other.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 30, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Manabu WATANABE, Kenji FUKUZONO, Shunji BABA
  • Patent number: 8871569
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Hwan Lee, Tae Sung Jeong, Yul Kyo Chung
  • Patent number: 8872330
    Abstract: A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: October 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Siegfried Herrmann, Berthold Hahn
  • Publication number: 20140312512
    Abstract: A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads. A portion of the first insulating layer is removed to form a toroid-shaped SRO over the contact pads while retaining a central portion of the first insulating layer over the contact pads. The central portion of the first insulating layer can extend above a surface of the first insulating layer outside the first conductive layer. A first conductive layer is formed over the central portion of the first insulating layer and through the SRO in the first insulating layer over the contact pads. The first conductive layer may extend above a surface of the first insulating layer outside the second conductive layer. A semiconductor die is mounted to the substrate with the bumps electrically connected to the first conductive layer.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventor: DaeSik Choi
  • Publication number: 20140312498
    Abstract: To provide a semiconductor device having improved reliability. In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly on the soft resin layer and are therefore supported by this soft resin layer. When a load is applied to each of the bonding leads during flip chip bonding, the resin layer sinks, by which a stress applied to a semiconductor chip can be relaxed.
    Type: Application
    Filed: March 30, 2014
    Publication date: October 23, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Michiaki Sugiyama, Jumpei Konno
  • Patent number: 8865526
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Patent number: 8865507
    Abstract: Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 21, 2014
    Assignee: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Leonard Forbes
  • Patent number: 8867869
    Abstract: The present disclosure relates to an optical module comprising a carrier substrate including first electrical connection terminals on a first surface and second electrical connection terminals on a second surface electrically connected to the first electrical connection terminals. The second electrical connection terminals are connectable to a circuit carrier. The optical module further comprises an optically transparent carrier including first electrical connection terminals, and an optical element electrically connected to the optically transparent carrier.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 21, 2014
    Assignee: Tyco Electronics Svenska Holdings AB
    Inventors: Odd Steijer, Magnus Andersson, Lars-Goete Svenson
  • Patent number: 8865587
    Abstract: Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Stuart Cardwell
  • Patent number: 8865522
    Abstract: A method for connecting a semiconductor chip to a metal layer of a carrier substrate is disclosed. A semiconductor chip is provided which has a first side, a second side opposite the first side, a glass substrate bonded to the second side of the semiconductor chip and including at least one opening leaving an area of the second side of the semiconductor chip uncovered by the glass substrate, and a metallization region arranged in the opening of the glass substrate and electrically contacting the second side of the semiconductor chip. The semiconductor chip with the bonded glass substrate is brought onto a metal layer of a carrier substrate. A firm mechanical and electrical connection is formed between the metal layer of the carrier substrate and the metallization region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten von Koblinski, Gerald Lackner, Karin Schrettlinger, Markus Ottowitz
  • Publication number: 20140306016
    Abstract: A contact smart card has a smart card contact pad and an IC chip. The smart card contact pad includes a circuit substrate, a card-reader contact element on a first side of the circuit substrate, and a connection element on a second side of the circuit substrate. The card-reader contact element has a noble metal electrically conductive surface, and the connection element has a chip terminal connection surface which is not a noble metal. The IC chip is preferably flip-chip mounted at the second side of the circuit substrate and electrically connected to the chip terminal connection surface. Furthermore, the chip terminal connection surface is preferably an organometallic electrically conductive corrosion protection layer.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 16, 2014
    Applicant: JOHNSON ELECTRIC S.A.
    Inventors: Vincent Daniel Jean SALLE, Teck De LOI, Arthur DEMASO
  • Publication number: 20140306350
    Abstract: A method of forming a through-glass via hole involves providing a glass substrate having first and second substantially planar parallel surfaces; masking the first and second substantially planar parallel surfaces to form a via-patterned portion thereon; and etching the via-patterned portion on the first and second substantially planar parallel surfaces to form a first channel in the first substantially planar parallel surface and a second channel in the second substantially planar parallel surface. The first channel and second channel are substantially orthogonal or non-orthogonal to one another. The first channel and the second channel intersect to form a quadrilateral through-glass via hole having via openings at the first and second substantially planar parallel surfaces. A low cost, low complexity and high reliability method for producing a glass substrate having a plurality of through-glass via holes such that the glass substrate can be used, for example, as an interposer.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Applicant: Schott Gemtron Corporation
    Inventor: Eric H. Urruti
  • Publication number: 20140306355
    Abstract: A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Inventors: Thorsten Meyer, Gerald Ofner
  • Patent number: 8859342
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: October 14, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Oh Han Kim, Haengcheol Choi, KyungOe Kim
  • Patent number: 8860205
    Abstract: Embodiments of the present invention relate to a method of stiffening a semiconductor coreless package substrate to improve rigidity and resistance against warpage. An embodiment of the method comprises disposing a sacrificial mask on a plurality of contact pads on a second level interconnect (package-to-board interconnect) side of a coreless package substrate, forming a molded stiffener around the sacrificial mask without increasing the effective thickness of the substrate, and removing the sacrificial mask to form a plurality of cavities in the molded stiffener corresponding to the contact pads. Embodiments also include plating the surface of the contact pads and the sidewalls of the cavities in the molded cavities with an electrically conductive material.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Nicholas R. Watts, John S. Guzek
  • Patent number: 8860220
    Abstract: An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Fumihiko Momose, Kazumasa Kido, Yoshitaka Nishimura, Fumio Shigeta
  • Patent number: 8853694
    Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uk Han, Jeong-Kyu Ha, Young-Shin Kwon, Seung-Hwan Kim, Kwan-Jai Lee
  • Publication number: 20140291834
    Abstract: Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Luke G. England, Owen R. Fay
  • Patent number: 8846447
    Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: September 30, 2014
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey, Cyprian Emeka Uzoh
  • Patent number: 8841647
    Abstract: A flexible substrate includes: a flexible base substrate; a plurality of display structures on a first surface of the flexible base substrate; and a barrier coating on a second surface of the flexible base substrate to prevent contaminants from penetrating into the display structures.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: September 23, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Yong In Park, Seung Han Paek, Sang Soo Kim
  • Publication number: 20140264935
    Abstract: A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-m
    Type: Application
    Filed: December 19, 2013
    Publication date: September 18, 2014
    Applicant: Fujitsu Limited
    Inventors: Mamoru Kurashina, Daisuke Mizutani
  • Publication number: 20140273353
    Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masatoshi YASUNAGA, Hironori MATSUSHIMA, Kenya HIRONAGA, Soshi KURODA
  • Publication number: 20140264734
    Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
    Type: Application
    Filed: July 3, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Wei Luo, Hsiao-Tsung Yen, Chin-Wei Kuo, Min-Chie Jeng
  • Publication number: 20140264693
    Abstract: A sensor package includes host substrate assembly includes a first substrate, circuit layers in the first substrate, and first contact pads electrically coupled to the circuit layers. A sensor chip includes a second substrate with opposing first and second surfaces, sensor(s) formed on or under the first surface of the second substrate, a plurality of second contact pads formed at the first surface of the second substrate and which are electrically coupled to the sensor(s), a plurality of holes each formed into the second surface of the second substrate and extends through the second substrate to one of the second contact pads, and conductive leads each extending from one of the second contact pads, through one of the plurality of holes, and along the second surface of the second substrate. A plurality of electrical connectors each electrically connect one of the first contact pads and one of the conductive leads.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 18, 2014
    Applicant: Optiz, Inc.
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 8835221
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jin-Yaun Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Patent number: 8836148
    Abstract: A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 16, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Peter Gillingham
  • Patent number: 8835227
    Abstract: A semiconductor device is manufactured by forming a first dielectric film on a substrate, forming an aperture in the first dielectric film, mounting a semiconductor chip in the aperture, forming a second dielectric film on the first dielectric film and the semiconductor chip, and forming an interconnection wiring structure on the second dielectric film. The second dielectric film secures the semiconductor chip without the need to etch the substrate or use an adhesive die attachment film.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: September 16, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hirokazu Saito
  • Patent number: 8826527
    Abstract: Disclosed herein is a printed circuit board, including: a substrate including an insulation layer in which a cavity is formed; an electronic component mounted in the cavity of the substrate and having connection terminals; an insulation material layer formed on one side of the substrate to bury the electronic component; a first circuit layer formed on the other side of the substrate and including a connection pattern connecting with the connection terminals of the electronic component; and a second circuit layer formed on the insulation material layer. The printed circuit board is advantageous in that it can prevent the warpage thereof and ensure the reliability of electrical connection between an electronic component and a circuit layer by adjusting the thickness, thermal expansion coefficient and elastic modulus of insulation layer or the insulating material.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 9, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jin Seon Park
  • Patent number: 8829684
    Abstract: An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive pathways and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: Microsemi Semiconductor Limited
    Inventors: Piers Tremlett, Michael Anthony Higgins, Martin McHugh
  • Publication number: 20140248746
    Abstract: A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. Applying a transversely extending solder resist strip over the first longitudinal end portions of the bond fingers. The strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps. Each tooth portion and each gap aligned with a different one of the bond fingers in each adjacent pair of bond fingers.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Raymond Maldan Partosa, Jesus Bajo Bautista, James Raymond Baello, Roxanna Bauzon Samson
  • Publication number: 20140248747
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Application
    Filed: May 9, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee
  • Publication number: 20140246783
    Abstract: A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically connected through implant pins and which can be manufactured with high productivity. Implant pins are bonded to a semiconductor element and/or a circuit pattern of a semiconductor mounting board through cylindrical terminals press-fitted into the other ends of the implant pins. Press-fitting depth L2 of each of the implant pins into corresponding cylindrical terminals is adjustable, so that total length of the implant pin and cylindrical terminal which are press-fitted to each other matches up with the distance between the semiconductor element and/or the circuit pattern on the semiconductor mounting board and an implant board.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 4, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Tatsuo NISHIZAWA, Shinji TADA, Yoshito KINOSHITA, Yoshinari IKEDA, Eiji MOCHIZUKI
  • Patent number: 8822266
    Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: September 2, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Peter Deane, Reda R. Razouk
  • Publication number: 20140239444
    Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.
    Type: Application
    Filed: December 27, 2013
    Publication date: August 28, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Abraham F. YEE
  • Publication number: 20140240944
    Abstract: A microelectronic circuit having at least one component adjacent a carrier which is not a semiconductor or sapphire.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Bernard P. Stenson, Michael Morrissey, Seamus A. Lynch
  • Publication number: 20140239491
    Abstract: A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba
  • Patent number: 8815648
    Abstract: A method of assembling semiconductor devices includes applying a metal paste including a plurality of metal particles having an average size less than 50 nanometers and a binder material onto a metal terminal of a package substrate. The metal paste is processed including a heat up step in a reducing gas atmosphere and then a vacuum sintering step at a temperature of at least 200° C. for forming a sintered metal coating. A semiconductor die is attached onto a die attach area of the package substrate. A bond wire is then connected between a bond pad on the semiconductor die and the sintered metal coating on the metal terminal.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: August 26, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kengo Aoya, Shohta Ujiie, Kazunori Hayata
  • Patent number: 8809974
    Abstract: In some embodiments, a semiconductor package can include: (a) a base having a cavity; (b) an interposer coupled to the base and at least partially over the cavity such that the interposer and the base form a back chamber, the interposer has a first opening into the back chamber; (c) a micro-electro-mechanical system device located over the interposer at the first opening; and (d) a lid coupled to the base. Other embodiments also are disclosed.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 19, 2014
    Assignee: Ubotic Intellectual Property Company Limited
    Inventors: Chi Kwong Lo, Lik Hang Wan, Ming Wa Tam
  • Patent number: 8809124
    Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Mathew J Manusharow, Mark S Hlad, Ravi K Nalla
  • Publication number: 20140225259
    Abstract: A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.
    Type: Application
    Filed: April 21, 2014
    Publication date: August 14, 2014
    Applicant: Micron Technology, Inc.
    Inventors: David R Hembree, Alan G. Wood
  • Publication number: 20140227833
    Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.
    Type: Application
    Filed: April 14, 2014
    Publication date: August 14, 2014
    Applicant: Apple Inc.
    Inventors: Shawn X. Arnold, Terry L. Gilton, Matthew E. Last
  • Patent number: 8803310
    Abstract: An embedded electronic device package structure includes a core layer, an electronic device, a first dielectric layer, a second dielectric layer and conductive vias. The core layer has cavity, a first surface and a second surface opposite to the first surface. The electronic device is disposed in the cavity. The first dielectric layer disposed on the first surface is filled in part of the cavity and covers one side of the electronic device. The second dielectric layer disposed on the second surface is filled in the cavity, covers another side of the electronic device and connects the first dielectric layer. The first and the second dielectric layers fully cover the electronic device. The conductive vias are disposed around the surrounding of the electronic device and penetrates through the first and the second dielectric layer and the core layer. The conductive vias respectively connects the first and the second dielectric layer.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: August 12, 2014
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Chen Chuo, Wei-Ming Cheng
  • Patent number: 8803185
    Abstract: A light emitting diode package and a method of fabricating the same. The package includes a light emitting diode chip having a first surface and a second surface opposing the first surface, a metal frame (or TAB tape) having leads connected to the light emitting diode chip, and a light-pervious encapsulant encapsulating the light emitting diode chip, wherein the second surface of the chip is exposed from the first light-pervious encapsulant. The metal frame (or TAB tape) connects the light emitting diode chip to an external circuit board. The LED package does not need wire-bonding process. A method of fabricating a light emitting diode package is also provided.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 12, 2014
    Inventors: Peiching Ling, Vivek B. Dutta
  • Patent number: 8802499
    Abstract: Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: August 12, 2014
    Assignee: Amkor Technology, Inc.
    Inventors: Michael G. Kelly, David Jon Hiner, Ronald Patrick Huemoeller