Abstract: A semiconductor device according to the disclosure includes a first semiconductor chip, a second semiconductor chip, a first metal plate provided on an upper surface of the first semiconductor chip, a second metal plate provided on an upper surface of the second semiconductor chip and a sealing resin covering the first semiconductor chip, the second semiconductor chip, the first metal plate and the second metal plate, wherein a groove is formed in the sealing resin, the groove extending downwards from an upper surface of the sealing resin, the first metal plate includes, at an end facing the second metal plate, a first exposed portion exposed from a side face of the sealing resin forming the groove, and the second metal plate includes, at an end facing the first metal plate, a second exposed portion exposed from a side face of the sealing resin forming the groove.

Abstract: Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system.

Abstract: A method of forming a protective film on at least one electronic module is provided. The method includes the following steps. A protective material is disposed on at least one electronic module such that the protective material and the electronic modules are in contact with each other. The electronic modules and the protective material disposed on the electronic modules are disposed in a chamber, and a first ambient pressure is provided in the chamber. The protective material in the chamber is heated to a first temperature to soften the protective material disposed on the electronic modules. After the protective material is softened, a second ambient pressure greater than the first ambient pressure is provided in the chamber, wherein a gas in the chamber directly pressurizes the protective material such that the protective material conformally covers a top of the electronic modules.

Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.

Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A micromechanical sensor device and a corresponding production method, in which the micromechanical sensor device is equipped with a sensor substrate having a front side and a rear side, a sensor region provided on the front side that can be brought into contact with an environmental medium, and a capping device, attached on the front side, for capping the sensor region. In the capping device and/or in the sensor substrate, one or more capillaries are formed for conducting the environmental medium onto the sensor region, a liquid-repellent layer being provided at least in some regions on the inner walls of the capillaries.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Abstract: A flexible display panel and a method for preparing thereof are provided. The method for preparing the flexible display panel includes providing a glass substrate and applying a thermosetting polymer on the glass substrate; curing the thermosetting polymer thereon into a solid film by baking; removing the solid film on a surface of a bonding region to expose a surface of the glass substrate underneath; forming a buffer layer on a surface of the solid film and the surface of the glass substrate from which the solid film has been removed; forming a metal layer on the buffer layer; forming a solder pad and metal wiring in the bonding region of the metal layer; attaching a chip to the solder pad of the bonding region after finishing bonding and sawing of a panel unit; and removing the glass substrate outside the bonding region and a transition region.

Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.

Abstract: A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.

Abstract: The present invention provides an encapsulation thin-film, including a first inorganic layer composed of a first oxide; a polymer layer disposed on the first inorganic layer, and composed of a polymer bonded to the first oxide by a chemical bond; and a second inorganic layer disposed on the polymer layer, and bonded to the polymer by a chemical bond. The encapsulation thin-film and the display device according to the present invention, the first inorganic layer, the polymer layer and the second inorganic layer are bonded by a chemical bond, thus can prevent external water and oxygen corrosion and improve bending resistance of the display device.

Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.

Abstract: A substrate for a power module (100) of the present invention includes a metal substrate (101), an insulating resin layer (102) provided on the metal substrate (101), and a metal layer (103) provided on the insulating resin layer (102). The insulating resin layer (102) includes a thermosetting resin (A) and inorganic fillers (B) dispersed in the thermosetting resin (A), a maximum value of a dielectric loss ratio of the insulating resin layer (102) at a frequency of 1 kHz and 100° C. to 175° C. is equal to or less than 0.030, and a change in a relative permittivity is equal to or less than 0.10.

Abstract: A lead frame includes a conductive member, a plating layer, and an oxide film. The conductive member includes a rough surface. The plating layer is formed on the rough surface and configured to be connected to a semiconductor element. The oxide film covers the rough surface at least around the plating layer.

Abstract: A semiconductor device includes a printed circuit board, a power element, and a sealing resin encapsulating therein the printed circuit board and the power element. The printed circuit board has a plurality of through holes formed therethrough, the through holes being located along an outer periphery at intervals each being equal to or less than four times as great as a circuit-board thickness. Components, which are electrical components such as a resistor, a capacitor, an integrated circuit, and a photocoupler, are mounted on the primed circuit board. The power element, which is a power semiconductor element, is electrically connected to the printed circuit board. The through holes are filled with the sealing resin.

Abstract: An OLED device encapsulating structure used to encapsulate an OLED is disclosed. The OLED device encapsulating structure includes a substrate, a barrier layer formed on the substrate, a surface active layer disposed on the barrier layer, and a buffer layer stacked on the surface active layer. An orthogonal projection of the buffer layer onto the barrier layer may coincide with that of the surface active layer onto the barrier layer. A composite layer may further be stacked on the buffer layer. An OLED device and a display screen are also disclosed.

Abstract: A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.

Abstract: A base body including a plurality of first regions and a second region having a shape surrounding each of the first regions is prepared. A resin layer is formed in the plurality of first regions while avoiding the second region. A buried layer having a moisture-proof property higher than the resin layer is formed in the second region. A functional layer including a self-emitting element layer emitting light whose luminance is controlled for each of a plurality of unit pixels constituting an image is formed on the resin layer and the buried layer. The buried layer and the functional layer are cut along a line passing through the second region, so as to separate the resin layer into a plurality of portions respectively corresponding to the plurality of first regions.

Abstract: Provided is a light extraction substrate capable of achieving both light extraction efficiency and preservability. Before forming a cap layer, a step of reducing in-membrane water content such that the in-membrane water content of a layer formed between a gas barrier layer and the cap layer is less than 1.0×1015/mg is performed. The in-membrane water content of less than 1.0×1015/mg is maintained until at least a step of forming the cap layer after the step of reducing the in-membrane water content, and the cap layer is then formed through a dry process.

Abstract: Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy.

Abstract: The described embodiments relate generally to liquid crystal displays (LCDs), and more particularly to methods for extending a glass portion of a display to an edge of a display housing. In one embodiment, a thin cover glass layer is provided between a color filter glass layer and an upper polarizer. The thin cover glass layer is supported along an edge of the display by a filler material that can include a foam dam and a glass spacer or adhesive filler. The filler material allows the cover glass layer to be supported without damaging any drivers or circuits located on an underlying thin film transistor glass layer. In another embodiment, a glass spacer circuit with integrated drivers and circuitry on its lower surface can support the cover glass along the edge of the display.

Abstract: According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.

Abstract: Disclosed is a method for the production of an organic light emitting device of the OLED type, the method including the following sequences of steps: a step of forming a stack of layers on a substrate; the stack including, successively and in the following order, a first electrode, an organic layer and a second electrode; a step of positioning a cover; a step of forming a connection pad. The method also includes: a step of fixing a first end of at least one elongated electrical connection member to an area of the connection pad covering a portion of the second face of the cover and a step of forming a layer of resist, the layer of resist being so configured as to preserve an electrical access to a second end of the elongated electrical connection member above the layer of resist.

Abstract: The invention relates to an electrical device comprising an electrical unit (2) like an organic light emitting diode, a protection element (3) like a thin film encapsulation, which at least partly covers the electrical unit, for protecting the electrical unit against water and/or oxygen, and a detection layer (4) arranged between the protection element and the electrical unit or within the protection element, wherein the detection layer comprises organic material and is adapted such that a property of the detection layer is changed, if the detection layer is in contact with a contact gas usable for detecting a permeability of the protection element. This allows easily integrating a fast detection test for detecting a permeability of the protection element into a production process for producing the electrical device, i.e. a time consuming external permeability test may not be required.

Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base strip having a base top side; forming a terminal body with a substantially spherical shape partially in the base strip; attaching a device adjacent the terminal body and over the base top side, a device mount side of the device below a top portion of the terminal body; attaching a device connector to the device and the top portion of the terminal body; applying an encapsulant over the device connector, the device, and the top portion of the terminal body; and removing the base strip providing the terminal body partially exposed from the encapsulant.

Abstract: A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier.

Abstract: Disclosed herein are a power semiconductor module and a method of manufacturing the same. The power semiconductor module includes: a substrate on which a semiconductor device is mounted; a pin positioned on the substrate and having one side electrically connected to the substrate; and a molding part formed to cover a portion of the pin and the substrate and the semiconductor device, wherein the molding part has a pin insertion opening.

Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.

Abstract: Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The upper insulating layer is formed in such a way as to fill a gap between a side surface of the IC chip and an inner peripheral surface of the opening of the core substrate. A first distance from the upper surface of the IC chip to an upper surface of the upper insulating layer is shorter than a second distance from the upper surface of the core substrate to the upper surface of the upper insulating layer.

Abstract: An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device.

Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.

Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.

Abstract: A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.

Abstract: The invention relates to an electronic component (1) having a corrosion-protected bonding connection and a method for producing said component. For this purpose the electronic component (1) has at least one semiconductor chip (3) on a substrate (4). Moreover, a bonding connection at risk of corrosion is provided on the semiconductor chip (3). For encapsulation of the at least one semiconductor chip (3) and the at least one bonding connection at risk of corrosion, said semiconductor chip and bonding connection are surrounded by a hermetically sealing housing (5). The hermetically sealed bonding connection is a bonding wire connection (2) which is fully enclosed in the housing (5), in which the substrate (4) is at least partially enclosed. The substrate (4) has at least one surface-mounted hydrolysis-sensitive component (6) in the housing (5).

Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract: A method for manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect.

Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.

Abstract: A method of forming a package on a package structure includes applying a no-reflow underfill (NUF) layer over a substrate, wherein the substrate has at least one first bump and a plurality of second bumps surrounding the at least one first bump. The method further includes bonding a semiconductor die to the at least one first bump. The method further includes bonding an interposer frame to the plurality of second bumps, wherein the interposer frame surrounds the semiconductor die, wherein the semiconductor die is disposed in an opening of the interposer frame.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.

Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes an interposer and a first semiconductor package comprising a first substrate, and a first semiconductor chip mounted on the first substrate. The device also includes at least two second semiconductor packages electrically connected to a top surface of the interposer, the second semiconductor packages spaced apart from each other in a direction parallel to the top surface of the interposer. Each of the second semiconductor packages comprises a second substrate, a second semiconductor chip mounted on the second substrate and a mold part disposed on the second substrate to protect the second semiconductor chip.

Abstract: An encapsulating sheet-covered semiconductor element includes a semiconductor element having one surface in contact with a board and the other surface disposed at the other side of the one surface and an encapsulating sheet covering at least the other surface of the semiconductor element. The encapsulating sheet includes an exposed surface that is, when projected from one side toward the other side, not included in the one surface of the semiconductor element and exposed from the one surface and the exposed surface has the other side portion that is positioned toward the other side with respect to the one surface of the semiconductor element.

Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

Abstract: The present disclosure relates to a chip package and a method for forming the same. The chip package comprises a carrier pad, a chip, and a plurality of second conductive bumps, and a molding compound. The carrier pad has a first surface with a plurality of first conductive bumps formed thereon. The chip has an active surface. One end of each of the plurality of second conductive bumps is electrically coupled to the active surface, and the other end of each of the plurality of second conductive bumps is electrically coupled to the first conductive bumps. The molding compound encapsulates the chip and completely fills space between the carrier pad and the chip.