And Encapsulating Patents (Class 438/126)
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Publication number: 20150118801Abstract: To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.Type: ApplicationFiled: January 6, 2015Publication date: April 30, 2015Inventors: Kozo HARADA, Shinji BABA, Masaki WATANABE, Satoshi YAMADA
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Patent number: 9018045Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.Type: GrantFiled: July 15, 2013Date of Patent: April 28, 2015Assignee: Freescale Semiconductor Inc.Inventors: Weng Foong Yap, Douglas G. Mitchell
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Patent number: 9018749Abstract: Described herein is a stacked package using laser direct structuring. The stacked package includes a die attached to a substrate. The die is encapsulated with a laser direct structuring mold material. The laser direct structuring mold material is laser activated to form circuit traces on the top and side surfaces of the laser direct structuring mold material. The circuit traces then undergo metallization. A package is then attached to the metalized circuit traces and is electrically connected to the substrate via the metalized circuit traces.Type: GrantFiled: January 2, 2014Date of Patent: April 28, 2015Assignee: Flextronics AP, LLCInventors: Samuel Tam, Bryan Lee Sik Pong, Dick Pang
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Patent number: 9018742Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.Type: GrantFiled: January 19, 2012Date of Patent: April 28, 2015Assignee: Infineon Technologies AGInventors: Ivan Nikitin, Joachim Mahler
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Publication number: 20150108643Abstract: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.Type: ApplicationFiled: October 23, 2014Publication date: April 23, 2015Inventors: Jin Seong Kim, Ye Sul Ahn, Cha Gyu Song
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Publication number: 20150108627Abstract: An electronic component comprises: a resin frame; a semicionductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion.Type: ApplicationFiled: October 21, 2014Publication date: April 23, 2015Inventors: Yasuo SHIMANUKI, Masakazu FUKUOKA
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Patent number: 9006030Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.Type: GrantFiled: December 9, 2013Date of Patent: April 14, 2015Assignee: Xilinx, Inc.Inventors: Woon-Seong Kwon, Suresh Ramalingam, Paul Y. Wu, Manoj Nachnani
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Publication number: 20150099331Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: ApplicationFiled: December 12, 2014Publication date: April 9, 2015Inventors: Eiji HAYASHI, Kyo GO, Kozo HARADA, Shinji BABA
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Publication number: 20150097282Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: ApplicationFiled: December 15, 2014Publication date: April 9, 2015Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Patent number: 8999813Abstract: A method of forming a focal plane array by: forming a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer, the sensing material being a thermistor material defining at least one pixel; providing supporting legs for the pixel within the sacrificial layer, covering them with a further sacrificial layer and forming first conductive portions in the surface of the sacrificial layer that are in contact with the supporting legs; forming a second wafer having read-out integrated circuit (ROIC), the second wafer being covered by another sacrificial layer, into which is formed second conductive portions in contact with the ROIC; bringing the sacrificial oxide layers of the first wafer and second wafer together such that the first and second conductive portions are aligned and bonding them together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; and removing the sacrificial lType: GrantFiled: March 1, 2011Date of Patent: April 7, 2015Assignee: SensoNor ASInventors: Adriana Lapadatu, Gjermund Kittilsland
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Patent number: 8999764Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.Type: GrantFiled: August 10, 2007Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
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Patent number: 8999762Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.Type: GrantFiled: October 5, 2012Date of Patent: April 7, 2015Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Xavier Baillin, Jean-Louis Pornin
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Patent number: 8999763Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.Type: GrantFiled: June 9, 2014Date of Patent: April 7, 2015Assignee: Micron Technology, Inc.Inventors: Steven Eskildsen, Aravind Ramamoorthy
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Publication number: 20150091182Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.Type: ApplicationFiled: September 30, 2013Publication date: April 2, 2015Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
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Publication number: 20150091145Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.Type: ApplicationFiled: December 11, 2014Publication date: April 2, 2015Applicant: STATS CHIPPAC, LTD.Inventors: Yaojian Lin, Pandi C. Marimuthu
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Publication number: 20150091157Abstract: A semiconductor device has a semiconductor die. The semiconductor die is disposed over a conductive substrate. An encapsulant is deposited over the semiconductor die. A first interconnect structure is formed over the encapsulant. An opening is formed through the substrate to isolate a portion of the substrate electrically connected to the first interconnect structure. A bump is formed over the first interconnect structure. Conductive vias are formed through the encapsulant and electrically connected to the portion of the substrate. A plurality of bumps is formed over the semiconductor die. A first conductive layer is formed over the encapsulant. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. Protrusions extend above the substrate.Type: ApplicationFiled: June 14, 2013Publication date: April 2, 2015Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
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Publication number: 20150091167Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
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Patent number: 8993377Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.Type: GrantFiled: September 13, 2011Date of Patent: March 31, 2015Assignee: STATS ChipPAC, Ltd.Inventors: Jun Mo Koo, Pandi C. Marimuthu, Seung Wook Yoon, Il Kwon Shim
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Publication number: 20150087115Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.Type: ApplicationFiled: December 1, 2014Publication date: March 26, 2015Inventors: Wen-Sung HSU, Ming-Chieh LIN, Ta-Jen YU
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Publication number: 20150084185Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
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Patent number: 8987921Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.Type: GrantFiled: July 29, 2011Date of Patent: March 24, 2015Assignee: Robert Bosch GmbHInventors: Ulrike Scholz, Ralf Reichenbach
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Patent number: 8987919Abstract: A built-in electronic component substrate includes a first substrate, an electronic component including side surfaces and mounted on the first substrate, a first resin provided on the first substrate and covering the side surfaces of the electronic component, a second substrate provided above the electronic component and the first resin and layered on the first substrate, a substrate connection member provided between the first and the second substrates and electrically connecting the first and the second substrates, a second resin filling in between the electronic component and the second substrate and in between the first resin and the second substrate, and a third resin filling in between the first and the second substrates and encapsulating the substrate connection member, the electronic component, the first resin, and the second resin.Type: GrantFiled: January 9, 2014Date of Patent: March 24, 2015Assignee: Shinko Electric Industries Co., Ltd.Inventors: Koichi Tanaka, Nobuyuki Kurashima, Hajime Iizuka, Satoshi Shiraki
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Publication number: 20150079736Abstract: A method for manufacturing a semiconductor device by using underfill material includes: a semiconductor chip mounting step configured to mount a semiconductor chip having a solder bump on a substrate via an underfill film including a film forming resin having a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, an epoxy resin, and an epoxy curing agent; and a reflow step configured to solder-bond the semiconductor chip and the substrate by a reflow furnace. The film forming resin of the underfill material has a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, and accordingly, the viscosity at the time of heat melting can be reduced, and a semiconductor chip can be mounted at a low pressure.Type: ApplicationFiled: November 19, 2014Publication date: March 19, 2015Inventor: Taichi KOYAMA
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Patent number: 8980694Abstract: Disclosed are a flip-chip carrier having individual pad masks (IPMs) and a fabricating method of a MPS-C2 package utilized from the same. The flip-chip carrier primarily comprises a substrate and a plurality of the IPMs. The substrate has a top surface and a plurality of connecting pads on the top surface. The IPMs cover the corresponding connecting pads in one-on-one alignment where each IPM consists of a photo-sensitive adhesive layer on the corresponding connecting pad and a pick-and-place body pervious to light formed on the photo-sensitive adhesive layer. After the photo-sensitive adhesive layers are irradiated by light penetrating through the pick-and-place bodies, the pick-and-place bodies can be pulled out by a pick-and-place process to expose the connecting pads from an encapsulant. The issues of solder bridging and package warpage can easily be solved in conventional MPS-C2 packages.Type: GrantFiled: September 21, 2011Date of Patent: March 17, 2015Assignee: Powertech Technology, Inc.Inventor: Shou-Chian Hsu
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Publication number: 20150069601Abstract: A method of manufacturing a semiconductor device and a semiconductor device that is manufactured by the method. In the method of manufacturing a semiconductor device, a releasing sheet is disposed in close contact with a hole of an aluminum plate having the recessed hole, and a skeleton structure of a semiconductor device is put into the recessed hole. Then, liquid epoxy resin is poured into the recessed hole. After hardening, the epoxy resin body 10 including the skeleton structure is taken out from the recessed hole to complete manufacturing the semiconductor device. Using a simple molding jig including the aluminum plate, and covering the skeleton structure with the epoxy resin body, a highly reliable semiconductor device with a case-less construction can be manufactured.Type: ApplicationFiled: August 12, 2014Publication date: March 12, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kei YAMAGUCHI, Yuji Ichimura, Daisuke Kimijima
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Publication number: 20150069612Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.Type: ApplicationFiled: November 19, 2014Publication date: March 12, 2015Inventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20150070864Abstract: An electronic device may be provided with integrated circuits and electrical components such as capacitors that are soldered to printed circuit boards. Liquid polymer adhesive such as encapsulant and underfill materials may be deposited on the printed circuit. Electrical components such as capacitors may be coated with the encapsulant. The underfill may be deposited adjacent to an integrated circuit, so that the underfill wicks into a gap between the integrated circuit and the printed circuit board. The encapsulant may be more viscous than the underfill and may therefore prevent the flowing underfill from reaching the electrical components. Some of the encapsulant may be located between the electrical components and the printed circuit board. The encapsulant can be cured to form an elastomeric material covering the electrical components that helps damp vibrations. The elastomeric material may be less stiff than the underfill.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: Apple Inc.Inventors: Amanda R. Rainer, Connor R. Duke, James W. Bilanski, Jeffrey M. Thoma, Michael Eng, Mingzhe Li, Sung Woo Yoo, Miguel Alejandro Lara-Pena, Weng Choy Foo, Kieran Poulain
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Publication number: 20150070865Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
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Patent number: 8975121Abstract: This invention discloses methods and apparatus to form thin film nanocrystal integrated circuit transistors upon three dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three dimensional surfaces with thin film nanocrystal integrated circuit based thin film transistors, electrical interconnects and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device.Type: GrantFiled: May 9, 2013Date of Patent: March 10, 2015Assignee: Johnson & Johnson Vision Care, Inc.Inventors: Randall B. Pugh, Frederick A. Flitsch
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Patent number: 8975150Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: GrantFiled: July 25, 2011Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Patent number: 8975739Abstract: The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device.Type: GrantFiled: January 10, 2014Date of Patent: March 10, 2015Assignee: Xintec Inc.Inventor: Ming-Chung Chung
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Patent number: 8975120Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).Type: GrantFiled: March 11, 2014Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Naoto Taoka, Atsushi Nakamura, Naozumi Morino, Toshikazu Ishikawa, Nobuhiro Kinoshita
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Publication number: 20150061127Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Feng Chen, Kai-Chiang Wu, Chun-Lin Lu, Hung-Jui Kuo
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Publication number: 20150061113Abstract: A method of processing semiconductor dies is provided. Each semiconductor die has a first side with one or more terminals, a second side opposite the first side and sidewalls extending between the first and the second sides. The semiconductor dies are processed by placing the semiconductor dies on a support substrate so that the first side of each semiconductor die faces the support substrate and the second side faces away from the support substrate. A coating is applied to the semiconductor dies placed on the support substrate. The coating has a lower reflectivity than the first side of the semiconductor dies. The coating covers the second side and at least a region of the sidewalls nearest the second side of each semiconductor die. The semiconductor dies are removed from the support substrate after applying the coating for further processing as loose dies such as taping.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Mathias Vaupel, Günther Ruhl
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Publication number: 20150061091Abstract: An electronic device which comprises at least one interconnect, a semiconductor chip comprising at least one electric chip pad, an encapsulant structure packaging at least a part of the semiconductor chip, and an electrically conductive redistribution layer arranged between and electrically coupled with the at least one interconnect and the at least one chip pad, wherein the redistribution layer comprises at least one adjustment structure configured for adjusting radio frequency properties of a transition between the semiconductor chip and its periphery.Type: ApplicationFiled: August 31, 2013Publication date: March 5, 2015Applicant: Infineon Technologies AGInventors: Ernst SELER, Maciej Wojnowski
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Publication number: 20150061117Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: MediaTek Inc.Inventors: Wen-Sung HSU, Ming-Chieh LIN, Ta-Jen YU
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Publication number: 20150061121Abstract: The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.Type: ApplicationFiled: March 5, 2014Publication date: March 5, 2015Applicant: CHIPMOS TECHNOLOGIES INCInventor: TSUNG JEN LIAO
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Publication number: 20150056756Abstract: The present disclosure relates generally to encapsulant materials, a method of making thereof and the use thereof for maintaining the electrical and mechanical integrity of solder connections between electronic devices and substrates. More specifically, the present disclosure relates to reflow encapsulant materials with fluxing properties and a method of making thereof. The present disclosure further relates to a method of manufacturing flip-chip assemblies using the reflow encapsulant materials of the present disclosure wherein only one heating cycle is utilized.Type: ApplicationFiled: April 5, 2013Publication date: February 26, 2015Inventors: Sathid Jitjongruck, Anongnat Somwangthanaroj
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Publication number: 20150054154Abstract: A method of forming an assembly of a substrate and a flip-chip having solder balls thereon, the method having steps of: placing the flip chip with the solder balls in contact with the substrate to form a first interim assembly at a first predetermined temperature; providing an encapsulant to the first interim assembly to form a second interim assembly at a second predetermined temperature that is lower than a melting temperature of the solder balls and higher than the first predetermined temperature; and subjecting the second interim assembly to an environment of a third predetermined temperature that is sufficient to melt the solder balls. An encapsulant for use in forming an assembly of a substrate and a flip-chip having solder balls thereon, the encapsulant consisting essentially of: an epoxy resin; an anhydride curing agent; a fluxing agent having a hydroxyl (—OH) group; and an inorganic filler.Type: ApplicationFiled: April 5, 2013Publication date: February 26, 2015Inventors: Sathid Jitjongruck, Anongnat Somwangthanaroj
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Publication number: 20150055309Abstract: The present invention can improve efficiency of a process of forming a via for connecting an electronic component embedded in a substrate to external wiring by including an electronic component having at least one external terminal on at least one surface thereof; a third insulating layer having a second circuit pattern on one surface thereof and a cavity to insert the electronic component therein; a fourth insulating layer provided on the third insulating layer and the electronic component; a first via having one surface in contact with the second circuit pattern through the fourth insulating layer; a second via having one surface in contact with the external terminal through the fourth insulating layer; and a fourth circuit pattern provided on an outer surface of the fourth insulating layer to be in contact with the other surface of the first via and the other surface of the second via.Type: ApplicationFiled: December 18, 2013Publication date: February 26, 2015Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Tae Kyun BAE, Doo Hwan Lee
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Publication number: 20150054167Abstract: A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Applicant: STATS ChipPAC, Ltd.Inventor: Rajendra D. Pendse
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Publication number: 20150048503Abstract: A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sao-Ling Chiu, Kuo-Ching Hsu, Wei-Cheng Wu, Ping-Kang Huang, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
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Publication number: 20150050779Abstract: Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (TPVs) over a carrier, and coupling a semiconductor device to the carrier. The semiconductor device includes contact pads disposed on a surface thereof and an insulating material disposed over the contact pads. A molding material is formed over the carrier between the TPVs and the semiconductor device. Openings are formed in the insulating material using a laser drilling process over the contact pads, and a redistribution layer (RDL) is formed over the insulating material and the openings in the insulating material. A portion of the RDL is coupled to a top surface of each of the contact pads.Type: ApplicationFiled: November 3, 2014Publication date: February 19, 2015Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
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Publication number: 20150048504Abstract: A package assembly includes a substrate, a chip located on the substrate, solder balls, pads, an encapsulation and separating posts corresponding to the pads one by one. The chip is electrically connected to the pads via the solder balls, and is encapsulated by the encapsulation. The separating posts extend from the edge of the corresponding pads in a direction away from the pads. The solder balls are accommodated in the separating posts to avoid a short connection between any two adjacent solder balls. A method of manufacturing the package assembly is also provided.Type: ApplicationFiled: October 22, 2013Publication date: February 19, 2015Applicant: AMBIT MICROSYSTEMS (ZHONGSHAN) LTD.Inventor: YUE-RONG WANG
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Patent number: 8956921Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.Type: GrantFiled: March 15, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
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Patent number: 8956914Abstract: An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.Type: GrantFiled: June 26, 2007Date of Patent: February 17, 2015Assignee: STATS ChipPAC Ltd.Inventors: Ja Eun Yun, Jong Wook Ju
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Publication number: 20150044824Abstract: The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
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Publication number: 20150044823Abstract: A method of forming a wire bond having a free end includes joining an end of a metal wire to a conductive element at a surface of a first component, the end of the metal wire being proximate a surface of a bonding tool adjacent an aperture through which the metal wire extends. A predetermined length of the metal wire is drawn out from the aperture. The surface of the bonding tool is used to plastically deform a region of the metal wire between the surface of the bonding tool and a metal element at the surface of the first component. The bonding tool then applies tension to the metal wire to cause a first portion of the metal wire having the end joined to the conductive element to detach from a remaining portion of the metal wire at the plastically deformed region.Type: ApplicationFiled: August 8, 2013Publication date: February 12, 2015Applicant: INVENSAS CORPORATIONInventor: Ilyas Mohammed
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Publication number: 20150044819Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.Type: ApplicationFiled: October 24, 2014Publication date: February 12, 2015Inventors: Chih-Wei Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chun-Cheng Lin, Meng-Tse Chen, Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Bor-Ping Jang, Hsiu-Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin
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Patent number: 8951848Abstract: A circuit board includes an insulation layer, an electrically conductive layer, and a solder mask layer. The insulation layer has a plurality of through holes passing through. The electrically conductive layer is formed on a surface of the insulation layer and covers the through holes. The electrically conductive layer has a plurality of portions exposed in the through holes to serve as a plurality of first conductive pads. The solder mask layer covers the electrically conductive layer and defines a plurality of openings to expose parts of the electrically conductive layer. Parts of the electrically conductive layer are exposed to the solder mask layer to serve as a plurality of second conductive pads. The second conductive pads are electrically connected to the first conductive pads respectively. This disclosure further relates to a chip package and a method of manufacturing the same.Type: GrantFiled: February 20, 2013Date of Patent: February 10, 2015Assignee: Zhen Ding Technology Co., Ltd.Inventors: E-Tung Chou, Chih-Jen Hsiao