Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs.

Abstract: An integrated circuit package system includes: providing a mountable structure having a contact pad and an inner pad; mounting an integrated circuit device having a linear through channel over the mountable structure with the linear through channel traversing between an integrated circuit device first side and an integrated circuit device second side; and connecting the linear through channel exposed on the integrated circuit device second side to the inner pad.

Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Abstract: Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages.

Abstract: A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.

Abstract: A light emitting device package including a package body including a plurality of first ceramic layers, at least one electrode pattern placed on the package body, at least one light emitting device electrically connected to the electrode pattern, and a heat dissipation member disposed in the package body to thermally come into contact with the light emitting device, wherein the heat dissipation member is provided with an expanded portion at a region corresponding to a boundary of different first ceramic layers.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract: A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate. A bond layer is disposed between the substrate and the dielectric liner layer.

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.

Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.

Abstract: A semiconductor chip which is mounted on a wiring substrate and which is electrically connected to the wiring substrate is disposed in a sealing apparatus. A sealing resin material made of a thermosetting resin composition is supplied into the sealing apparatus. The sealing resin material contains a solid foreign matter having a cured product of a thermosetting resin, and includes particulates of the thermosetting resin composition pulverized with the solid foreign matter, a granulation powder of the particulates, or a preform of the particulates. The semiconductor chip is resin sealed by using the sealing resin material.

Abstract: In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant.

Abstract: A connection device includes a mounting section on which an electronic component stacked with a thermosetting adhesive agent layer is mounted, a heat press head for heating and pressing the electronic component, a first elastic body that is disposed between the electronic component and a pressing surface of the heat press head so as to press an upper surface of the electronic component, and a support member that is disposed on a periphery of the electronic component and supports the first elastic body.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant.

Abstract: In various embodiments, a package arrangement is provided. The package arrangement may include a first package. The package arrangement may further include a through hole package including at least one contact terminal. The first package may include at least one hole in an encapsulant to receive the at least one contact terminal of the through hole package. The received at least one contact terminal may provide a solder contact.

Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Abstract: Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 ?m, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 ?m; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 ?m. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure.

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Abstract: A semiconductor package structure includes a chip unit, a package unit and an electrode unit. The chip unit includes at least one semiconductor chip. The semiconductor chip has an upper surface, a lower surface, and a surrounding peripheral surface connected between the upper and the lower surfaces, and the semiconductor chip has a first conductive pad and a second conductive pad disposed on the lower surface thereof. The package unit includes a package body covering the upper surface and the surrounding peripheral surface of the semiconductor chip. The package body has a first lateral portion and a second lateral portion respectively formed on two opposite lateral sides thereof. The electrode unit includes a first electrode structure covering the first lateral portion and a second electrode structure covering the second lateral portion. The first and the second electrode structures respectively electrically contact the first and the second conductive pads.

Abstract: A system and method for manufacturing an integrated circuit packaging system includes: forming a base substrate including: providing a sacrificial carrier: mounting a metallic sheet on the sacrificial carrier, applying a top trace to the metallic sheet, forming a conductive stud on the top trace, forming a base encapsulation over the metallic sheet, the top trace, and the conductive stud, the top trace exposed from a top surface of the base encapsulation, and removing the sacrificial carrier and the metallic sheet; mounting an integrated circuit device on the base substrate; and encapsulating the integrated circuit device and the base substrate with a top encapsulation.

Abstract: According to one embodiment, there is disclosed a semiconductor device which has a wiring substrate, a semiconductor element mounted on the wiring substrate, a molding resin which seals the semiconductor element, and a shield layer provided on the molding resin, wherein the molding resin has a marking portion by laser irradiation on a surface, and the shield layer is provided on the molding resin having the marking portion.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

Abstract: A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer.

Abstract: A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness.

Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

Abstract: A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer.

Abstract: A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector.

Abstract: A method of forming a package on package structure includes bonding a semiconductor die and an interposer frame to a substrate, and the interposer frame surrounds the semiconductor die. The semiconductor die is disposed in an opening of the interposer frame, and the interposer frame has a plurality of TSHs. The plurality of TSHs is aligned with a plurality of bumps on the substrate. The method also includes positioning a packaged die over the semiconductor die and the interposer frame. The packaged die has a plurality of bumps aligned with the plurality of TSHs of the interposer. The method further includes performing a reflow process to allow solder of the plurality of bumps of the substrate and the solder of the plurality of bumps of the packaged die to fill the plurality of TSHs.

Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.

Abstract: There are provided a substrate for mounting a device and a package for housing the device employing the same in which a power semiconductor device can be readily set for a temperature suitable for operation and can thus function in a proper fashion. The substrate for mounting the device includes a support body having, on one main surface of the support body, a device mounting portion for mounting a power semiconductor device, the support body having a plurality of columnar parts that are spaced apart in a thickness direction with respect to the device mounting portion and are arranged apart from each other; and a heat accumulating region which is disposed between the columnar parts and is lower in thermal conductivity than the support body.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: Thermosetting resin compositions with low coefficient of thermal expansion are provided herein.

Abstract: A method for producing a light emitting diode device includes the steps of preparing a board mounted with a light emitting diode; preparing a hemispherical lens molding die; preparing a light emitting diode encapsulating material which includes a light emitting diode encapsulating layer and a phosphor layer laminated thereon, and in which both layers are prepared from a resin before final curing; and disposing the light emitting diode encapsulating material between the board and the lens molding die so that the phosphor layer is opposed to the lens molding die to be compressively molded, so that the light emitting diode is directly encapsulated by the hemispherical light emitting diode encapsulating layer and the phosphor layer is disposed on the hemispherical surface thereof.

Abstract: A method of packaging integrated circuits includes providing a molded substrate including a first plurality of functional semiconductor dies and a plurality of placeholders laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the placeholders. The exposed placeholders are removed to form cavities in the molded substrate. A second plurality of functional semiconductor dies is inserted in the cavities formed in the molded substrate. Electrical connections are formed to the first plurality and second plurality of functional semiconductor dies at a side of the dies uncovered by the molding compound.

Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.

Abstract: The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Abstract: A packaging substrate is disclosed, which includes: an encapsulant having opposite first and second surfaces; a plurality of conductive elements embedded in the encapsulant, wherein each of the conductive elements has a first conductive pad exposed from the first surface of the encapsulant and a second conductive pad exposed from the second surface of the encapsulant; and a protection layer formed on the second surface of the encapsulant and the second conductive pads so as to protect the second surface of the encapsulant from being scratched.

Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side.

Abstract: Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.

Abstract: The method for filling a liquid material, and the apparatus and the program make it possible, without changing a moving speed of an ejection device, to correct a change in ejection amount and to stabilize an application shape. The method fills a liquid material into a gap between a substrate and a work by using the capillary action. The method includes the steps of: generating an application pattern consisting of a plurality of application areas continuous to one another; assigning a plurality of ejection cycles, each obtained by combining the number of ejection pulses and the number of pause pulses at a predetermined ratio therebetween, to each of the application areas; and measuring an ejection amount at correction intervals and calculating a correction amount for the ejection amount.

Abstract: A method of manufacturing a flip chip package includes: providing a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is to be mounted, and a connection pad disposed outside the mounting region; forming a resin layer on the board; forming a trench by removing a part of the resin layer or forming an uneven portion at a portion of a surface of the resin layer; forming, on the trench or uneven portion, a dam member preventing leakage of an underfill between the mounting region and the connection pad; and mounting the electronic device on the mounting region.