Abstract: An array substrate, a method for manufacturing the same, a display panel, and a display device are provided. In the method for manufacturing an array substrate provided by an embodiment of the present disclosure, the annealing process for the first active layer in the pixel area is performed by a high temperature required in the dehydrogenation process for the second active layer in the peripheral area.

Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10?13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract: According to one embodiment, a thin film transistor includes an oxide semiconductor layer provided above an insulating substrate and including a channel region between a source region and a drain region, a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region, a gate electrode provided on the first insulating film, a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal, a second protective film provided on the first protective film and a third protective film provided on the second protective film, as an insulating film containing a metal.

Abstract: A method of manufacturing an array substrate is provided. The method divides an array substrate into a curing area and a stretchable area. A metal wiring corresponding to the stretchable area is made of a flexible conductive material, so as to reduce disconnection risk of the display panel during bending.

Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.

Abstract: Disclosed are an organic light-emitting display device and a method for manufacturing the same. In the organic light-emitting display device, a switching thin film field-effect transistor comprises a first active layer for reducing a sub-threshold swing of a transfer characteristic curve of the switching thin film field-effect transistor; and a driving thin film field-effect transistor comprises a second active layer for increasing a sub-threshold swing of a transfer characteristic curve of the drive film field-effect transistor.

Abstract: A vertical power semiconductor component includes a semiconductor chip, the semiconductor chip having a top main surface and a bottom main surface. Each of said top main surface and said bottom main surface is in a heat exchanging relationship with a top metallization layer and a bottom metallization each of which serving as a heat sink. Each of said top metallization layer and said bottom metallization layer have a layer thickness of at least 15 ?m and have a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. Each of said top metallization layer and said bottom metallization layer serving as a heat sink contacts the respective main surface via a respective diffusion barrier layer.

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: An OLED display panel includes a cover and a backplane, a plurality of color filter (CF) units are arranged in an array on the cover; auxiliary cathodes are filled into gaps among the CF units; the auxiliary cathodes include a black matrix, a buffer layer and a metal layer; a planarization layer is disposed on the auxiliary cathodes and the CF units; a plurality of openings are disposed in the planarization layer at locations corresponding to the auxiliary cathodes; a plurality of spacers are disposed on the planarization layer at locations corresponding to the auxiliary cathodes; the spacers abut against and support the cover and the backplane; a transparent electrode layer is disposed on the planarization layer and the spacers and is communicated with the auxiliary cathodes via the openings; and the plurality of CF units of the cover and pixel regions of the backplane are oppositely arranged.

Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first fin structure over the substrate. The first fin structure includes a first semiconductor material layer, having a semiconductor oxide layer as its outer layer, as a lower portion of the first fin structure. The first semiconductor has a first width. The first fin structure also includes a second semiconductor material layer as an upper portion of the first fin structure. The second semiconductor material layer has a third width, which is substantially smaller than the first width. The semiconductor structure also includes a gate region formed over a portion of the first fin and a high-k (HK)/metal gate (MG) stack on the substrate including wrapping over a portion of the first fin structure in the gate region.

Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.

Abstract: To provide a liquid crystal display device suitable for a thin film transistor which uses an oxide semiconductor. In a liquid crystal display device which includes a thin film transistor including an oxide semiconductor layer, a film having a function of attenuating the intensity of transmitting visible light is used as an interlayer film which covers at least the oxide semiconductor layer. As the film having a function of attenuating the intensity of transmitting visible light, a coloring layer can be used and a light-transmitting chromatic color resin layer is preferably used. An interlayer film which includes a light-transmitting chromatic color resin layer and a light-blocking layer may be formed in order that the light-blocking layer is used as a film having a function of attenuating the intensity of transmitting visible light.

Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).

Abstract: A method for manufacturing a semiconductor device includes: digging first and second trenches at the top surface of a plate-like base-body portion; forming an insulating film in the inside of each of the first and second trenches; laminating a conductive film on the top surface of the base-body portion so as to bury the first and second trenches with the conductive film via the insulating film; testing insulation-characteristics of the insulating film by applying a voltage between the conductive film and the bottom surface of the base-body portion; and after testing the insulation-characteristics, selectively removing the conductive film from the top surface of the base-body portion, so as to define a gate electrode in the first trench and an separated-electrode in the second trench, the separated-electrode being separated from the gate electrode.

Abstract: A method and apparatus, the method comprising: forming at least two electrodes (23) on a release layer wherein the at least two electrodes are configured to enable a layer of two dimensional material (25) to be provided between the at least two electrodes; providing moldable polymer (27) overlaying the at least two electrodes; wherein the at least two electrodes and the moldable polymer form at least part of a planar surface (29).

Abstract: An array substrate and a method of manufacturing the array substrate are provided. The method includes providing a substrate, sequentially forming a light-shielding layer, a buffer layer, an active layer, a source, a drain, a gate insulating layer, and a gate on the substrate, performing a first conductorization process on a corresponding region of the active layer opposite to the source and the drain, and performing a second conductorization process on another corresponding region of the active layer between the source and the gate and between the drain and the gate.

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first stack having layers of a first material and layers of a second material. A second stack is formed having layers of a third material, layers of the second material, and a liner formed around the layers of the third material. A dummy gate stack is formed over channel regions of the first and second stacks. A passivating insulator layer is deposited around the dummy gate stacks. The dummy gate stacks are etched away. The second material is etched away after etching away the dummy gate stacks. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices.

Abstract: A manufacturing method of the back-channel-etched (BCE) TFT substrate, able to prevent the passivation layer from curling up and forming bubbles, while not causing damaging to the channel region of the active layer.

Abstract: There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.

Abstract: A complimentary metal-oxide-semiconductor (CMOS) device includes a wafer having a bulk semiconductor layer. A fin-type semiconductor device is formed on a first portion of the wafer. The CMOS devices also includes a nanosheet semiconductor device formed on a second portion of the wafer different from the first portion.

Abstract: Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.

Abstract: A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug adjacent to the active device; and a second contact plug in the ILD layer and electrically connected to the active device. Preferably, the first contact plug includes a first portion in the insulating layer and the second semiconductor layer and a second portion in the ILD layer, in which a width of the second portion is greater than a width of the first portion.

Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a pixel region formed in a substrate and a storage region formed in the substrate and adjacent to the pixel region. The FSI image sensor device structure includes a storage gate structure formed over the storage region, and the storage gate structure includes a top surface and sidewall surfaces. The FSI image sensor device structure includes a metal shield structure formed on the storage gate structure, and the top surface and the sidewall surfaces of the storage gate structure are covered by the metal shield structure.

Abstract: This disclosure relates to the field of display technologies, and discloses a method for manufacturing an array substrate, an array substrate, a grayscale mask plate and a display device. The method includes forming a transparent conductive layer and a metal layer sequentially on a base substrate. A photoresist pattern is formed on the base: substrate on which the transparent conductive layer and the metal layer have been formed The transparent conductive layer and the metal layer corresponding to a photoresist-free region are removed. The photoresist in a second photoresist region is removed. The metal layer corresponding to the second photoresist region is removed to expose a pixel electrode. Additionally, the photoresist in a first photoresist region is removed to expose a first electrode, a second electrode and a first data line.

Abstract: Provided is a hydrogenation annealing method using a microwave, which performs hydrogenation annealing at a low temperature and with low power in a manufacturing process of a thin film transistor (TFT) for a display device. The hydrogenation annealing method is constituted by a loading step of loading a device requiring hydrogenation annealing into a chamber and an annealing step of irradiating a microwave having a frequency in an industrial scientific medical (ISM) band into the chamber into which the device is loaded. As hydrogenation annealing is performed at a low temperature by using the microwave for an oxide semiconductor TFT or LTPS having very large electron mobility, high integrated energy is transmitted to the device by the microwave, thereby implementing recoupling of hydrogen atoms which have been performed only at a high temperature, even at a low temperature.

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and strained source and drain regions. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. Moreover, the strained source and drain regions are located within recesses of the semiconductor fin beside the gate stack. Moreover, at least one of the strained source and drain regions has a top portion and a bottom portion, the bottom portion is connected to the top portion, and a bottom width of the top portion is greater than a top width of the bottom portion.

Abstract: A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature is at least partially disposed in the substrate. The gate structure is disposed on the substrate and adjacent to the source/drain feature. The contact is electrically connected to the source/drain feature. The gate spacer is disposed on a sidewall of the gate structure and between the gate structure and the contact. The contact spacer is disposed on the gate spacer and on a sidewall of the contact. An interface is formed between the gate spacer and the contact spacer, and a bottom surface of the contact spacer is in contact with the contact.

Abstract: Embodiments of the disclosure relate to a signal line structure, an array substrate, and a display device, where the signal line structure includes a plurality of signal lines arranged adjacent to each other at the same layer; and at least one redundant wire at a different layer from the signal lines, wherein each redundant wire corresponds to two adjacent signal lines, and a positive projection of the each redundant wire onto the layer where the signal lines are located covers a part or all of a gap between the two adjacent signal lines corresponding to the each redundant wire.

Abstract: A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.

Abstract: A display device, including a first transparent magnetic layer; a display panel on the first transparent magnetic layer; an upper member on the display panel; and a second transparent magnetic layer on the upper member, the second transparent magnetic layer being penetrated by light.

Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.

Abstract: A time temperature monitoring system and method for use with a microchip or similar structure. A disclosed system includes: a substrate having an active region; a dopant source located proximate the active region; an activation system for activating a diffusion of the dopant source into the active region; and a set of spatially distributed electrodes embedded in the active region of the substrate, wherein the electrodes are configured to detect the diffusion in the active region at varying distances from the dopant source to provide time temperature information.

Abstract: The present disclosure relates to a nano-scale transistor. The nano-scale transistor includes a source electrode, a drain electrode, a gate electrode and a nano-heterostructure. The nano-heterostructure is electrically coupled with the source electrode and the drain electrode. The gate electrode is insulated from the nano-heterostructure, the source electrode and the drain electrode via an insulating layer. The nano-heterostructure includes a first carbon nanotube, a second carbon nanotube and a semiconductor layer. The semiconductor layer includes a first surface and a second surface opposite to the first surface. The first carbon nanotube is located on the first surface, the second carbon nanotube is located on the second surface.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate manufacturing method comprises: forming a source electrode and a drain electrode on a gate insulating layer; forming photoresist above the gate insulating layer and the source electrode and the drain electrode; etching the photoresist to form an opening region so as to expose the gate insulating layer between the source electrode and the drain electrode, and a part of the source electrode and a part of the drain electrode; and forming an active layer in the opening region, the active layer covering the exposed gate insulating layer, the part of the source electrode and the part of the drain electrode.

Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.

Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

Abstract: Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer st

Abstract: A deposition mask includes a deposition pattern through which a deposition material passes and a distal end extended in a length direction of the deposition mask from the deposition pattern. The distal end includes a dummy pattern between a clamping groove and the deposition pattern in the length direction. The clamping groove and the dummy pattern are provided in plural along a second direction crossing the length direction. In the length direction of the deposition mask, the number of clamping grooves and dummy patterns correspond to each other, the clamping grooves respectively overlap a corresponding dummy pattern, a distal end area at which clamping grooves overlap the corresponding dummy pattern defines a second area of the distal end, and a distal end area at which the clamping grooves do not overlap the corresponding dummy pattern defines a first area of the distal end to which a clamp is applied.

Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.

Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.

Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Abstract: The present disclosure discloses an organic light emitting diode substrate and a method for manufacturing the same. In one embodiment the present disclosure, an organic light emitting diode substrate includes a display region in which an organic film layer that is formed by curing an ink layer is provided, and a border region located outside the display region and including an exposed area in which no organic film layer is provided. The organic light emitting diode substrate further includes: a barrier structure located in the border region and adapted for preventing the ink layer from coming into contact with a surface of the exposed area.

Abstract: A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.

Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.

Abstract: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.