Including Recrystallization Step Patents (Class 438/166)
  • Patent number: 11161201
    Abstract: A powder melting device for an additive manufacturing system is provided. The powder melting device includes at least one laser device configured to generate at least one energy beam for forming at least one melt pool in a layer of powdered material. The powder melting device also includes at least two optical elements configured to dynamically induce beam distortion in the at least one energy beam to modify a beam spot incident on the layer of powdered material. The at least two optical elements are configured to induce at least one of an aspect ratio adjustment of the at least one energy beam, an optical powder redistribution between a periphery and a center of the at least one energy beam, and a rotation of the at least one energy beam.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: November 2, 2021
    Assignee: General Electric Company
    Inventors: Victor Petrovich Ostroverkhov, Jason Harris Karp, Mark Marshall Meyers, William Thomas Carter
  • Patent number: 11158504
    Abstract: A method of making polycrystalline silicon (p-Si), including: depositing amorphous silicon to produce an amorphous silicon super-mesa; dehydrogenating the amorphous silicon; patterning the super-mesa to produce a patterned substrate; depositing a capping oxide layer on the amorphous silicon on the patterned substrate; heating the capped, patterned substrate to the crystallization temperature of the a-Si; and flash lamp annealing the patterned substrate with a xenon lamp to produce p-Si having at least one super-mesa, and the super-mesa having supersized grains. Also disclosed are p-Si articles and devices incorporating the articles, and an apparatus for making the p-Si articles.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 26, 2021
    Assignee: Corning Incorporated
    Inventors: Karl D Hirschman, Robert George Manley, Tarun Mudgal
  • Patent number: 11152232
    Abstract: Localized heating can use a fixed-frequency planar transmission line resonators arranged along a main-line, selected by tuning an electromagnetic input signal frequency applied to the main line for depositing heat in an adjacent active substrate. More generally, adjusting input signal frequency can be used to selectively address and energize an electromagnetic-to-heat, an electromagnetic-to-vibration, or other transducer to controllably direct energy toward a desired transducer load. Resonators or other electromagnetically energized transducers can be arranged to electromagnetically interfere, such that specifying or adjusting a relative phase of applied electrical signals can be used to specify or adjust the energy directed toward a desired transducer load. Temperature sensing can characterize a material in a target region near the transducer. A cold-hot-cold temperature profile can better manage temperature and avoid overheating a dielectric material such as the active substrate material.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: October 19, 2021
    Inventor: Anand Deo
  • Patent number: 11107710
    Abstract: Localized heating can use a fixed-frequency planar transmission line resonators arranged along a main-line, selected by tuning an electromagnetic input signal frequency applied to the main line for depositing heat in an adjacent active substrate. More generally, adjusting input signal frequency can be used to selectively address and energize an electromagnetic-to-heat, an electromagnetic-to-vibration, or other transducer to controllably direct energy toward a desired transducer load. Resonators or other electromagnetically energized transducers can be arranged to electromagnetically interfere, such that specifying or adjusting a relative phase of applied electrical signals can be used to specify or adjust the energy directed toward a desired transducer load. Temperature sensing can characterize a material in a target region near the transducer. A cold-hot-cold temperature profile can better manage temperature and avoid overheating a dielectric material such as the active substrate material.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 31, 2021
    Inventor: Anand Deo
  • Patent number: 11024503
    Abstract: To provide a laser annealing device capable of performing annealing whereby electron mobility is different depending on the part, a mask, a thin film transistor, and a laser annealing method. A laser annealing device of the present invention is provided with a mask in which a plurality of openings are formed along the scanning direction, moves a substrate in the scanning direction, and irradiates the substrate with laser light via the openings. The openings respectively have first opening regions, which are aligned in the scanning direction, and which have a same shape, and some of the openings among the openings respectively have second opening regions continuous to the first opening regions in the predetermined direction with respect to the first opening regions.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 1, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Hidetoshi Nakagawa
  • Patent number: 11006489
    Abstract: An optical device includes a light-emitting device and a sensor device (a light receiving element). The light-emitting device includes a substrate, a plurality of light-emitting elements, and a plurality of light-transmitting units. The substrate has a first surface and a second surface. The second surface is opposite the first surface. The plurality of light-emitting elements are located on the first surface side of the substrate. Each of the plurality of light-transmitting units is located between light-emitting elements adjacent to each other. The light-emitting device has light-transmitting properties by the plurality of light-transmitting units. Light from the plurality of light-emitting elements is emitted mainly from the second surface of the substrate. The amount of light leakage from light emitted from each light-emitting element and leaked toward the outside of the first surface of the substrate is suppressed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 11, 2021
    Assignee: PIONEER CORPORATION
    Inventor: Kazuaki Arai
  • Patent number: 10950707
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 16, 2021
    Assignee: Acorn Semi, LLC
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 10937984
    Abstract: The present disclosure relates to an organic compound, a light emitting diode and an organic light emitting diode display device using the same. The organic compound is represented by a following chemical formula 1.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 2, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Ji-Cheol Shin, Sung-Hoon Joo, Seon-Keun Yoo, Seung-Hee Yoon
  • Patent number: 10937880
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 2, 2021
    Assignee: Acorn Semi, LLC
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 10886130
    Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Darwin Franseda Fan, Junting Liu-Norrod, Michael Mutch
  • Patent number: 10869396
    Abstract: In one embodiment, a motherboard to be cut, includes: a motherboard body provided, on a surface thereof, with a cutting line comprising a special-shaped cutting line section, wherein, a plurality of positional marker groups are provided on a portion of the surface where the special-shaped cutting line section is provided; each positional marker group includes a first marker assembly and a second marker assembly provided at both sides of the special-shaped cutting line section; and, in the arrangement direction of the first marker assembly and the second marker assembly, size of the first marker assembly is not less than tolerance size of a side of the special-shaped cutting line section where the first marker assembly is in, and size of the second marker assembly is not less than tolerance size of a side of the special-shaped cutting line section where the second marker assembly is in.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: December 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Fuzheng Xie, Junshuo Li, Binfeng Feng, Xiaoxia Liu, Meiling Piao
  • Patent number: 10847381
    Abstract: Laser annealing systems and methods with ultra-short dwell times are disclosed. The method includes locally pre-heating the wafer with a pre-heat line image and then rapidly scanning an annealing image relative to the pre-heat line image to define a scanning overlap region that has a dwell time is in the range from 10 ns to 500 ns. These ultra-short dwell times are useful for performing surface or subsurface melt annealing of product wafers because they prevent the device structures from reflowing.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Veeco Instruments Inc.
    Inventors: Andrew M. Hawryluk, Serguei Anikitchev
  • Patent number: 10823992
    Abstract: There is provided a liquid crystal display (LCD) device that prevents light leaks near spacers. The LCD device controls the optical transmissivity of a liquid crystal layer interposed between substrates disposed opposite each other, by means of an electric field generated in the layer-thickness direction of the liquid crystal layer. The LCD device includes spacers on a liquid-crystal-side surface of one substrate, signal lines formed on a liquid-crystal-side surface of the other substrate, an insulating film formed to cover the signal lines, and electrodes on the insulating film's upper surface. Each electrode contributes to controlling the optical transmissivity of the liquid crystal layer. Each spacer has a vertex surface disposed opposite to the signal lines. A portion of each electrode extends to the upper surface of a corresponding signal line. The extended portion is opposite to a part of a spacer's vertex surface disposed opposite to the corresponding signal line.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: November 3, 2020
    Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Kazuhiko Yanagawa, Yasushi Iwakabe, Yoshiaki Nakayoshi, Masatoshi Wakagi
  • Patent number: 10804407
    Abstract: A laser processing apparatus and a stack processing apparatus are provided. The laser processing apparatus can perform steps selectively by switching of optical paths. The steps are a step in which a first surface of a flat-plate structure is irradiated with a laser and a step in which a surface opposite to the first surface of the structure is irradiated with the laser. The laser is a linear laser whose shape on the irradiated surface is a rectangle. By laser irradiation performed while the structure is moved in the horizontal direction, the whole or a desired region of the first surface or the opposite surface of the structure can be processed.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 13, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata, Naoto Kusumoto
  • Patent number: 10763407
    Abstract: Alight emitting device includes a package, alight emitting element, and a light-transmissive encapsulant. The package has a top surface and a recessed portion formed with an opening at the top surface. The light emitting element is located on a bottom surface of the recessed portion. The light-transmissive encapsulant is supplied in the recessed portion. The package is provided with a groove formed in the top surface and surrounding the opening. A surface of the groove includes depressed portions and projecting portions. The encapsulant covers at least a part of the surface of the groove, and a portion of the encapsulant that covers the surface of the groove includes a surface irregularity.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: September 1, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Yoshio Ichihara, Mitsuhiro Isono
  • Patent number: 10686995
    Abstract: A light irradiation apparatus for irradiating an object with light, includes a plurality of line-shaped light blockers arranged at a predetermined center-to-center interval, and configured to at least partially block light, and a plurality of line-shaped light irradiators arranged to overlap some of the plurality of light blockers so as to irradiate the object with light. The plurality of light irradiators are arranged to form a period not less than twice as large as the center-to-center interval of the plurality of light blockers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 16, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takanori Uemura
  • Patent number: 10665504
    Abstract: Methods disclosed herein include scanning a focus spot formed by a laser beam over either a metal layer or IC structures that include a metal and a non-metal. The focus spot is scanned over a scan path that includes scan path segments that partially overlap. The focus spot has an irradiance and a dwell time selected to locally melt the metal layer or locally melt the metal of the IC structures without melting the non-metal. This results in rapid melting and recrystallization of the metal, which decreases the resistivity of the metal and results in improved performance of the IC chips being fabricated. Also disclosed is an example laser melt system for carrying out methods disclosed herein is also disclosed.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Veeco Instruments Inc.
    Inventors: Serguei Anikitchev, Andrew M. Hawryluk
  • Patent number: 10656483
    Abstract: A semiconductor apparatus (100) is provided with: a substrate (1); and a thin-film transistor (10). The thin-film transistor has: an oxide semiconductor layer (11) that includes a channel region (11a) and first and second contact regions (11b, 11c); a gate insulating layer (12) that is provided so as to cover the oxide semiconductor layer; a gate electrode (13) that is provided on the gate insulating layer and that overlaps the channel region via the gate insulating layer; a source electrode (14) that is electrically connected to the first contact region; and a drain electrode (15) that is electrically connected to the second contact region. This semiconductor apparatus is further provided with a light-shielding layer (2) arranged between the oxide semiconductor layer and the substrate, and the channel region is aligned to the part of the light-shielding layer overlapping the oxide semiconductor layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 19, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hiroshi Matsukizono
  • Patent number: 10629494
    Abstract: A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Yen-Chun Lin
  • Patent number: 10629637
    Abstract: To provide a semiconductor device in which a layer to be peeled is attached to a base having a curved surface, and a method of manufacturing the same, and more particularly, a display having a curved surface, and more specifically a light-emitting device having a light emitting element attached to a base with a curved surface. A layer to be peeled, which contains a light emitting element furnished to a substrate using a laminate of a first material layer which is a metallic layer or nitride layer, and a second material layer which is an oxide layer, is transferred onto a film, and then the film and the layer to be peeled are curved, to thereby produce a display having a curved surface.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 10608115
    Abstract: A laser beam irradiation device includes a light source that emits a laser beam; and a projection lens that irradiates a plurality of different areas of an amorphous silicon thin film attached to a thin-film transistor with the laser beam, wherein the projection lens irradiates the plurality of different areas of the amorphous silicon thin film with the laser beam such that a source electrode and a drain electrode of the thin-film transistor are connected in parallel to each other by a plurality of channel regions.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 31, 2020
    Assignee: V Technology Co., Ltd.
    Inventor: Michinobu Mizumura
  • Patent number: 10573205
    Abstract: A flexible organic EL display device includes a polycrystalline silicon layer in which an extent of alignment of a silicon crystal orientation by electron back scatter diffraction patterns with a 001 plane is greater than or equal to 3.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Masaki Yamanaka, Yohsuke Kanzaki, Seiji Kaneko, Masahiko Miwa
  • Patent number: 10535778
    Abstract: The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 14, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventors: Michinobu Mizumura, Makoto Hatanaka, Tetsuya Kiguchi
  • Patent number: 10535516
    Abstract: A method for depositing a semiconductor structure on a surface of a substrate is disclosed. The method may include: depositing a first group IVA semiconductor layer over a surface of the substrate; contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas; and depositing a second group IVA semiconductor layer over a surface of the first group IVA semiconductor layer. Related semiconductor structures are also disclosed.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: January 14, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: David Kohen, Nupur Bhargava, John Tolle, Vijay D'Costa
  • Patent number: 10529566
    Abstract: A display panel and a manufacturing method of a display panel are provided. The manufacturing method of a display panel includes: forming the nanoporous silicon oxide material on a substrate to form a nanoporous silicon oxide layer; forming the amorphous silicon material on the nanoporous silicon oxide layer to form an amorphous silicon layer; irradiating the amorphous silicon layer by a laser to crystallize the amorphous silicon layer to form a polycrystalline silicon layer; forming the gate oxide material on the polycrystalline silicon layer to form a gate oxide layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Yiqun Tian
  • Patent number: 10515800
    Abstract: A solid phase crystallization method of the present invention includes: providing amorphous silicon; heating the amorphous silicon to a first crystallization temperature; continuously heating the amorphous silicon to cause a temperature rise, in a first time period, from the first crystallization temperature to a second crystallization temperature, keeping the amorphous silicon in the second crystallization temperature for a predetermined time interval, causing a temperature drop of the amorphous silicon so as to gradually drop, in a second time period, from the second crystallization temperature to the first crystallization temperature, allowing continuous temperature drop of the amorphous silicon to reach the room temperature to thereby obtain low-temperature poly-silicon.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 24, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lei Yu, Songshan Li
  • Patent number: 10497755
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 10468613
    Abstract: Embodiment of the present disclosure provides a motherboard of flexible display panel, a cutting method thereof, a flexible display panel and a display device. The motherboard of flexible display panel includes: a plurality of display units; a space region, disposed to at least separate adjacent ones of the display unis; and a barrier strip, disposed in the space region and configured to stop a crack from extending towards the display units across the barrier strip.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongwei Tian, Yanan Niu, Yueping Zuo
  • Patent number: 10396207
    Abstract: There is provided a manufacturing method for a thin-film transistor substrate, which enables to excellently perform alignment between an annealed region of a semiconductor film and a mask pattern of a conductive film. The method comprises annealing a semiconductor film being formed on a gate insulation film covering a gate electrode with a laser beam by using a mask, the gate electrode being formed within a thin-film transistor substrate region on a substrate; forming a first alignment mark outside the thin-film transistor substrate region on the substrate, by irradiating the substrate through the mask with the laser beam; patterning the semiconductor film; forming a conductive film on the semiconductor film; positioning a photomask on the basis of the first alignment mark; and forming a source electrode and a drain electrode by patterning the conductive film through the photomask; wherein the first alignment mark is formed while annealing the semiconductor film.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 27, 2019
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Masahiro Kato
  • Patent number: 10347772
    Abstract: A display device includes a switching transistor, a driving transistor, a storage capacitor connected to the switching and driving transistors, and an organic light-emitting diode connected to the driving transistor. The driving transistor is connected to the switching transistor. The driving transistor includes a semiconductor layer having a channel region, first doped regions at sides of the channel region, and second doped regions doped with impurities of a concentration greater than the first doped regions. A first electrode layer is over an insulating layer, which covers the semiconductor layer. The electrode layer includes convex portions extending toward the first doped regions and covering an end of the channel region. At least one of the convex portions has a width greater than or equal to a width of the end of the channel region.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jongyun Kim
  • Patent number: 10236386
    Abstract: The present disclosure provides vertical hetero- and homo-junction tunnel FET (TFET) based on multi-layer black phosphorus (BP) and transition metal dichalcogenides.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 19, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Wenjuan Zhu, Shang-Chun Lu, Mohamed Mohamed
  • Patent number: 10199526
    Abstract: A method for forming a semiconductor device includes forming an amorphous semiconductor layer adjacent to a lightly doped region of a semiconductor wafer. The lightly doped region forms at least part of a back side of the semiconductor wafer, and the lightly doped region has a first conductivity type. The method further includes incorporating dopants into the amorphous semiconductor layer during or after forming the amorphous semiconductor layer. The method further includes annealing the amorphous semiconductor layer to transform at least a part of the amorphous semiconductor layer into a substantially monocrystalline semiconductor layer and to form a highly doped region in the monocrystalline semiconductor layer at the back side of the semiconductor wafer. The highly doped region has the first conductivity type.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Hacker
  • Patent number: 10192993
    Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanwei Ren, Chaochao Sun, Kunpeng Zhang, Yezhou Fang, Jingyi Xu
  • Patent number: 10130274
    Abstract: An implantable device for the electrical and/or pharmaceutical stimulation of the central nervous system, especially the spinal cord, is suggested. The device comprises a conformable substrate which is primarily composed of a flexible and stretchable polymer, and a plurality of flexible electrodes and conductive leads embedded in the conformable substrate. Not only the substrate, but also the leads are stretchable. The substrate may consist of PDMS, and the leads may consist of a conductive PDMS, in particular, PDMS with an electrically conductive filler material, and may optionally be metal-coated. The device defines a multi-electrode array which may be employed for neurostimulation in the epidural or subdural space of an animal or human.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: November 20, 2018
    Assignee: Ecole Polytechnique Federale De Lausanne (EPFL)
    Inventors: Janos Voros, Gregoire Courtine, Alexandre Larmagnac, Pavel Musienko
  • Patent number: 10074538
    Abstract: Apparatus and methods of treating a substrate with an amorphous semiconductor layer, or a semiconductor layer having small crystals, to form large crystals in the substrate are described. A treatment area of the substrate is identified and melted using a progressive melting process of delivering pulsed energy to the treatment area. The treatment area is then recrystallized using a progressive crystallization process of delivering pulsed energy to the area. The pulsed energy delivered during the progressive crystallization process is selected to convert the small crystals into large crystals as the melted material freezes.
    Type: Grant
    Filed: June 19, 2016
    Date of Patent: September 11, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bruce E. Adams, Aaron Muir Hunter, Stephen Moffatt
  • Patent number: 10049873
    Abstract: The invention provides a preparation method of a low temperature poly-silicon thin film, a preparation method of a low temperature poly-silicon thin film transistor, and a laser crystallization apparatus, and belongs to the technical field of display. The preparation method of a low temperature poly-silicon thin film of the invention comprises: forming an amorphous silicon thin film on a transparent substrate; and performing laser annealing on said amorphous silicon thin film from a side of said amorphous silicon thin film departing from said substrate, and performing laser irradiation from a side of said substrate departing from said amorphous silicon thin film, to form a low temperature poly-silicon thin film.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 14, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaowei Xu, Xiaolong Li
  • Patent number: 10038043
    Abstract: The present invention provides method for manufacturing an AMOLED backplane and a structure thereof. The method uses a drain terminal of a drive TFT to serve as an anode of AMOLED the anode, so that compared to the prior art, the steps of forming a planarization layer and an anode layer are eliminated and also, the same half-tone masking operation is used to form a pixel definition layer and photo spacers, whereby the method for manufacturing the AMOLED backplane according to the present invention requires only six masking operations and saves three masking operations compared to the prior art, thereby effectively simplifying the manufacturing process, improving manufacturing efficiency, and saving cost. The present invention provides a structure of an AMOLED backplane, which has a simple structure, is easy to manufacture, and has a low cost.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 31, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanjun Hsu
  • Patent number: 9966392
    Abstract: A laser annealing apparatus includes: a substrate supporting unit which supports a substrate; a laser beam irradiating unit which irradiates a line laser beam extending in a first direction to an amorphous silicon layer provided on the substrate on the substrate supporting unit; a substrate moving unit which moves the substrate supporting unit in a second direction crossing the first direction; and a first beam cutter and a second beam cutter, which are disposed between the substrate supporting unit and the laser beam irradiating unit, where the first and second beam cutters move to increase or decrease a shielded area of the substrate, which is an area of the substrate overlapping the first or second beam cutter and the line laser beam, to shield from at least a portion of the line laser beam irradiated to a portion of the substrate at an outer portion of the amorphous silicon layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hongro Lee, Chunghwan Lee
  • Patent number: 9966453
    Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Perrine Batude, Frederic Mazen, Benoit Sklenard
  • Patent number: 9898963
    Abstract: An organic light emitting display device is disclosed. One inventive aspect includes a plurality of pixels provided at a region sectioned by scan lines and data lines and an initialization power unit. The plurality of pixels are configured to control the amount of a current flowing from a first power source to a second power source through an organic light emitting diode in response to a data signal. The initialization power unit supplies initialization power to a driving transistor within each pixel circuit. The initialization power unit further controls the voltage of the initialization power supply to maintain a substantially constant voltage difference between the second power source and the initialization power.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 20, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Hyun Lee, Jong-Woon Kim
  • Patent number: 9842535
    Abstract: A display apparatus includes a display panel including a display area and a non-display area, a driving chip disposed in the non-display area, and a heat radiate sheet. The heat radiate sheet includes a first portion disposed on a rear surface of the display panel, a second portion disposed on the driving chip, and a connection portion connecting the first portion and the second portion.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 12, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minki Kim, HwanJin Kim
  • Patent number: 9837546
    Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoko Tsukamoto
  • Patent number: 9818606
    Abstract: The embodiments described herein generally relate to methods for forming an amorphous silicon structure that may be used in thin film transistor devices. In embodiments disclosed herein, the amorphous silicon layer is deposited using a silicon-based gas with an activation gas comprising a high concentration of inert gas and a low concentration of hydrogen-based gas. The activation gas combination allows for a good deposition profile of the amorphous silicon layer from the edge of the shadow frame which is translated to the polycrystalline silicon layer post-annealing.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: November 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Qunhua Wang, Lai Zhao, Soo Young Choi
  • Patent number: 9786700
    Abstract: The present disclosure relates to a LTPS TFT unit for liquid crystal modules and the manufacturing method thereof. The manufacturing method includes: forming a SiNx layer on a glass substrate; forming a SiOx layer and an a-Si layer on the SiNx layer in sequence; scanning the a-Si layer by laser beams to remove hydrogen within the a-Si layer; adopting excimer laser to re-crystallization anneal the a-Si layer to form the polysilicon layer; forming a gate insulation layer on the polysilicon layer; forming a gate on the gate insulation layer; and forming a drain insulation layer on the gate.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: October 10, 2017
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Zijian Li
  • Patent number: 9768279
    Abstract: To provide a transistor formed using an oxide semiconductor film with reduced oxygen vacancies. To provide a semiconductor device that operates at high speed. To provide a highly reliable semiconductor device. To provide a miniaturized semiconductor device. The semiconductor device includes an oxide semiconductor film; a gate electrode overlapping with the oxide semiconductor film; a gate insulating film between the oxide semiconductor film and the gate electrode; and a protective insulating film that is above the oxide semiconductor film, the gate electrode, and the gate insulating film and includes a region containing phosphorus or boron.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Yuichi Sato, Yuta Endo
  • Patent number: 9748284
    Abstract: Embodiments of the present invention provide a thin film transistor, a method for fabricating the same and an array substrate. The thin film transistor comprises a base substrate and an active region and a plurality of reflective plates formed on the base substrate, wherein the plurality of reflective plates are spaced apart from each other and provided at least at positions corresponding to the active region, the active region comprises polysilicon, and the polysilicon in the active region is formed by irradiating an amorphous silicon layer with laser emitted from a side of the amorphous silicon layer away from the reflective plates.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 29, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qianqian Bu
  • Patent number: 9678501
    Abstract: Systems and methods for fuel cell stack part serialization and tracking. In an embodiment, a barcode may be applied to a fuel cell stack part which may identify the fuel cell stack part. In an embodiment, the barcode may be applied as ink on a green fuel cell stack part prior to sintering. In an embodiment, a portion of a fuel cell stack part may be imaged and pattern recognition techniques may be utilized to identify the fuel cell stack part based on the unique features of fuel cell stack part. In an embodiment, portion of a fuel cell stack part may be measured to generate one or more series of unique volume/area values and one or more series of unique volume/area values may be utilized to identify the fuel cell stack part.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: June 13, 2017
    Assignee: BLOOM ENERGY CORPORATION
    Inventors: Stephen Couse, Tulin Akin, Matthias Gottmann, Harald Herchen, Arne Ballantine
  • Patent number: 9673334
    Abstract: A LTPS TFT and a TFT substrate are disclosed. The LTPS TFT includes: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, and the polysilicon layer covers the first gate, wherein the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the LTPS TFT has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage. In this way, the feed through voltage may be reduced such that the TFT performance is enhanced.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Chiu-chuan Chen
  • Patent number: 9647074
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 9, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Patent number: 9633845
    Abstract: A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joowoan Cho, Byoungho Cheong, Byoungkwon Choo, Jeongkyun Na, Sanghoon Ahn, Hyunjin Cho