Including Recrystallization Step Patents (Class 438/166)
  • Patent number: 10763407
    Abstract: Alight emitting device includes a package, alight emitting element, and a light-transmissive encapsulant. The package has a top surface and a recessed portion formed with an opening at the top surface. The light emitting element is located on a bottom surface of the recessed portion. The light-transmissive encapsulant is supplied in the recessed portion. The package is provided with a groove formed in the top surface and surrounding the opening. A surface of the groove includes depressed portions and projecting portions. The encapsulant covers at least a part of the surface of the groove, and a portion of the encapsulant that covers the surface of the groove includes a surface irregularity.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: September 1, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Yoshio Ichihara, Mitsuhiro Isono
  • Patent number: 10686995
    Abstract: A light irradiation apparatus for irradiating an object with light, includes a plurality of line-shaped light blockers arranged at a predetermined center-to-center interval, and configured to at least partially block light, and a plurality of line-shaped light irradiators arranged to overlap some of the plurality of light blockers so as to irradiate the object with light. The plurality of light irradiators are arranged to form a period not less than twice as large as the center-to-center interval of the plurality of light blockers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 16, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takanori Uemura
  • Patent number: 10665504
    Abstract: Methods disclosed herein include scanning a focus spot formed by a laser beam over either a metal layer or IC structures that include a metal and a non-metal. The focus spot is scanned over a scan path that includes scan path segments that partially overlap. The focus spot has an irradiance and a dwell time selected to locally melt the metal layer or locally melt the metal of the IC structures without melting the non-metal. This results in rapid melting and recrystallization of the metal, which decreases the resistivity of the metal and results in improved performance of the IC chips being fabricated. Also disclosed is an example laser melt system for carrying out methods disclosed herein is also disclosed.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Veeco Instruments Inc.
    Inventors: Serguei Anikitchev, Andrew M. Hawryluk
  • Patent number: 10656483
    Abstract: A semiconductor apparatus (100) is provided with: a substrate (1); and a thin-film transistor (10). The thin-film transistor has: an oxide semiconductor layer (11) that includes a channel region (11a) and first and second contact regions (11b, 11c); a gate insulating layer (12) that is provided so as to cover the oxide semiconductor layer; a gate electrode (13) that is provided on the gate insulating layer and that overlaps the channel region via the gate insulating layer; a source electrode (14) that is electrically connected to the first contact region; and a drain electrode (15) that is electrically connected to the second contact region. This semiconductor apparatus is further provided with a light-shielding layer (2) arranged between the oxide semiconductor layer and the substrate, and the channel region is aligned to the part of the light-shielding layer overlapping the oxide semiconductor layer.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 19, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hiroshi Matsukizono
  • Patent number: 10629494
    Abstract: A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Yen-Chun Lin
  • Patent number: 10629637
    Abstract: To provide a semiconductor device in which a layer to be peeled is attached to a base having a curved surface, and a method of manufacturing the same, and more particularly, a display having a curved surface, and more specifically a light-emitting device having a light emitting element attached to a base with a curved surface. A layer to be peeled, which contains a light emitting element furnished to a substrate using a laminate of a first material layer which is a metallic layer or nitride layer, and a second material layer which is an oxide layer, is transferred onto a film, and then the film and the layer to be peeled are curved, to thereby produce a display having a curved surface.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Hideaki Kuwabara, Shunpei Yamazaki
  • Patent number: 10608115
    Abstract: A laser beam irradiation device includes a light source that emits a laser beam; and a projection lens that irradiates a plurality of different areas of an amorphous silicon thin film attached to a thin-film transistor with the laser beam, wherein the projection lens irradiates the plurality of different areas of the amorphous silicon thin film with the laser beam such that a source electrode and a drain electrode of the thin-film transistor are connected in parallel to each other by a plurality of channel regions.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 31, 2020
    Assignee: V Technology Co., Ltd.
    Inventor: Michinobu Mizumura
  • Patent number: 10573205
    Abstract: A flexible organic EL display device includes a polycrystalline silicon layer in which an extent of alignment of a silicon crystal orientation by electron back scatter diffraction patterns with a 001 plane is greater than or equal to 3.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Masaki Yamanaka, Yohsuke Kanzaki, Seiji Kaneko, Masahiko Miwa
  • Patent number: 10535778
    Abstract: The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 14, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventors: Michinobu Mizumura, Makoto Hatanaka, Tetsuya Kiguchi
  • Patent number: 10535516
    Abstract: A method for depositing a semiconductor structure on a surface of a substrate is disclosed. The method may include: depositing a first group IVA semiconductor layer over a surface of the substrate; contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas; and depositing a second group IVA semiconductor layer over a surface of the first group IVA semiconductor layer. Related semiconductor structures are also disclosed.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: January 14, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: David Kohen, Nupur Bhargava, John Tolle, Vijay D'Costa
  • Patent number: 10529566
    Abstract: A display panel and a manufacturing method of a display panel are provided. The manufacturing method of a display panel includes: forming the nanoporous silicon oxide material on a substrate to form a nanoporous silicon oxide layer; forming the amorphous silicon material on the nanoporous silicon oxide layer to form an amorphous silicon layer; irradiating the amorphous silicon layer by a laser to crystallize the amorphous silicon layer to form a polycrystalline silicon layer; forming the gate oxide material on the polycrystalline silicon layer to form a gate oxide layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 7, 2020
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Yiqun Tian
  • Patent number: 10515800
    Abstract: A solid phase crystallization method of the present invention includes: providing amorphous silicon; heating the amorphous silicon to a first crystallization temperature; continuously heating the amorphous silicon to cause a temperature rise, in a first time period, from the first crystallization temperature to a second crystallization temperature, keeping the amorphous silicon in the second crystallization temperature for a predetermined time interval, causing a temperature drop of the amorphous silicon so as to gradually drop, in a second time period, from the second crystallization temperature to the first crystallization temperature, allowing continuous temperature drop of the amorphous silicon to reach the room temperature to thereby obtain low-temperature poly-silicon.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: December 24, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lei Yu, Songshan Li
  • Patent number: 10497755
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama
  • Patent number: 10468613
    Abstract: Embodiment of the present disclosure provides a motherboard of flexible display panel, a cutting method thereof, a flexible display panel and a display device. The motherboard of flexible display panel includes: a plurality of display units; a space region, disposed to at least separate adjacent ones of the display unis; and a barrier strip, disposed in the space region and configured to stop a crack from extending towards the display units across the barrier strip.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongwei Tian, Yanan Niu, Yueping Zuo
  • Patent number: 10396207
    Abstract: There is provided a manufacturing method for a thin-film transistor substrate, which enables to excellently perform alignment between an annealed region of a semiconductor film and a mask pattern of a conductive film. The method comprises annealing a semiconductor film being formed on a gate insulation film covering a gate electrode with a laser beam by using a mask, the gate electrode being formed within a thin-film transistor substrate region on a substrate; forming a first alignment mark outside the thin-film transistor substrate region on the substrate, by irradiating the substrate through the mask with the laser beam; patterning the semiconductor film; forming a conductive film on the semiconductor film; positioning a photomask on the basis of the first alignment mark; and forming a source electrode and a drain electrode by patterning the conductive film through the photomask; wherein the first alignment mark is formed while annealing the semiconductor film.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 27, 2019
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Masahiro Kato
  • Patent number: 10347772
    Abstract: A display device includes a switching transistor, a driving transistor, a storage capacitor connected to the switching and driving transistors, and an organic light-emitting diode connected to the driving transistor. The driving transistor is connected to the switching transistor. The driving transistor includes a semiconductor layer having a channel region, first doped regions at sides of the channel region, and second doped regions doped with impurities of a concentration greater than the first doped regions. A first electrode layer is over an insulating layer, which covers the semiconductor layer. The electrode layer includes convex portions extending toward the first doped regions and covering an end of the channel region. At least one of the convex portions has a width greater than or equal to a width of the end of the channel region.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jongyun Kim
  • Patent number: 10236386
    Abstract: The present disclosure provides vertical hetero- and homo-junction tunnel FET (TFET) based on multi-layer black phosphorus (BP) and transition metal dichalcogenides.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 19, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Wenjuan Zhu, Shang-Chun Lu, Mohamed Mohamed
  • Patent number: 10199526
    Abstract: A method for forming a semiconductor device includes forming an amorphous semiconductor layer adjacent to a lightly doped region of a semiconductor wafer. The lightly doped region forms at least part of a back side of the semiconductor wafer, and the lightly doped region has a first conductivity type. The method further includes incorporating dopants into the amorphous semiconductor layer during or after forming the amorphous semiconductor layer. The method further includes annealing the amorphous semiconductor layer to transform at least a part of the amorphous semiconductor layer into a substantially monocrystalline semiconductor layer and to form a highly doped region in the monocrystalline semiconductor layer at the back side of the semiconductor wafer. The highly doped region has the first conductivity type.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Hacker
  • Patent number: 10192993
    Abstract: The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanwei Ren, Chaochao Sun, Kunpeng Zhang, Yezhou Fang, Jingyi Xu
  • Patent number: 10130274
    Abstract: An implantable device for the electrical and/or pharmaceutical stimulation of the central nervous system, especially the spinal cord, is suggested. The device comprises a conformable substrate which is primarily composed of a flexible and stretchable polymer, and a plurality of flexible electrodes and conductive leads embedded in the conformable substrate. Not only the substrate, but also the leads are stretchable. The substrate may consist of PDMS, and the leads may consist of a conductive PDMS, in particular, PDMS with an electrically conductive filler material, and may optionally be metal-coated. The device defines a multi-electrode array which may be employed for neurostimulation in the epidural or subdural space of an animal or human.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: November 20, 2018
    Assignee: Ecole Polytechnique Federale De Lausanne (EPFL)
    Inventors: Janos Voros, Gregoire Courtine, Alexandre Larmagnac, Pavel Musienko
  • Patent number: 10074538
    Abstract: Apparatus and methods of treating a substrate with an amorphous semiconductor layer, or a semiconductor layer having small crystals, to form large crystals in the substrate are described. A treatment area of the substrate is identified and melted using a progressive melting process of delivering pulsed energy to the treatment area. The treatment area is then recrystallized using a progressive crystallization process of delivering pulsed energy to the area. The pulsed energy delivered during the progressive crystallization process is selected to convert the small crystals into large crystals as the melted material freezes.
    Type: Grant
    Filed: June 19, 2016
    Date of Patent: September 11, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bruce E. Adams, Aaron Muir Hunter, Stephen Moffatt
  • Patent number: 10049873
    Abstract: The invention provides a preparation method of a low temperature poly-silicon thin film, a preparation method of a low temperature poly-silicon thin film transistor, and a laser crystallization apparatus, and belongs to the technical field of display. The preparation method of a low temperature poly-silicon thin film of the invention comprises: forming an amorphous silicon thin film on a transparent substrate; and performing laser annealing on said amorphous silicon thin film from a side of said amorphous silicon thin film departing from said substrate, and performing laser irradiation from a side of said substrate departing from said amorphous silicon thin film, to form a low temperature poly-silicon thin film.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: August 14, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaowei Xu, Xiaolong Li
  • Patent number: 10038043
    Abstract: The present invention provides method for manufacturing an AMOLED backplane and a structure thereof. The method uses a drain terminal of a drive TFT to serve as an anode of AMOLED the anode, so that compared to the prior art, the steps of forming a planarization layer and an anode layer are eliminated and also, the same half-tone masking operation is used to form a pixel definition layer and photo spacers, whereby the method for manufacturing the AMOLED backplane according to the present invention requires only six masking operations and saves three masking operations compared to the prior art, thereby effectively simplifying the manufacturing process, improving manufacturing efficiency, and saving cost. The present invention provides a structure of an AMOLED backplane, which has a simple structure, is easy to manufacture, and has a low cost.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: July 31, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanjun Hsu
  • Patent number: 9966453
    Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Perrine Batude, Frederic Mazen, Benoit Sklenard
  • Patent number: 9966392
    Abstract: A laser annealing apparatus includes: a substrate supporting unit which supports a substrate; a laser beam irradiating unit which irradiates a line laser beam extending in a first direction to an amorphous silicon layer provided on the substrate on the substrate supporting unit; a substrate moving unit which moves the substrate supporting unit in a second direction crossing the first direction; and a first beam cutter and a second beam cutter, which are disposed between the substrate supporting unit and the laser beam irradiating unit, where the first and second beam cutters move to increase or decrease a shielded area of the substrate, which is an area of the substrate overlapping the first or second beam cutter and the line laser beam, to shield from at least a portion of the line laser beam irradiated to a portion of the substrate at an outer portion of the amorphous silicon layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hongro Lee, Chunghwan Lee
  • Patent number: 9898963
    Abstract: An organic light emitting display device is disclosed. One inventive aspect includes a plurality of pixels provided at a region sectioned by scan lines and data lines and an initialization power unit. The plurality of pixels are configured to control the amount of a current flowing from a first power source to a second power source through an organic light emitting diode in response to a data signal. The initialization power unit supplies initialization power to a driving transistor within each pixel circuit. The initialization power unit further controls the voltage of the initialization power supply to maintain a substantially constant voltage difference between the second power source and the initialization power.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 20, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Hyun Lee, Jong-Woon Kim
  • Patent number: 9842535
    Abstract: A display apparatus includes a display panel including a display area and a non-display area, a driving chip disposed in the non-display area, and a heat radiate sheet. The heat radiate sheet includes a first portion disposed on a rear surface of the display panel, a second portion disposed on the driving chip, and a connection portion connecting the first portion and the second portion.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 12, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minki Kim, HwanJin Kim
  • Patent number: 9837546
    Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoko Tsukamoto
  • Patent number: 9818606
    Abstract: The embodiments described herein generally relate to methods for forming an amorphous silicon structure that may be used in thin film transistor devices. In embodiments disclosed herein, the amorphous silicon layer is deposited using a silicon-based gas with an activation gas comprising a high concentration of inert gas and a low concentration of hydrogen-based gas. The activation gas combination allows for a good deposition profile of the amorphous silicon layer from the edge of the shadow frame which is translated to the polycrystalline silicon layer post-annealing.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: November 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Qunhua Wang, Lai Zhao, Soo Young Choi
  • Patent number: 9786700
    Abstract: The present disclosure relates to a LTPS TFT unit for liquid crystal modules and the manufacturing method thereof. The manufacturing method includes: forming a SiNx layer on a glass substrate; forming a SiOx layer and an a-Si layer on the SiNx layer in sequence; scanning the a-Si layer by laser beams to remove hydrogen within the a-Si layer; adopting excimer laser to re-crystallization anneal the a-Si layer to form the polysilicon layer; forming a gate insulation layer on the polysilicon layer; forming a gate on the gate insulation layer; and forming a drain insulation layer on the gate.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: October 10, 2017
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Zijian Li
  • Patent number: 9768279
    Abstract: To provide a transistor formed using an oxide semiconductor film with reduced oxygen vacancies. To provide a semiconductor device that operates at high speed. To provide a highly reliable semiconductor device. To provide a miniaturized semiconductor device. The semiconductor device includes an oxide semiconductor film; a gate electrode overlapping with the oxide semiconductor film; a gate insulating film between the oxide semiconductor film and the gate electrode; and a protective insulating film that is above the oxide semiconductor film, the gate electrode, and the gate insulating film and includes a region containing phosphorus or boron.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Yuichi Sato, Yuta Endo
  • Patent number: 9748284
    Abstract: Embodiments of the present invention provide a thin film transistor, a method for fabricating the same and an array substrate. The thin film transistor comprises a base substrate and an active region and a plurality of reflective plates formed on the base substrate, wherein the plurality of reflective plates are spaced apart from each other and provided at least at positions corresponding to the active region, the active region comprises polysilicon, and the polysilicon in the active region is formed by irradiating an amorphous silicon layer with laser emitted from a side of the amorphous silicon layer away from the reflective plates.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 29, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qianqian Bu
  • Patent number: 9678501
    Abstract: Systems and methods for fuel cell stack part serialization and tracking. In an embodiment, a barcode may be applied to a fuel cell stack part which may identify the fuel cell stack part. In an embodiment, the barcode may be applied as ink on a green fuel cell stack part prior to sintering. In an embodiment, a portion of a fuel cell stack part may be imaged and pattern recognition techniques may be utilized to identify the fuel cell stack part based on the unique features of fuel cell stack part. In an embodiment, portion of a fuel cell stack part may be measured to generate one or more series of unique volume/area values and one or more series of unique volume/area values may be utilized to identify the fuel cell stack part.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: June 13, 2017
    Assignee: BLOOM ENERGY CORPORATION
    Inventors: Stephen Couse, Tulin Akin, Matthias Gottmann, Harald Herchen, Arne Ballantine
  • Patent number: 9673334
    Abstract: A LTPS TFT and a TFT substrate are disclosed. The LTPS TFT includes: a substrate; a first gate arranged on the substrate; a polysilicon layer arranged on the substrates, and the polysilicon layer covers the first gate, wherein the polysilicon layer comprises a source area, a drain area, and a trench area formed between the source area and the drain area; a second gate arranged on the polysilicon layer; wherein when the LTPS TFT has been driven, the first gate and the second gate are respectively applied with a first voltage and a second voltage, and a polarity of the first voltage is opposite to the polarity of the second voltage. In this way, the feed through voltage may be reduced such that the TFT performance is enhanced.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Chiu-chuan Chen
  • Patent number: 9647074
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 9, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Patent number: 9633845
    Abstract: A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joowoan Cho, Byoungho Cheong, Byoungkwon Choo, Jeongkyun Na, Sanghoon Ahn, Hyunjin Cho
  • Patent number: 9530644
    Abstract: The present invention provides a polysilicon manufacturing method that enhances homogeneity of a polysilicon layer, including (1) forming a amorphous silicon layer (30) on a substrate (10); (2) dividing the amorphous silicon layer (30) into a plurality of areas and measuring a film thickness of the amorphous silicon layer (30) in each of the areas: (3) comparing the measured film thickness of each of the areas with a predetermined film thickness so as to identify and define ones of the areas of which the measured film thicknesses are greater than a predetermined film thickness as excessive-film-thickness areas (42); (4) spraying an etchant liquid to rinse the amorphous silicon layer (30) of the excessive-film-thickness areas (42) in order to etch off a portion of the amorphous silicon layer (30) of each of the excessive-film-thickness areas (42) and at the same time, spraying pure water to rinse remaining ones of the areas so as to make the film thickness of each of the areas of the amorphous silicon layer (3
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: December 27, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xiang Zhang
  • Patent number: 9508889
    Abstract: A method is presented for forming a Ge containing layer on a Si substrate. The method includes providing a crystalline Si substrate having a surface that has a crystallographic orientation, heating the Si substrate in a vacuum environment, exposing the Si substrate to a surfactant that is suitable for growth of the Ge containing layer on the crystalline Si using surfactant mediation, and thereafter growing the Ge containing layer on the surface of the heated Si substrate using a suitable sputtering technique. The conditions of the growth of the Ge containing layer are selected such that a thin Ge containing layer is formed on the surface of the Si substrate. The thin Ge containing layer has a surface that has crystallographic properties suitable for epitaxial growth of a layer of a further material on the surface of the thin Ge containing layer.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: November 29, 2016
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Martin Green, Xiaojing Hao, Chao-Yang Tsao
  • Patent number: 9468996
    Abstract: A method of repairing a substrate that may prevent a metal layer from being corroded. A substrate including a metal layer and an insulating layer on the metal layer is first provided. Then, a laser beam having a wavelength range having a high transmittance with respect to the insulating layer is irradiated to selectively remove a portion of the metal layer. Also, a first laser beam is irradiated to remove a portion of the metal layer and a portion of the insulating layer, and then a second laser beam is irradiated onto side surfaces of the exposed insulating layer to melt the insulating layer, thereby forming a corrosion preventing layer covering the metal layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: October 18, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sung Bae Ju
  • Patent number: 9455196
    Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 27, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 9437830
    Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate capable of being bent in a first direction and an insulating layer including a first opening pattern positioned on the flexible substrate and extending in a second direction crossing the first direction.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae Woong Kim, Hyun Woo Koo, Young Gug Seol
  • Patent number: 9419243
    Abstract: Provided is an organic light-emitting diode (OLED) display including: a first plastic layer; a first barrier layer formed on the first plastic layer; a first intermediate layer formed on the first barrier layer; a second plastic layer formed on the intermediate layer; an OLED layer formed on the second plastic layer; and a thin-film encapsulation layer encapsulating the OLED layer.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 16, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Hwan Park, Jae-Seob Lee, Gyoo-Chul Jo, Jin-Kyu Kang, Jun Heo, Sung-Guk An, Sung-Sik Bae
  • Patent number: 9384965
    Abstract: According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface. The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: July 5, 2016
    Assignee: Japan Display Inc.
    Inventors: Naoya Ito, Toshihide Jinnai, Hirofumi Mizukoshi
  • Patent number: 9373646
    Abstract: The present invention discloses a polysilicon TFT device and the manufacturing method thereof. The polysilicon TFT device comprises: a scanning line and a data line arranged alternately; a semiconductor layer electrically connected with the scanning line and the data line; and a pixel electrode electrically connected with the semiconductor layer. Multiple channel regions and multiple doped regions are provided sequentially with interval between the connecting point of the semiconductor layer with the data line and the connecting point of the semiconductor layer with the pixel electrode, the channel regions are the portions of the semiconductor layer overlapping the scanning line, the rest portions are the doped regions, the width of at least one said doped region is 0.5˜3 ?m, the ion doping concentration is 2*E11˜5*E15.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: June 21, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Guo Zhao
  • Patent number: 9373511
    Abstract: Apparatus and methods of treating a substrate with an amorphous semiconductor layer, or a semiconductor layer having small crystals, to form large crystals in the substrate are described. A treatment area of the substrate is identified and melted using a progressive melting process of delivering pulsed energy to the treatment area. The treatment area is then recrystallized using a progressive crystallization process of delivering pulsed energy to the area. The pulsed energy delivered during the progressive crystallization process is selected to convert the small crystals into large crystals as the melted material freezes.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 21, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Bruce E. Adams, Aaron Muir Hunter, Stephen Moffatt
  • Patent number: 9336709
    Abstract: An electronic device may be provided with a display. The display may be formed from an array of organic light-emitting diode display pixels. Each display pixel may have an organic light-emitting diode having an anode and a cathode and may have an associated pixel circuit for controlling the light-emitting diode. The anodes may be formed from patches of metal arranged in an array on the display. The display pixels may be controlled using data lines and gate lines. The gate lines may control thin-film transistors in the pixel circuits. Gate driver circuitry along the left and right edges of the display may supply signals to the gate lines. The pixel circuits may be located in the center of the display between the gate driver circuitry. Some of the anodes may overlap the pixel circuits and some of the anodes may overlap the gate driver circuitry.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 10, 2016
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Shih-Chang Chang, Tsung-Ting Tsai
  • Patent number: 9330925
    Abstract: A thin-film transistor includes a substrate, a gate electrode over the substrate, an insulating layer over the gate electrode, and a semiconductor layer over the insulating layer. The semiconductor layer includes a channel region, a source region, and a drain region. A source electrode is over the source region, and a drain electrode is over the drain region. The source electrode and the drain electrode each comprise Ni and a metal other than Ni. The channel region, the source region, and the drain region comprise at least one of a polycrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer and a microcrystalline silicon that is formed by crystallizing an amorphous silicon layer by thermally diffusing the Ni in the source electrode and the drain electrode into the semiconductor layer.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 3, 2016
    Assignee: JOLED INC.
    Inventors: Tohru Saitoh, Takaaki Ukeda, Kazunori Komori, Sadayoshi Hotta
  • Patent number: 9318329
    Abstract: Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kanamori Kohji, Young-Woo Park, Jin-Taek Park, Jae-Duk Lee
  • Patent number: 9305984
    Abstract: A method of manufacturing a flexible display includes: forming a first barrier layer on a flexible substrate; forming a second barrier layer including silicon nitride on the first barrier layer; releasing stress of the second barrier layer; forming a first buffer layer including silicon nitride on the second barrier layer; forming a second buffer layer on the first buffer layer; and forming a thin film transistor on the second buffer layer.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin Gyu Kang
  • Patent number: 9299565
    Abstract: In a method for producing a solar cell having a substrate made of crystalline silicon, on a surface of the Si substrate, a locally defined n-doped emitter region is produced by full-surface cold coating of the surface using a P-containing coating, followed by a local laser beam-doping of P atoms from the P-containing coating, and subsequent thermal driving in of the P atoms, starting from the doping-in region.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: March 29, 2016
    Assignee: SolarWorld Industries Thueringen GmbH
    Inventor: Tim Boescke