Optical Characteristic Sensed Patents (Class 438/16)
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Patent number: 8956886Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.Type: GrantFiled: March 11, 2014Date of Patent: February 17, 2015Assignee: Applied Materials, Inc.Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
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Patent number: 8958061Abstract: A method for characterizing a surface comprises rotating a carrier about an axis of rotation where the carrier has a top surface adapted to hold at least one semiconductor wafer with a major surface of the wafer extending generally transverse to the axis of rotation. A surface characterization tool is moved over a plurality of positions relative to the top surface of the carrier, where a measurement location over the top surface of the carrier is changed while said top surface of the carrier is heated to a predetermined temperature. Characterization signals over the plurality of positions with the surface characterization tool are produced and contain information about the heated top surface of the carrier, or when semiconductor wafers are held on the carrier, information about the semiconductor wafer can also be obtained.Type: GrantFiled: May 30, 2012Date of Patent: February 17, 2015Assignee: Veeco Instruments Inc.Inventors: Vadim Boguslavskiy, Joshua Mangum, Matthew King, Earl Marcelo, Eric A. Armour, Alexander I. Gurary, William E. Quinn, Guray Tas
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Patent number: 8956897Abstract: In a method for producing an optoelectronic component, a growth substrate having a first coefficient of thermal expansion is provided. A multilayered buffer layer sequence is applied thereto. A layer sequence having a second coefficient of thermal expansion—different than the first coefficient of thermal expansion—is subsequently deposited epitaxially. It furthermore comprises an active layer for emitting electromagnetic radiation. A carrier substrate is subsequently applied on the epitaxially deposited layer sequence. The growth substrate is removed and the multilayered buffer layer sequence is structured in order to increase a coupling-out of electromagnetic radiation. Finally, contact is made with the epitaxially deposited layer sequence.Type: GrantFiled: August 30, 2012Date of Patent: February 17, 2015Assignee: Osram Opto Semiconductors GmbHInventors: Patrick Rode, Martin Strassburg, Karl Engl, Lutz Höppel
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Patent number: 8951813Abstract: A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type film thickness measuring device prior to cleaning and drying of the substrate; measuring a thickness of the film by the wet-type film thickness measuring device; comparing the thickness with a predetermined target value; and if the thickness has not reached the predetermined target value, performing re-polishing of the substrate in the polishing section prior to cleaning and drying of the substrate.Type: GrantFiled: July 9, 2013Date of Patent: February 10, 2015Assignee: Ebara CorporationInventors: Takeshi Iizumi, Katsuhide Watanabe, Yoichi Kobayashi
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Patent number: 8953868Abstract: A defect inspection method comprising: picking up an image of a subject under inspection to thereby acquire an inspection image; extracting multiple templates corresponding to multiple regions, respectively from design data of the subject under inspection; finding a first misregistration amount between the inspection image and the design data using a first template as any one template selected from among the plural templates; finding a second misregistration amount between the inspection image and the design data using a second template other than the first template, the second template being selected from among the plural templates, and the first misregistration-amount; and converting the design data, misregistration thereof being corrected using the first misregistration-amount, and the second misregistration-amount, into a design data image, and comparing the design data image with the inspection image to thereby detect a defect of the subject under inspection.Type: GrantFiled: May 30, 2013Date of Patent: February 10, 2015Assignee: Hitachi High-Technologies CorporationInventors: Shinya Murakami, Chie Shishido, Takashi Hiroi, Taku Ninomiya, Tsuyoshi Minakawa, Atsushi Miyamoto
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Publication number: 20150037915Abstract: In embodiments, a method of laser scribing a mask disposed over a semiconductor wafer includes determining a height of the semiconductor over which a mask layer is disposed prior to laser scribing the mask layer. In one embodiment the method includes: determining a height of the semiconductor wafer under the mask in a dicing street using an optical sensor and patterning the mask with a laser scribing process. The laser scribing process focuses a scribing laser beam at a plane corresponding to the determined height of the semiconductor wafer in the dicing street. Examples of determining the height of the semiconductor wafer can include directing a laser beam to the dicing street of the semiconductor wafer, which is transmitted through the mask and reflected from the wafer, and identifying an image on a surface of the wafer under the mask with a camera.Type: ApplicationFiled: September 24, 2013Publication date: February 5, 2015Inventors: Wei-Sheng LEI, Brad Eaton, Apama IYER, Madhava Rao Yalamanchili, Ajay Kumar
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Patent number: 8945939Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.Type: GrantFiled: November 18, 2013Date of Patent: February 3, 2015Assignee: Ecolab USA Inc.Inventors: Amy M. Tseng, Brian V. Jenkins, Robert Mack
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Patent number: 8945954Abstract: There is provided an inspection method for inspecting a substrate supporting portion configured to support a substrate during an exposure performed by an exposure apparatus, the method including: irradiating a surface of the exposed substrate with an illumination light beam; detecting reflected light from a pattern in the irradiated surface; determining a focusing state at the time of exposing the pattern of the substrate based on the detected reflected light; and inspecting a state of the substrate supporting portion based on the focusing state.Type: GrantFiled: December 14, 2011Date of Patent: February 3, 2015Assignee: Nikon CorporationInventor: Kazuhiko Fukazawa
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Patent number: 8945955Abstract: A method for changing reflectance or resistance of a region in an optoelectronic memory device. Changing the reflectance of the region includes sending an electric current through the region to cause a reflectance change in the region. Changing the resistance of the region includes: projecting a laser beam at a first beam intensity on the region, resulting in the region changing from a first to a second different resistance value; electrically reading the second resistance value during which an optical signal carried by the laser beam has a first digital value; after electrically reading the second resistance value, the laser beam is projected at a second beam intensity on the region resulting in the region changing from the second to the first resistance value; and electrically reading the first resistance value of the region while the laser beam is being projected on the region at the second beam intensity.Type: GrantFiled: February 13, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Fen Chen, Richard Steven Kontra, Tom C. Lee, Theodore M. Levin, Christopher David Muzzy, Timothy Dooling Sullivan
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Patent number: 8940551Abstract: The present invention provides a method for monitoring a contact hole etching process of a TFT substrate, which includes: (1) providing a substrate having a first metal layer and a monitoring machine; (2) providing a target value of reflection rate of the substrate having the first metal layer; (3) applying a masking operation to patternize the first metal layer for forming a gate terminal; (4) forming a gate insulation layer on the gate terminal; and (5) forming a contact hole in the gate insulation layer through etching and simultaneously operating the monitoring machine to measure the reflection rate of a bottom of the contact hole, whereby when the reflection rate of the bottom of the contact hole is substantially equal to the target value, the etching operation is stopped. The variation of reflection rate of the metal layer is monitored to identify if the insulation layer is completely etched away.Type: GrantFiled: October 24, 2012Date of Patent: January 27, 2015Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Xiangdeng Que
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Patent number: 8941742Abstract: Provided is a luminance measurement method for accurately measuring luminance of each pixel even if pixel images of a display panel overlap each other on an imaging surface of a camera. A central exposure factor indicating luminance of the central part of the pixel image is calculated on the basis of an output of a picture element corresponding to the central part. A peripheral exposure factor indicating luminance of the peripheral part of the pixel image is calculated on the basis of an output of picture elements corresponding to the peripheral part of the pixel image is calculated, all pixels of the display panel are sorted into a plurality of groups, sequentially turned on one group after another, and imaged by the camera, and the luminance of all the pixels of the display panel is calculated based on this imaged image, the central exposure factor, and the peripheral exposure factor.Type: GrantFiled: June 19, 2014Date of Patent: January 27, 2015Assignee: IIX Inc.Inventor: Hiroshi Murase
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Patent number: 8940554Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.Type: GrantFiled: January 27, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Nathaniel C. Berliner, Kangguo Cheng, Toshiharu Furukawa, Douglas C. La Tulipe, Jr., William R. Tonti
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Publication number: 20150024521Abstract: There is provided a plasma processing apparatus which compares a plurality of patterns detected using an interference light intensity pattern using a wavelength from at least one preset film of the plurality of film layers as a parameter and an intensity pattern using a wavelength of light from the other film as a parameter and an light intensity pattern from inside the processing chamber which is detected during processing of the film to be processed; and compares a film thickness corresponding to one of the plurality of patterns having a minimum difference obtained by the comparison and a target film thickness; and determines that the thickness of the film to be processed reaches the target film thickness.Type: ApplicationFiled: February 19, 2014Publication date: January 22, 2015Inventors: Kousuke Fukuchi, Shigeru Nakamoto, Tatehito Usui, Satomi Inoue, Kousa Hirota
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Publication number: 20150014821Abstract: Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure.Type: ApplicationFiled: October 2, 2014Publication date: January 15, 2015Inventor: Carlos Strocchia-Rivera
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Patent number: 8932883Abstract: The present invention relates to a method of measuring surface properties of a polishing pad which measures surface properties such as surface topography or surface condition of a polishing pad used for polishing a substrate such as a semiconductor wafer. The method of measuring surface properties of a polishing pad includes applying a laser beam to the polishing pad, detecting scattered light that is reflected and scattered by the polishing pad with a photodetector and performing an optical Fourier transform on the detected scattered light to produce an intensity distribution corresponding to a spatial wavelength spectrum based on surface topography of the polishing pad, and calculating a numerical value representing surface properties of the polishing pad based on the intensity distribution corresponding to two different prescribed spatial wavelength ranges.Type: GrantFiled: September 11, 2013Date of Patent: January 13, 2015Assignees: Ebara Corporation, Kyushu Institute of TechnologyInventors: Hisanori Matsuo, Keiichi Kimura, Keisuke Suzuki, Panart Khajornrungruang, Takashi Kushida
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Patent number: 8932874Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.Type: GrantFiled: July 2, 2014Date of Patent: January 13, 2015Assignee: Nalco CompanyInventors: Amy M. Tseng, Brian V. Jenkins, Robert M. Mack
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Publication number: 20150011027Abstract: Embodiments of the present disclosure provide methods for forming stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips using precise photoresist trimming process endpoint control. In one example, a method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, directing an optical signal to a surface of the patterned photoresist layer while trimming the patterned photoresist layer, collecting a return reflected optical signal reflected from the photoresist layer, and determining a trimming endpoint by analyzing the return optical signal reflected from the photoresist layer.Type: ApplicationFiled: July 8, 2014Publication date: January 8, 2015Inventor: Lei LIAN
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Patent number: 8930011Abstract: A method of measuring an overlay of an object is provided. In the method, first information of a first structure may be obtained. A preliminary structure may be formed on the first structure. Second information of the preliminary structure may be obtained. The first information and the second information may be processed to obtain virtual information of a second structure that would be formed on the first structure if a process is performed on the preliminary structure. A virtual overlay between the first structure and the second structure may be measured using the virtual information.Type: GrantFiled: May 13, 2011Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Seok Heo, Seok-Hwan Oh, Jeong-Ho Yeo
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Publication number: 20150001087Abstract: Disclosed herein are electroplating systems for forming a layer of metal on a wafer which include an electroplating module and a wafer edge imaging system. The electroplating module may include a cell for containing an anode and an electroplating solution during electroplating, and a wafer holder for holding the wafer in the electroplating solution and rotating the wafer during electroplating. The wafer edge imaging system may include a wafer holder for holding and rotating the wafer through different azimuthal orientations, a camera oriented for obtaining multiple azimuthally separated images of a process edge of the wafer while it is held and rotated (the process edge corresponding to the outer edge of the layer of metal formed on the wafer), and image analysis logic for determining an edge exclusion distance, wherein the edge exclusion distance is a distance between the wafer's edge and the process edge.Type: ApplicationFiled: June 26, 2013Publication date: January 1, 2015Inventors: Daniel Mark Dinneen, James E. Duncan
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Publication number: 20140377890Abstract: An apparatus for monitoring deposition rate, an apparatus including the same, for depositing an organic layer, a method of monitoring deposition rate, and a method of manufacturing an organic light emitting display apparatus using the same, are provided. The deposition rate monitoring apparatus for measuring deposition rate of a deposition material discharged from a deposition source, includes: a light source for irradiating light having a wavelength within a photoexcitation bandwidth of the deposition material; a first optical system for irradiating the light emitted from the light source toward the discharged deposition material; a second optical system for collecting the light emitted from the deposition material; and a first light sensor for detecting the amount of the light which is emitted from the deposition material and collected in the second optical system.Type: ApplicationFiled: November 13, 2013Publication date: December 25, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Alexander Voronov, Dmitry Maslov, Gyoo-Wan Han
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Publication number: 20140374758Abstract: System for wafer-level phosphor deposition. A method for phosphor deposition on a semiconductor wafer that has a plurality of LED dies includes the operations of covering the semiconductor wafer with a selected thickness of photo resist material, removing portions of the photo resist material to expose portions of the semiconductor wafer so that electrical contacts associated with the plurality of LED dies remain unexposed, and depositing phosphor on the exposed portions of the semiconductor wafer.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Applicant: BRIDGELUX, INC.Inventor: TAO XU
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Publication number: 20140374771Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Applicants: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.Inventors: Kazuyuki UMENO, Tatsuyuki Shinagawa, Keishi Takaki, Ryosuke Tamura, Shinya Ootomo
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Patent number: 8916407Abstract: A method of manufacturing a micromachined resonator having a moveable member comprising forming the moveable member from a material having a first concentration of dopants of a first impurity type, depositing a dopant carrier layer on or over at least a portion of the moveable member, wherein the dopant carrier layer includes one or more dopants of the first impurity type, transferring at least a portion of the one or more dopants from the dopant carrier layer to the moveable member, wherein, in response, the concentration of dopants of the first impurity type in the moveable member increases (for example, to greater than 1019 cm?3, and preferably between 1019 cm?3 and 1021 cm?3). The method further includes removing the dopant carrier layer and may include providing an encapsulation structure over the moveable member of the micromachined resonator.Type: GrantFiled: March 15, 2013Date of Patent: December 23, 2014Assignee: SiTime CorporationInventors: Charles I Grosjean, Ginel Hill, Paul M. Hagelin, Renata Melamud Berger, Aaron Partridge, Markus Lutz
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Publication number: 20140370628Abstract: According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality.Type: ApplicationFiled: September 3, 2014Publication date: December 18, 2014Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: Takeo SATO
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Publication number: 20140370627Abstract: A Raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The Raman probe may be coupled to a targeting system of a laser thermal processing system. The Raman probe includes a laser positioned to direct probe radiation through the targeting system to the substrate, a receiver attuned to Raman radiation emitted by the substrate, and a filter that blocks laser radiation reflected by the substrate. The Raman probe may include more than one laser, more than one receiver, and more than one filter. The Raman probe may provide more than one wavelength of incident radiation to probe the substrate at different depths.Type: ApplicationFiled: June 16, 2014Publication date: December 18, 2014Inventor: Jiping LI
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Publication number: 20140363153Abstract: An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Inventors: Michael B. McShane, Perry H. Pelley, Tab A. Stephens
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Patent number: 8908161Abstract: Approaches for substantially removing bulk aluminum nitride (AlN) from one or more layers epitaxially grown on the bulk AlN are discussed. The bulk AlN is exposed to an etchant during an etching process. During the etching process, the thickness of the bulk AlN can be measured and used to control etching.Type: GrantFiled: August 25, 2011Date of Patent: December 9, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Brent S. Krusor, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Bowen Cheng
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Patent number: 8906708Abstract: A method for checking an ion implantation condition when ions are implanted over an entirety of one surface of a semiconductor wafer having an insulator film on the one surface, the method including checking whether the ions are implanted over the entirety of the one surface of the semiconductor wafer by directly or indirectly observing light emitted when the one surface of the semiconductor wafer is irradiated with an ion beam of the implanted ions throughout the ion implantation.Type: GrantFiled: March 28, 2011Date of Patent: December 9, 2014Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Isao Yokokawa
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Patent number: 8906784Abstract: A method of manufacturing a modified structure comprising a semiconducting modified graphene layer on a substrate, comprising the subsequent following steps: supply of an initial structure comprising at least one substrate, formation of a graphene layer on the substrate, hydrogenation of the initial structure by exposure to atomic hydrogen, characterized in that the hydrogenation step of the graphene layer is done with an exposure dose between 100 and 4000 Langmuirs, and forms a modified graphene layer.Type: GrantFiled: November 9, 2010Date of Patent: December 9, 2014Assignee: Commissariat á l'Energie Atomique et aux Énergies AlternativesInventors: Shirley Chiang, Hanna Enriquez, Hamid Oughaddou, Patrick Soukiassian, Antonio Tejeda Gala, Sébastien Vizzini
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Patent number: 8906777Abstract: A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided.Type: GrantFiled: January 29, 2009Date of Patent: December 9, 2014Assignee: Sumco Techxiv CorporationInventors: Kazuhiro Iriguchi, Toshiyuki Isami, Kouhei Kawano
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Patent number: 8906709Abstract: Provided are methods of high productivity combinatorial (HPC) inspection of semiconductor substrates. A substrate includes two layers of dissimilar materials interfacing each other, such as a stack of a silicon bottom layer and an indium gallium arsenide top layer. The dissimilar materials have one or more of thermal, structural, and lattice mismatches. As a part of the inspection, the top layer is etched in a combinatorial manner. Specifically, the top layer is divided into multiple different site-isolated regions. One such region may be etched using different process conditions from another region. Specifically, etching temperature, etching duration and/or etchant composition may vary among the site-isolated regions. After combinatorial etching, each region is inspected to determine its etch-pit density (EPD) value. These values may be then analyzed to determine an overall EPD value for the substrate, which may involve discarding EPD values for over-etched and under-etched regions.Type: GrantFiled: December 23, 2013Date of Patent: December 9, 2014Assignee: Intermolecular, Inc.Inventors: Khaled Ahmed, Frank Greer, George Mirth, Zhi-Wen Sun
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Publication number: 20140356988Abstract: A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer.Type: ApplicationFiled: April 15, 2014Publication date: December 4, 2014Inventors: Daquan Yu, Feng Jiang
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Patent number: 8900889Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.Type: GrantFiled: October 19, 2012Date of Patent: December 2, 2014Assignee: Applied Materials, Inc.Inventors: Khurshed Sorabji, Joseph M. Ranish, Wolfgang Aderhold, Aaron M. Hunter, Blake R. Koelmel, Alexander N. Lerner, Nir Merry
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Patent number: 8900888Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence contains at least one active layer for generating primary radiation. In addition, the semiconductor layer sequence includes a plurality of conversion layers, the conversion layers being designed to absorb the primary radiation at least partially and to convert it into secondary radiation of a longer wavelength than the primary radiation. Furthermore the semiconductor layer sequence comprises a roughening which extends at least into the conversion layers.Type: GrantFiled: April 8, 2010Date of Patent: December 2, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Nikolaus Gmeinwieser, Berthold Hahn
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Patent number: 8900887Abstract: A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other.Type: GrantFiled: December 28, 2012Date of Patent: December 2, 2014Assignee: Shanghai Huali Microelectronics CorporationInventors: Zaifeng Tang, Chao Fang, Yukun Lv, HsuSheng Chang
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Publication number: 20140349419Abstract: A method of manufacturing a light-emitting device includes forming a wave length conversion portion on a light-emitting element. The light emitting device includes a light-emitting element which emits light of a predetermined wavelength and a wavelength conversion portion which includes a fluorescent substance which is excited by the light emitted from the light-emitting element so as to emit fluorescence of a wavelength different from the predetermined wavelength, which wavelength conversion portion is formed by including the fluorescent substance, a layered silicate mineral, and an organometallic compound.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventor: Takeshi KOJIMA
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Patent number: 8893377Abstract: When bump electrodes 26 of a semiconductor light-emitting element 2 and electrode portions 21 of a mounting board 3 are joined to each other, power is supplied to the electrode portions 21 of the mounting board 3 to allow the semiconductor light-emitting element 2 to emit light, the optical properties of the semiconductor light-emitting element 2 having emitted light are detected, and the detected value of optical properties is processed to obtain the joining state of the bump electrodes 26 of the semiconductor light-emitting element 2 and the electrode portions 21 of the mounting board 3, so that the completion of joining is determined. Thus, the semiconductor light-emitting element can be satisfactorily joined to the electrode portions on the mounting board via the metal electrodes formed on the semiconductor light-emitting element.Type: GrantFiled: April 26, 2011Date of Patent: November 25, 2014Assignee: Panasonic CorporationInventors: Tomonori Itoh, Kaori Toyoda, Hiroki Ikeuchi, Takeshi Kawabata
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Patent number: 8893650Abstract: A substrate treatment apparatus configured such that substrates in a same lot are distributed by a delivery mechanism into a plurality of unit blocks, each unit block including a solution treatment module, an ultraviolet irradiation module, and a substrate carrying mechanism, the apparatus includes: an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; and a control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates which have already been delivered to the one unit block with an irradiation time adjusted to a length according to the illuminance detection value.Type: GrantFiled: January 15, 2013Date of Patent: November 25, 2014Assignee: Tokyo Electron LimitedInventor: Masatoshi Kaneda
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Publication number: 20140342477Abstract: A method of monitoring a semiconductor fabrication process including forming a barrier pattern on a substrate, forming a sacrificial pattern on the barrier pattern, removing the sacrificial pattern to expose a surface of the barrier pattern, generating photoelectrons by irradiating X-rays to a surface of the substrate, and inferring at least one material existing on the surface of the substrate by collecting and analyzing the photoelectrons may be provided.Type: ApplicationFiled: March 4, 2014Publication date: November 20, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choon-Shik LEEM, Deok-Yong KIM, Sang-Ho SONG, Chul-Gi SONG, Ho-Yeol LEE, Soo-Bok CHIN
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Patent number: 8889434Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.Type: GrantFiled: December 17, 2012Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Di Tsen, Shin-Rung Lu, Jong-I Mou
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Patent number: 8891240Abstract: An apparatus and method for cooling a semiconductor device. The apparatus comprises a chamber configured for receiving a cooling fluid; and a plurality of contact elements comprising respective first ends disposed within the chamber; wherein, during operation, respective second ends of contact elements contact a surface of the semiconductor device for transferring heat generated in the semiconductor device to the cooling fluid.Type: GrantFiled: August 31, 2011Date of Patent: November 18, 2014Assignee: Semicaps Pte LtdInventors: Choon Meng Chua, Lian Ser Koh, Sze Wei Choong, Jacob Chee Hong Phang
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Patent number: 8892568Abstract: A method of controlling polishing includes storing a library having a plurality of reference spectra, polishing a substrate, measuring a sequence of spectra of light from the substrate during polishing, for each measured spectrum of the sequence of spectra, finding a best matching reference spectrum using a matching technique other than sum of squared differences to generate a sequence of best matching reference spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. Finding a best matching reference spectrum may include performing a cross-correlation of the measured spectrum with each of two or more of the plurality of reference spectra from the library and selecting a reference spectrum with the greatest correlation to the measured spectrum as a best matching reference spectrum.Type: GrantFiled: October 10, 2011Date of Patent: November 18, 2014Assignee: Applied Materials, Inc.Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Xiaoyuan Hu
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Patent number: 8883522Abstract: A system includes a computer-readable medium that stores a plurality of instructions for execution by at least one computer processor. The instructions include receiving a reflectivity measurement on a semiconductor wafer and generating a reflectivity map based on the received reflectivity measurement. The instructions determine a spatial distance for a selected reflectivity change using the generated reflectivity map. Subsequently, the determined spatial distance is compared with a thermal diffusion length of a first anneal process technique. In embodiments, the system further includes a light source and a reflectivity measurement tool.Type: GrantFiled: April 28, 2014Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, De-Wei Yu
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Patent number: 8884406Abstract: A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.Type: GrantFiled: September 13, 2011Date of Patent: November 11, 2014Assignee: Alpha & Omega Semiconductor LtdInventors: Yingying Lou, Tiesheng Li, Yu Wang, Anup Bhalla
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Publication number: 20140327112Abstract: Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.Type: ApplicationFiled: October 14, 2011Publication date: November 6, 2014Applicant: SunEdison, Inc.Inventors: Jeffrey L. Libbert, Lu Fei
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Publication number: 20140329343Abstract: A method and system for monitoring crystallization of an amorphous silicon (a-Si) thin film, and a method of manufacturing a thin film transistor (TFT) by using the method and system are disclosed. The method of monitoring the crystallization of the a-Si thin film includes: irradiating light from a light source onto a monitoring a-Si thin film to anneal the monitoring a-Si thin film; annealing the monitoring a-Si thin film and concurrently measuring a Raman scattering spectrum of light scattered by the monitoring a-Si thin film at set time intervals; and calculating a crystallization characteristic value of the monitoring a-Si thin film based on the Raman scattering spectrum.Type: ApplicationFiled: September 9, 2013Publication date: November 6, 2014Applicant: Samsung Display Co., Ltd.Inventors: Maidanchuk Ivan, Byung-Soo So, Dong-Hyun Lee, Won-Pil Lee
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Patent number: 8878561Abstract: This invention is to detect defective products of semiconductor devices with high accuracy even when the characteristics of the semiconductor devices vary according to their positions on each of wafers.Type: GrantFiled: July 26, 2012Date of Patent: November 4, 2014Assignee: Renesas Electronics CorporationInventor: Kazuhiro Sakaguchi
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Patent number: 8877525Abstract: Mechanisms are provided for chip (e.g., semiconductor chip) identification (e.g., low cost secure identification). In one example, a method of manufacturing for implementing integrated chip identification is provided. In another example, a method of using a chip with an integrated identification is provided.Type: GrantFiled: July 25, 2013Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Effendi Leobandung, Dirk Pfeiffer
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Patent number: 8877524Abstract: A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED chips comprises light from the conversion material, typically in combination with LED light. The emission characteristics of at least some of the LED chips is measured and at least some of the conversion material over the LEDs is removed to alter the emission characteristics of the LED chips. The invention is particularly applicable to fabricating LED chips on a wafer where the LED chips have light emission characteristics that are within a range of target emission characteristics. This target range can fall within an emission region on a CIE curve to reduce the need for binning of the LEDs from the wafer.Type: GrantFiled: March 30, 2009Date of Patent: November 4, 2014Assignee: Cree, Inc.Inventors: Ashay Chitnis, John Edmond, Jeffrey Carl Britt, Bernd P. Keller, David Todd Emerson, Michael John Bergmann, Jasper S. Cabalu
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Publication number: 20140312367Abstract: A Light Emitting Diode (LED) package comprises a Printed Circuit Board (PCB), an LED mounted on the PCB, a pillar placed higher than the LED around the LED on the PCB, a transparent plate disposed on the pillar, spaced apart from the LED, and configured to transmit light emitted from the LED, and a fluorescent layer formed on a surface of the transparent plate, facing the LED, and conformably coated with a substance for converting a wavelength of the light emitted from the LED, wherein an electrical pad of the LED and an electrical pad of the PCB are electrically connected to each other, and the LED and the fluorescent layer are spaced apart from each other.Type: ApplicationFiled: May 18, 2012Publication date: October 23, 2014Inventors: Byoung-Gu Cho, Jae-Sik Min