Vertical Channel Insulated Gate Field Effect Transistor Patents (Class 438/206)
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Patent number: 8222110Abstract: A method for fabricating a semiconductor device includes forming a plurality of first active pillars by etching a substrate using a hard mask layer as an etching barrier, forming a gate conductive layer surrounding sidewalls of the first active pillars and the hard mask layer, forming a word line conductive layer filling gaps defined by the gate conductive layer, forming word lines and vertical gates by simultaneously removing portions of the word line conductive layer and the gate conductive layer on the sidewalls of the hard mask layer, forming an inter-layer dielectric layer filling gaps formed by removing the word line conductive layer and the gate conductive layer, exposing surfaces of the first active pillars by removing the hard mask layer, and growing second active pillars over the first active pillars.Type: GrantFiled: June 30, 2010Date of Patent: July 17, 2012Assignee: Hynix Semiconductor Inc.Inventors: Eun-Jeong Kim, Sang-Tae Ahn
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Patent number: 8211758Abstract: It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor.Type: GrantFiled: February 3, 2010Date of Patent: July 3, 2012Assignee: Unisantis Electronics Singapore PTE Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo
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Patent number: 8207566Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.Type: GrantFiled: March 24, 2011Date of Patent: June 26, 2012Assignee: Hynix Semiconductor Inc.Inventor: Chun-Hee Lee
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Patent number: 8207032Abstract: Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 ?/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.Type: GrantFiled: August 31, 2010Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventors: Mark Fischer, Sanh D. Tang
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Patent number: 8193080Abstract: An impurity is introduced into a fin-type semiconductor region (102) formed on a substrate (100) using a plasma doping process, thereby forming an impurity-introduced layer (105). Carbon is introduced into the fin-type semiconductor region (102) using a plasma doping process to overlap at least a part of the impurity-introduced layer (105), thereby forming a carbon-introduced layer.Type: GrantFiled: March 26, 2010Date of Patent: June 5, 2012Assignee: Panasonic CorporationInventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
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Patent number: 8168492Abstract: In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.Type: GrantFiled: April 5, 2010Date of Patent: May 1, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Dong-Gun Park, Dong-Won Kim, Min-Sang Kim, Eun-jung Yun
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Patent number: 8138581Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.Type: GrantFiled: September 21, 2010Date of Patent: March 20, 2012Assignee: Infineon Technologies Austria AGInventor: Franz Hirler
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Patent number: 8119471Abstract: A method for manufacturing a semiconductor device including a vertical double-diffusedmetal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type.Type: GrantFiled: August 8, 2011Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventor: Hiroki Fujii
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Patent number: 8105890Abstract: A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium.Type: GrantFiled: June 30, 2005Date of Patent: January 31, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Terry Sparks
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Patent number: 8097512Abstract: A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.Type: GrantFiled: July 30, 2008Date of Patent: January 17, 2012Assignee: Power Integrations, Inc.Inventors: Jian Li, Daniel Chang, Ho-Yuan Yu
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Patent number: 8093122Abstract: A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a gate electrode by etching the etch-backed conductive layer.Type: GrantFiled: June 27, 2008Date of Patent: January 10, 2012Assignee: Hynix Semiconductor Inc.Inventor: Chun-Hee Lee
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Patent number: 8084304Abstract: A method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET includes fabricate numerous trench MOSFETs on a wafer; add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer; add numerous ESD protection modules atop the Si3N4 isolation layer.Type: GrantFiled: May 29, 2010Date of Patent: December 27, 2011Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen
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Patent number: 8058683Abstract: An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.Type: GrantFiled: December 11, 2007Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Man Yoon, Yong-Chul Oh, Hui-Jung Kim, Hyun-Woo Chung
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Patent number: 8053286Abstract: A method of forming a semiconductor device is provided, which may include, but is not limited to, the following processes. Grooves may be formed in an insulating region and in a semiconductor region, while forming burrs near the boundary between the insulating region and the semiconductor region. Protection films may be selectively formed on inside walls of the grooves except on bottom walls of the grooves. A selective thermal process may be carried out in the presence of the protection films, thereby removing the burrs.Type: GrantFiled: November 14, 2008Date of Patent: November 8, 2011Assignee: Elpida Memory, Inc.Inventors: Kyoko Miyata, Fumiki Aiso
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Patent number: 8003456Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.Type: GrantFiled: June 25, 2008Date of Patent: August 23, 2011Assignee: Infineon Technologies Austria AGInventors: Davide Chiola, Carsten Schaeffer
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Patent number: 7968396Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: GrantFiled: November 25, 2009Date of Patent: June 28, 2011Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7935598Abstract: A vertical channel transistor includes a plurality of active pillar patterns extending perpendicularly from the top surface of the substrate toward an upper part. A gate insulating layer is deposited on the side wall of the active pillar pattern and serves as an ion diffusion barrier between the pillar patterns and surrounding lower gate electrodes. The resultant pillar pattern structure is encapsulated with a metal. The resultant pillar pattern is surrounded on all sides by a specified height by a sacrificial layer of Spin-On Dielectric (SOD). The metal layer is etched-back to the height of the sacrificial layer, thus forming the lower gate electrodes. A spacer layer of an insulating mater is deposited surrounding the upper part of the pillar patterns and the sacrificial layer is removed exposing a part of the lower gate electrodes. The exposed gate electrode is etched to facilitate semiconductor integration.Type: GrantFiled: December 16, 2008Date of Patent: May 3, 2011Assignee: Hynix Semiconductor Inc.Inventor: Chun-Hee Lee
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Patent number: 7932142Abstract: A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer.Type: GrantFiled: October 27, 2008Date of Patent: April 26, 2011Assignee: Elpida Memory, Inc.Inventor: Hiroyuki Uchiyama
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Patent number: 7923320Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.Type: GrantFiled: February 21, 2007Date of Patent: April 12, 2011Assignee: Cree, Inc.Inventor: Sei-Hyung Ryu
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Patent number: 7915113Abstract: A method for manufacturing a semiconductor device including a vertical cell transistor structure may include forming a vertical cell transistor structure over a semiconductor substrate of a cell region; forming an insulating film over the vertical cell transistor structure; planarizing the insulating film to expose a hard mask film disposed at a top portion of the vertical cell transistor structure; and forming a storage node contact by removing the hard mask film.Type: GrantFiled: October 14, 2008Date of Patent: March 29, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jin Soo Kim, Chang Moon Lim
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Patent number: 7892896Abstract: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other to a certain distance in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region.Type: GrantFiled: March 3, 2010Date of Patent: February 22, 2011Assignee: Hynix Semiconductor Inc.Inventor: Sang-Oak Shim
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Patent number: 7892911Abstract: Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.Type: GrantFiled: January 10, 2008Date of Patent: February 22, 2011Assignee: Applied Materials, Inc.Inventors: Bingxi Sun Wood, Chorng-Ping Chang
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Patent number: 7889556Abstract: A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.Type: GrantFiled: January 20, 2010Date of Patent: February 15, 2011Assignee: Macronix International Co., Ltd.Inventors: Shaw Hung Ku, Ten Hao Yeh, Shih Chin Lee, Shang Wei Lin, Chia Wei Wu, Tzung Ting Han, Ming Shang Chen, Wenpin Lu
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Patent number: 7879676Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.Type: GrantFiled: July 30, 2010Date of Patent: February 1, 2011Assignee: Alpha & Omega Semiconductor IncorporatedInventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
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Patent number: 7855105Abstract: A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer.Type: GrantFiled: June 18, 2009Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Hemanth Jagannathan, Vijay Narayanan, Vamsi K. Paruchuri
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Patent number: 7851293Abstract: A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.Type: GrantFiled: December 12, 2008Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: Yun-Seok Cho
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Patent number: 7851283Abstract: Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures.Type: GrantFiled: July 30, 2008Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Thomas Ludwig, Edward J. Nowak
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Patent number: 7851309Abstract: Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body.Type: GrantFiled: April 6, 2009Date of Patent: December 14, 2010Assignee: Micron Technology, Inc.Inventor: Terrence C. Leslie
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Patent number: 7829898Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.Type: GrantFiled: February 14, 2006Date of Patent: November 9, 2010Assignee: Mitsubishi Electric CorporationInventors: Kenichi Ootsuka, Tetsuya Takami, Tadaharu Minato
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Patent number: 7824982Abstract: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.Type: GrantFiled: December 12, 2007Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7816229Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.Type: GrantFiled: September 30, 2008Date of Patent: October 19, 2010Assignee: Infineon Technologies Austria AGInventor: Franz Hirler
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Patent number: 7767526Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.Type: GrantFiled: January 29, 2009Date of Patent: August 3, 2010Assignee: Alpha & Omega Semiconductor IncorporatedInventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
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Patent number: 7705396Abstract: In an embodiment of the present invention, a Trench MOSFET includes a trench region provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate, a P-type semiconductor epitaxial layer, an N-type semiconductor body region, and a P-type semiconductor source diffusion. The substrate, the epitaxial layer, the body region, and the source diffusion are adjacently formed in this order. A P-type semiconductor channel region formed of a SiGe layer is provided on a bottom surface and a side wall of the trench region. This facilitates carrier movement in the channel region, reducing ON resistance of the Trench MOSFET. Thus, a Trench MOSFET allowing reduction in the ON resistance without reducing a breakdown voltage is realized.Type: GrantFiled: June 7, 2006Date of Patent: April 27, 2010Assignee: Sharp Kabushiki KaishaInventor: Alberto O Adan
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Patent number: 7682889Abstract: A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region (22) doped to have the second conductivity type above a drain region (20) doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region (4) and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.Type: GrantFiled: February 23, 2005Date of Patent: March 23, 2010Assignee: NXP B.V.Inventor: Steven T. Peake
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Patent number: 7674669Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.Type: GrantFiled: September 7, 2007Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventor: Hussein I. Hanafi
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Patent number: 7645655Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: GrantFiled: June 5, 2006Date of Patent: January 12, 2010Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7642149Abstract: A method for producing a semiconductor device which includes: a semiconductor base, a hetero semiconductor region made of a semiconductor material different in band gap from a semiconductor material for the semiconductor base, and so configured as to form a hetero junction in combination with the semiconductor base, a gate insulating film so configured as to contact with the hetero junction between the semiconductor base and the hetero semiconductor region, a gate electrode so configured as to contact with the gate insulating film, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor base. The method includes: forming the following in a self-aligning manner, by using a certain mask material: a source contact hole for the source electrode, and the gate electrode.Type: GrantFiled: October 11, 2007Date of Patent: January 5, 2010Assignee: Nissan Motor Co., Ltd.Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Hideaki Tanaka, Shigeharu Yamagami
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Patent number: 7642154Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.Type: GrantFiled: October 27, 2006Date of Patent: January 5, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Kwang Young Ko
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Patent number: 7642589Abstract: A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.Type: GrantFiled: May 15, 2006Date of Patent: January 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Si-Young Choi, Byeong-Chan Lee, Deok-Hyung Lee, In-Soo Jung
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Patent number: 7629211Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.Type: GrantFiled: March 9, 2007Date of Patent: December 8, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Sven Beyer, Thorsten Kammler, Rolf Stephan, Manfred Horstmann
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Patent number: 7612431Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: January 17, 2008Date of Patent: November 3, 2009Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
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Patent number: 7592218Abstract: A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source/drain elevationally above the first source/drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.Type: GrantFiled: March 31, 2008Date of Patent: September 22, 2009Assignee: Micron Technology, Inc.Inventor: Kris K. Brown
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Patent number: 7588977Abstract: A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.Type: GrantFiled: June 13, 2006Date of Patent: September 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-dae Suk, Sung-young Lee, Dong-won Kim, Sung-min Kim
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Patent number: 7585717Abstract: A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is overlapped with the sacrifice film; forming a semiconductor film over the sacrifice film such that the semiconductor film crosses over the lower gate electrode; removing the sacrifice film; forming a lower gate insulating film in an empty space between the lower gate electrode and the semiconductor film, the empty space being obtained by removing the sacrifice film; forming an upper gate insulating film over the semiconductor film; and forming an upper gate electrode over the upper gate insulating film, the upper gate electrode being electrically connected to the lower gate electrode.Type: GrantFiled: November 29, 2006Date of Patent: September 8, 2009Assignee: Seiko Epson CorporationInventor: Ichio Yudasaka
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Patent number: 7585705Abstract: A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process is found to cause the gate oxide damage. The method includes: a) Fabricate numerous trench MOSFETs on a wafer. b) Add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer. c) Add numerous ESD protection modules atop the Si3N4 isolation layer. d) Remove those portions of the Si3N4 isolation layer that are not beneath the ESD protection modules. In one embodiment, hydrofluoric acid is used as a first etchant for patterning the LTO while hot phosphoric acid is used as a second etchant for removing portions of the Si3N4 isolation layer.Type: GrantFiled: November 29, 2007Date of Patent: September 8, 2009Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Mengyu Pan, Zengyi He, Kaiyu Chen
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Patent number: 7537994Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.Type: GrantFiled: August 28, 2006Date of Patent: May 26, 2009Assignee: Micron Technology, Inc.Inventors: Ted Taylor, Xiawan Yang
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Patent number: 7534674Abstract: First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors.Type: GrantFiled: April 19, 2007Date of Patent: May 19, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Sinan Goktepeli, Venkat R. Kolagunta
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Patent number: 7531395Abstract: Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an opening into a silicate glass-comprising material received over a monocrystalline material. The etching is conducted to the monocrystalline material effective to expose the monocrystalline material at a base of the opening. A silicon-comprising layer is epitaxially grown within the opening from the monocrystalline material exposed at the base of the opening. The silicate glass-comprising material is etched from the substrate effective to leave a free-standing projection of the epitaxially grown silicon-comprising layer projecting from the monocrystalline material which was at the base of the opening. Other implementations and aspects are contemplated.Type: GrantFiled: January 12, 2005Date of Patent: May 12, 2009Assignee: Micron Technology, Inc.Inventors: Eric R. Blomiley, Gurtej S. Sandhu, Cem Basceri, Nirmal Ramaswamy
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Patent number: 7514324Abstract: Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. These components are grown directly in electrical communication lines. Moreover, these components are adapted for use in memory devices and are believed to not require the use of shallow trench isolation.Type: GrantFiled: August 31, 2005Date of Patent: April 7, 2009Assignee: Micron Technology, Inc.Inventor: Terrence C. Leslie
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Patent number: 7501674Abstract: Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.Type: GrantFiled: October 6, 2005Date of Patent: March 10, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Deok-Hyung Lee, Yu-Gyun Shin, Jong-Wook Lee, Min-Gu Kang