Including Isolation Structure Patents (Class 438/207)
  • Patent number: 6977417
    Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: December 20, 2005
    Assignee: Fujitsu Limited
    Inventors: Youichi Momiyama, Kenichi Okabe, Takashi Saiki, Hidenobu Fukutome
  • Patent number: 6974999
    Abstract: It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode (3) is formed by etching using a hard mask as a mask and the hard mask remains on an upper surface of the gate electrode (3) at a subsequent step. In the meantime, the upper surface of the gate electrode (3) can be therefore prevented from being unnecessarily etched. The hard mask is removed after ion implantation for forming a source-drain region. Consequently, the influence of the removal of the hard mask on a characteristic of a semiconductor device can be suppressed. In that case, moreover, a surface of a side wall (4) is also etched by a thickness of (d) so that an exposure width of an upper surface of the source-drain region is increased. After the removal of the hard mask, it is easy to salicide the gate electrode (3) and to form a contact on the gate electrode (3).
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: December 13, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Tsuyoshi Sugihara
  • Patent number: 6964894
    Abstract: A method of forming a MEMS device produces a device layer wafer having a pre-formed conductive pathway before coupling it with a handle wafer. To that end, the method produces the noted device layer wafer by 1) providing a material layer, 2) coupling a conductor to the material layer, and 3) forming at least two conductive paths through at least a portion of the material layer to the conductor. The method then provides the noted handle wafer, and couples the device layer wafer to the handle wafer. The wafers are coupled so that the conductor is contained between the material layer and the handle wafer.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: November 15, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Bruce K. Wachtmann, Michael W. Judy
  • Patent number: 6955957
    Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: October 18, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Patent number: 6943398
    Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: September 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
  • Patent number: 6940145
    Abstract: A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: September 6, 2005
    Assignee: Zetex PLC
    Inventors: Peter Blair, Adrian Finney, Paul Gerrard, Andrew Wood, David Mottram
  • Patent number: 6927459
    Abstract: A gate electrode is provided via a gate insulating film formed between the source and drain regions on a semiconductor substrate, wherein the sidewall of the gate electrode excluding the exposed part formed at the upper part thereof facing the source and drain regions is covered with a sidewall insulating film, and an epitaxial film is formed on the exposed part of the sidewall of the gate electrode but not formed on a top surface of the gate electrode. An element isolation region formed on the semiconductor substrate is composed of a first insulating film formed in the semiconductor substrate and a second insulating film which is formed inside the first insulating film and has a lower epitaxial growth rate than that of the first insulating film, and the surface of the source and drain regions is covered with a silicon layer, part of which runs onto the surface of the first insulating film.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: August 9, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Hokazono, Mariko Takayanagi
  • Patent number: 6924187
    Abstract: A semiconductor device, including a dummy diffused layer in the upper part of a substrate, has its noise immunity improved. The dummy diffused layer is formed between analog and digital blocks to eliminate dishing, which usually occurs during a CMP process for defining STI regions. The surface of the dummy diffused layer is covered with an anti-silicidation film at least partially and a dummy gate electrode so as not to be silicided. The dummy gate electrode can be formed along with a normal gate electrode for a transistor.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: August 2, 2005
    Assignee: Matsushita Electrical Industrial Co., Ltd.
    Inventors: Satoshi Ishikura, Yukio Iijima, Nobuaki Minakuchi
  • Patent number: 6921688
    Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: July 26, 2005
    Assignee: Alliance Semiconductor
    Inventor: Ritu Shrivastava
  • Patent number: 6914308
    Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: July 5, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Hidenori Fujii
  • Patent number: 6869838
    Abstract: A method of passivation layer deposition using a cyclical deposition process is described. The cyclical deposition process may comprise alternately adsorbing a silicon-containing precursor and a reactant gas on a substrate structure. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a silicon-containing passivation layer, may be formed using such cyclical deposition techniques.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: March 22, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Kam Law, Quanyuan Shang, William Reid Harshbarger, Dan Maydan
  • Patent number: 6864133
    Abstract: A device comprising a semiconductor film (12) formed on a substrate (11), a gate region (15), in which a gate insulating film (13) formed on the semiconductor film and a gate electrode film (14) are laminated, isolation means (A) formed on both sides of the gate region to prevent contact between the gate electrode film and other regions, and a source region and a drain region formed by baking a liquid semiconductor material (17) and disposed on regions on the substrate and on both sides of the gate region.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: March 8, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Aoki, Masahiro Furusawa, Ichio Yudasaka
  • Patent number: 6858486
    Abstract: A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a channel stop p-well region and emitter region which are vertically oriented within a semiconductor substrate. The resulting bipolar device is junction isolated from other circuits formed on the substrate by a p-well region.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: February 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Amitava Chatterjee
  • Patent number: 6852585
    Abstract: A semiconductor circuit arrangement includes a circuit element embedded in a semiconductor substrate of a first conductivity type in an integrated manner and is provided with at least one gate electrode and first and second terminal electrodes. The first terminal electrode includes a well region that is embedded in the semiconductor substrate and is of a second conductivity type which is opposite the first conductivity type. A sub-well region is embedded in the well region of the first terminal electrode and is of the second conductivity type and has a higher doping than said well region. The sub-well region is embedded in the surface of the substrate and ends without reaching a well region of the gate electrode which is of the first conductivity type.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Christian Herzum, Ulrich Krumbein, Karl-Heinz Mueller
  • Patent number: 6830977
    Abstract: A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isolation trench portion within and extending below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe
  • Publication number: 20040241929
    Abstract: In order to produce insulator structures (8), insulator trenches (21) with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate (1) from a substrate surface (10) and filled with an insulator filling (3). The insulator filling (3) is formed from a plurality of portions (31, 32, 33, 34) which are deposited successively in situ in an HDP/CVD process chamber in the course of an HDP/CVD deposition process. A main layer (33) is provided made from fluorine-doped silicon oxide with good filling properties. A barrier layer (32) is formed directly before the deposition of the main layer (33), said barrier layer preventing an outgassing of the fluorine from the fluorine-doped silicon oxide (33), an interaction of the fluorine with the semiconductor substrate (1) and a formation of defect areas (6) with oxide of low quality in the area of the insulator filling (3). The barrier (32) makes it possible to form nondegrading p-channel transistors (73) in the area of the substrate surface (10).
    Type: Application
    Filed: March 12, 2004
    Publication date: December 2, 2004
    Inventor: Joerg Radecker
  • Patent number: 6825074
    Abstract: A silicon-on-insulator (SOI) substrate is provided which includes a silicon substrate having an upper surface, a first insulating layer having a lower surface extending horizontally over the upper surface of the silicon substrate, and a silicon layer having a lower surface extending horizontally over an upper surface of the first insulating layer. A second insulating layer is formed over an upper surface of the silicon layer of the SOI substrate. Impurity ions are implanted into the silicon layer of the SOI substrate such that a peak ion concentration along a vertical depth of the silicon layer is located between an intermediate horizontal plane of the silicon layer and the lower surface of the silicon layer inclusive, wherein the intermediate horizontal plane extends horizontally within the silicon layer at half a vertical depth of the silicon layer. A gate electrode is formed on the second insulating layer.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: November 30, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noriyuki Miura
  • Patent number: 6815282
    Abstract: Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corp.
    Inventors: William R. Dachtera, Rajiv V. Joshi, Werner A. Rausch
  • Patent number: 6815794
    Abstract: Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a semiconductor substrate, and an epitaxial layer having the first conductivity type, which covers an entire surface of the semiconductor substrate. A device isolation structure is disposed such that the device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. The device isolation structure includes an upper isolation structure penetrating an epitaxial layer as well as a lower isolation structure formed in the semiconductor substrate under the upper isolation structure.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa-Sook Shin, Kwang-Dong Yoo
  • Publication number: 20040217429
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Application
    Filed: May 25, 2004
    Publication date: November 4, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Patent number: 6800518
    Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: October 5, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi, Sandip Tiwari
  • Publication number: 20040188769
    Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.
    Type: Application
    Filed: October 2, 2003
    Publication date: September 30, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hitoshi Tsuno
  • Publication number: 20040169251
    Abstract: A power IC for an automobile engine control unit incorporating at least one semiconductor device comprising an N-channel insulated-gate filed-effect transistor formed on an SOI substrate, having an N-type layer having a concentration higher than a concentration of an N-type layer in contact with a p-body layer contacting a gate oxide film of the transistor. The high concentration N-type layer is formed in a region covering at most 95% of the source-drain distance between the p-body layer and a drain electrode of the transistor in the silicon substrate over an interface of a buried oxide film, the silicon substrate being in contact with both the field oxide film and the high concentration N-type layer contacting the drain electrode.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 2, 2004
    Inventors: Takasumi Ohyanagi, Atsuo Watanabe
  • Patent number: 6784042
    Abstract: An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one d
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: August 31, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventor: Leonardi Salvatore
  • Patent number: 6784065
    Abstract: A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow through the transistor, while the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: August 31, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Abdalla Aly Naem
  • Patent number: 6780695
    Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: August 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Seshadri Subbanna, Basanth Jagannathan, Gregory G. Freeman, David C. Ahlgren, David Angell, Kathryn T. Schonenberg, Kenneth J. Stein, Fen F. Jamin
  • Patent number: 6777772
    Abstract: Trenches for defining chip areas are formed on the surface of a semiconductor substrate so that outlines of side walls of each of the trenches have recesses or protrusions. Then, a sputtering film is so formed as to be continuous in an area bridging the surface of each of the chip areas and the inside surface of each of the trenches, and the semiconductor substrate is diced along lines outside the trenches.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Taya, Takio Ohno, Naofumi Murata
  • Publication number: 20040150020
    Abstract: In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.
    Type: Application
    Filed: August 27, 2003
    Publication date: August 5, 2004
    Applicants: Elpida Memory, Inc., Hitachi, Ltd.
    Inventors: Satoru Yamada, Ryo Nagai, Kiyonori Oyu, Ryoichi Nakamura, Norikatsu Takaura
  • Publication number: 20040129982
    Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 8, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Katsuya Oda, Katsuyoshi Washio
  • Publication number: 20040124477
    Abstract: A semiconductor integrated circuit device having a capacitor element including a lower electrode provided over an element isolation region of a principal surface of a semiconductor substrate, and an upper electrode provided over the lower electrode via a dielectric film interposed therebetween, has oxidation resistant films between the element isolation region of the principal surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 1, 2004
    Inventors: Shinichi Minami, Fukuo Oowada, Xiaudong Fang
  • Patent number: 6744113
    Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: June 1, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kuroi, Tomohiro Yamashita, Katsuyuki Horita
  • Publication number: 20040094784
    Abstract: A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The barrier implanted region is formed by conducting a plurality of deep implants at different energies and doping levels below the isolation region. The deep implants reduce surface leakage and dark current and increase the capacitance of the photodiode by acting as a reflective barrier to electrons generated by light in the doped region of the second conductivity type of the photodiode.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Inventors: Howard Rhodes, Chandra Mouli
  • Publication number: 20040092094
    Abstract: The present invention provides a unique methodology for device and process technology that results in significant improvements in the parameters of the active devices of all integrated technologies including: bipolar, CMOS, BiCmos, BCD (Bipolar, Cmos, DMOS), and DMOS. The approach results in fewer process steps than the standard approach in each of these technologies, while providing lower capacitance, higher speed, lower power dissipation, lower Ron, lower ground resistance, lower output resistance, reduced de-biasing at high current, higher breakdown voltage, higher beta and over a broader current range while providing significant reduction in die size. Use of this approach also results in improved Schottky diodes and solar cells.
    Type: Application
    Filed: September 24, 2003
    Publication date: May 13, 2004
    Inventor: John Durbin Husher
  • Patent number: 6734524
    Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 11, 2004
    Assignee: Motorola, Inc.
    Inventors: Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, Amitava Bose, Todd Roggenbauer, Paul Hui
  • Patent number: 6729886
    Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R. Efland, Chin-Yu Tsai
  • Patent number: 6730557
    Abstract: A semiconductor device having a bipolar transistor which is capable of high integration, and a semiconductor device in which the bipolar transistor has good characteristic properties. A process for producing said semiconductor device.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: May 4, 2004
    Assignee: Sony Corporation
    Inventor: Chihiro Arai
  • Patent number: 6706580
    Abstract: A plurality of memory cell transistors are formed on a principal surface of a semiconductor substrate in a plurality of active regions defined by an isolation region. Each memory cell transistor uses one word line as its gate electrode and has a pair of source and drain regions defined by the gate electrode and the isolation region. One of a pair of source and drain regions is connected to one of a plurality of bit lines, and the other region is connected to one of a plurality of capacitors. Three sides of the other region are defined by the isolation region. The other region includes a first impurity doped region extending to under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: March 16, 2004
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Koichi Hashimoto
  • Patent number: 6682966
    Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: January 27, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Seizo Kakimoto, Masayuki Nakano, Kouichiro Adachi
  • Publication number: 20040014273
    Abstract: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 22, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Paul A. Farrar
  • Publication number: 20040004250
    Abstract: An impurity-diffused layer having an extension structure is formed first by implanting Sb ion as an impurity for forming a pocket region; then by implanting N as a diffusion-suppressive substance so as to produce two peaks in the vicinity of the interface with a gate electrode and at an amorphous/crystal interface which serves as an defect interface generated by the impurity in the pocket region; and by carrying out ion implantations for forming an extension region and deep source and drain regions.
    Type: Application
    Filed: June 20, 2003
    Publication date: January 8, 2004
    Inventors: Youichi Momiyama, Kenichi Okabe, Takashi Saiki, Hidenobu Fukutome
  • Patent number: 6674146
    Abstract: An apparatus including a contact point on a substrate; a first dielectric layer comprising a material having a dielectric constant less than five formed on the contact point, and a different second dielectric layer formed on the substrate and separated from the contact point by the first dielectric layer. Collectively, the first and second dielectric layers comprise a composite dielectric layer having a composite dielectric constant value. The contribution of the first dielectric layer to the composite dielectric value is up to 20 percent. Also, a method including depositing a composite dielectric layer over a contact point on a substrate, the composite dielectric layer comprising a first material having a dielectric constant less than 5 and a second different second material, and forming a conductive interconnection through the composite dielectric layer to the contact point.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: January 6, 2004
    Assignee: Intel Corporation
    Inventor: Loren A. Chow
  • Patent number: 6667201
    Abstract: The present invention discloses a method for manufacturing a flash memory cell having a horizontal surrounding gate (HSG). The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell composed of a semiconductor film is encompassed and surrounded by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence. In addition, the floating gate and the control gate are also formed on the trench below the channel. Therefore, the leakage current of the channel can be reduced, and the short channel effect can be avoided. Furthermore, the coupling capacitor between the control gate and the floating gate is increased without increasing the cell size. Besides, the data can be programmed and erased by a Fowler-Nordheim (FN) tunneling effect.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: December 23, 2003
    Assignee: Windbond Electronics Corporation
    Inventor: Wen-Yueh Jang
  • Publication number: 20030230786
    Abstract: A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 18, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Kim, Ki-Nam Kim
  • Patent number: 6664150
    Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: December 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Edward J. Nowak, Jed H. Rankin, Minh H. Tong
  • Publication number: 20030228730
    Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 11, 2003
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Chin-Yu Tsai, Dale Skelton
  • Publication number: 20030228729
    Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 11, 2003
    Inventors: Taylor R. Efland, David A. Grant, Ramanathan Ramani, Dale Skelton, David D. Briggs, Chin-Yu Tsai
  • Patent number: 6660599
    Abstract: A semiconductor device is formed by including the step of forming a polycrystalline silicon layer on a semiconductor substrate which includes a pad oxide. A trench is formed in the semiconductor substrate by etching sequentially a part of the polycrystalline silicon layer, a part of the pad oxide layer, and a part of the semiconductor substrate. An oxide layer spacer is formed on the walls of the trench and the side walls of the etched pad oxide layer and the etched polycrystalline silicon layer. A nitride liner is formed on the oxide layer spacer. The trench is filled with an insulating layer on the nitride liner and the insulating layer is planarized until the polycrystalline silicon layer is exposed. And then the polycrystalline silicon layer is dry-etched.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: December 9, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-sik Han, Kyoung-hyun Kim
  • Patent number: 6657262
    Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: December 2, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Patti
  • Patent number: 6653181
    Abstract: A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: November 25, 2003
    Assignee: Agere Systems Inc.
    Inventors: John Michael Hergenrother, Donald Paul Monroe
  • Patent number: 6653194
    Abstract: Disclosed is a method for forming a contact hole in the process of manufacturing a logic device employing a shallow trench isolation (STI) method. The method prevents an isolation region from being damaged because there is little overlap margin for a contact hole in the active region, when a contact hole is formed in an isolation region beyond the border of an active region, that is, when a borderless contact hole is formed. According to the method, a silicon nitride layer used as an etch-stop layer is formed in the process of providing the STI, thereby avoiding deterioration of the characteristics of a resulting semiconductor device.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: November 25, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kun Joo Park