Including Additional Vertical Channel Insulated Gate Field Effect Transistor Patents (Class 438/209)
  • Publication number: 20020048865
    Abstract: A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating layer is etched proximate the line along at least a portion of at least one sidewall of the line. An insulating spacer forming layer is then deposited over the substrate and the line. It is anisotropically etched to form an insulating sidewall spacer. A method of forming a local interconnect comprises forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates.
    Type: Application
    Filed: August 31, 2001
    Publication date: April 25, 2002
    Inventor: H. Montgomery Manning
  • Publication number: 20020028548
    Abstract: A circuit and method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.
    Type: Application
    Filed: July 20, 2001
    Publication date: March 7, 2002
    Applicant: STMicroelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Mehdi Zamanian, David Charles McClure
  • Publication number: 20020025619
    Abstract: This specification disclosed a multilayer film structure of a tunneling magneto-resistor and the manufacturing of the same, the structure being able to increase the tunneling magneto-resistance (TMR) ratio and to decrease the difficulty in manufacturing. The multilayer film structure disclosed herein forms, in a three-layer film structure composed of two layers of ferromagnetic films and an insulating layer provided in between, a layer of moderately thick ferromagnetic metal insertion between one of the ferromagnetic film and the insulating layer. Through the insertion the tunneling magneto-resistance ratio can be greatly increased and the thickness of the insulating layer is increased to the range where the manufacturing difficulty is lowered.
    Type: Application
    Filed: December 19, 2000
    Publication date: February 28, 2002
    Inventors: Chi-Kuen Lo, Chia-Hwo Ho, Minn-Tsong Lin, Yeong-Der Yao, Der-Ray Huang
  • Publication number: 20010044190
    Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. According to this method, a semiconductor substrate is first provided. A pad layer is formed over the substrate. Then, a deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is formed to fill the deep trench. The pad layer, the substrate, the first and the second conductive layers and the collar oxide layer are patterned. A first insulating layer is deposited to form the Shallow Trench Isolation. Both sides of the Shallow Trench Isolation and a portion of the second conductive layer are removed to form a buried strap and an opening. The pad layer is removed. A second insulating layer is formed over the substrate and the buried strap, and is removed after forming a well. A third insulating layer is formed on the substrate.
    Type: Application
    Filed: May 15, 2001
    Publication date: November 22, 2001
    Inventors: Kuen-Chy Heo, Jeng-Ping Lin
  • Patent number: 6300199
    Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: October 9, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Alan R. Reinberg
  • Patent number: 6255689
    Abstract: A flash memory cell structure and its method of manufacture. The flash memory cell has a vertical configuration. An opening and then a trench are formed in a substrate by etching. The trench (defined as the recessed section of the substrate) is used for forming a shallow trench isolation structure. The substrate region between two neighboring openings (defined as the protruding section of the substrate) is used for forming a common drain and a channel. A source terminal is formed in the substrate at the upper comer next to the shallow trench structure. A tunnel oxide layer is formed over the substrate surface of the opening. A floating gate and a dielectric layer are formed over the tunnel oxide layer. A control gate is formed inside the opening.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: July 3, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Robin Lee
  • Patent number: 6255699
    Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: July 3, 2001
    Assignee: International Business Machines Corporation
    Inventors: John A. Bracchitta, Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman
  • Patent number: 6207484
    Abstract: A method for fabricating a BiCDMOS device where bipolar, CMOS and DMOS transistors are formed on a single wafer is provided. A semiconductor region of a second conductivity type is formed on a semiconductor substrate of a first conductivity type. Well regions of first and second conductivity types are formed within the semiconductor region. Then, an oxidation passivation layer pattern defining a region where a pad oxide layer and a field oxide layer are to be formed is formed on a surface of the substrate where the well regions have been formed. Impurity ions of the first conductivity type are implanted into the entire surface of a region where the field oxide layer is to be formed, using the oxidation passivation layer pattern as an ion implantation mask. An ion implantation mask pattern defining a field region of the second conductivity type is formed on the substrate where the oxidation passivation layer has been formed.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: March 27, 2001
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jong-Hwan Kim, Suk-Kyun Lee, Yong-Cheol Choi, Chul-Joong Kim
  • Patent number: 6201293
    Abstract: The present invention relates to electro optical devices with a reduced filter thinning on the edge pixels and a method for reducing the thinning of filter layers on the pixels closest to the edge of an electro optical device such as a photosensitive chip, as would be used, for example, in a full-color digital copier or scanner. A semiconductor wafer includes a main surface defining a plurality of chip areas and tab regions separated by grooves, wherein the chip areas include inner photosites, outer photosites and bonding pads. A plurality of dams are deposited over the main surface in the tab regions, and a clear layer is deposited over the main surface exclusive of the bonding pads. Alternatively, a clear layer is deposited over the main surface exclusive of the bonding pads, and a plurality of tabs is then deposited in the tab regions on the main surface.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: March 13, 2001
    Assignee: Xerox Corporation
    Inventors: Brian T. Ormond, Josef E. Jedlicka, Thomas Grimsley, Paul A. Hosier
  • Patent number: 6197640
    Abstract: A method of manufacturing a semiconductor component includes providing a semiconductor substrate (200) having top and bottom surfaces, forming a drain electrode (160) at the bottom surface of the semiconductor substrate (200), and simultaneously forming source and gate electrodes (251, 254, 255, 253) at the first surface of the semiconductor substrate (200).
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: March 6, 2001
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Robert B. Davies
  • Patent number: 6100123
    Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N.sup.+ and P.sup.+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N.sup.+ diffusion to said P.sup.+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P.sup.+ diffusion is formed in the N well in the pillar adjacent the distal end and a N.sup.+ diffusion is formed in the P well in the pillar adjacent the distal end.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: John A. Bracchitta, Jack A. Mandelman, Stephen A. Parke, Matthew R. Wordeman
  • Patent number: 6092281
    Abstract: A package for a device includes a substrate having a common voltage plane and a mounting region. The device is mounted to the mounting region. An electrically conductive dam structure is disposed on the upper surface of the substrate circumscribing the perimeter of the mounting region. The electrically conductive dam structure is coupled to the common voltage plane. An electrically insulating encapsulant at least partially fills the pocket defined by the substrate and the electrically conductive dam structure. The electrically insulating encapsulant contacts the electrically conductive dam structure. An electrically conductive encapsulant overlies the electrically insulating encapsulant and is coupled to the electrically conductive dam structure.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: July 25, 2000
    Assignee: Amkor Technology, Inc.
    Inventor: Thomas P. Glenn
  • Patent number: 6090652
    Abstract: Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: July 18, 2000
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jae-Kap Kim
  • Patent number: 6063703
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connecting holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: May 16, 2000
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 6017797
    Abstract: There is provided a method of fabricating a semiconductor device including, a first conductivity type MOSFET, a second conductivity type MOSFET, and a power MOSFET having a high breakdown voltage, and having a drain offset region formed in the substrate between the drain region and a channel region located below the gate electrode, and containing first conductivity type impurities therein at such a concentration that carriers are depleted in an operation of the semiconductor device, the method including the steps, in sequence, of (a) forming gate electrodes on the substrate in first, second and third regions where the first conductivity type MOSFET, the second conductivity type MOSFET, and the power MOSFET are to be fabricated, respectively, (b) introducing first conductivity type impurities into the substrate at such a concentration that carriers are depleted in an operation of the semiconductor device, (c) introducing first conductivity type impurities into the substrate with both the second region and a re
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: January 25, 2000
    Assignee: NEC Corporation
    Inventor: Akio Furukawa
  • Patent number: 5976937
    Abstract: Method of making transistors having ultrashallow source and drain junction with reduced gate overlap may comprise forming a first gate electrode (124) separated from a first active area (126) of a semiconductor layer (112) by a first gate insulator (130). A second gate electrode (140) may be formed substantially perpendicular to the first gate electrode (124) and separated from a second active area (142) of the semiconductor layer by a second gate insulator (146). A masking layer (160) may be formed over the semiconductor layer (112) and expose a source and a drain section (162 and 164) of the first active area (126) and a source and a drain section (166 and 168) of the second active area (142). Dopants may be implanted from a first direction substantially parallel to the first gate electrode (124) into the source and drain sections (166 and 168) of the first active area (126).
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: November 2, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Mark S. Rodder, Mahalingam Nandakumar
  • Patent number: 5970343
    Abstract: In the manufacture of an MOS gated semiconductor device, indentations are provided on a surface of a semiconductor wafer extending inwardly of respective spaced apart regions at the wafer surface having doping concentrations greater than that present in the remainder of the wafer. A layer of silicon having a doping concentration less than that of the substrate is conformally provided on the substrate surface whereby the indentations in the substrate surface are replicated on the surface of the silicon layer. Dopants in the substrate regions are then out-diffused into the silicon layer to provide highly doped buried regions within the layer. Then, using the silicon layer surface indentations as photomask alignment marks, gate electrode structures are formed on and within the silicon layer in preselected orientation relative to the buried regions. The buried regions provide low resistance paths for current through the resulting devices.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: October 19, 1999
    Assignee: Harris Corp.
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 5900662
    Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: May 4, 1999
    Assignees: SGS Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
  • Patent number: 5618743
    Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 8, 1997
    Assignee: Siliconix incorporated
    Inventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
  • Patent number: 4601916
    Abstract: An economical process for producing metal plated through holes in metal core circuit boards which permits the formation of small holes and fine conductor lines is disclosed. A metal sheet, which will become the core of a metal core circuit board, is provided with insulation layers on both sides, and through holes are provided through the insulation layers. The process involves incorporating fillers in a resinous coating solution which is electrophoretically applied to the hole walls to form an insulating layer of uniform thickness thereon. An increased diameter in the metal wall portion of each hole acts to restrict flow of the filled resinous coating solution during cure resulting in a straight hole wall. The coating is adhesion promoted and a metal layer is deposited thereon.
    Type: Grant
    Filed: July 18, 1984
    Date of Patent: July 22, 1986
    Assignee: Kollmorgen Technologies Corporation
    Inventor: James J. Arachtingi