Vertical Channel Patents (Class 438/212)
  • Patent number: 8890252
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
  • Patent number: 8883576
    Abstract: Provided are methods of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, forming a mask layer on the mold layer, etching the mold layer using the mask layer as an etch mask to form a channel hole penetrating the mold layer, shrinking the mask layer to provide a reduced mask layer, forming a spacer layer to cover the reduced mask layer, and forming a vertical channel to fill the channel hole and be electrically connected to the substrate. As a result, the channel hole can have an enlarged entrance.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinkwan Lee, Yoochul Kong, Seongsoo Lee
  • Patent number: 8883593
    Abstract: A semiconductor pillar which has a first conductivity type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductivity type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductivity type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kazuhiro Nojima
  • Patent number: 8872243
    Abstract: A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fumitake Mieno
  • Patent number: 8859369
    Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: October 14, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Publication number: 20140264559
    Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.
    Type: Application
    Filed: April 19, 2013
    Publication date: September 18, 2014
    Inventors: Tai-I Yang, Hong-Seng Shue, Kun-Ming Huang, Tzu-Cheng Chen, Ming-Che Yang, Po-Tao Chu
  • Patent number: 8835977
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
  • Patent number: 8828817
    Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Patent number: 8829641
    Abstract: In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 9, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Bruce D. Marchant
  • Patent number: 8802524
    Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
  • Patent number: 8803205
    Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu
  • Patent number: 8796123
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda
  • Patent number: 8796085
    Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 5, 2014
    Inventors: Viktor Koldiaev, Rimma Pirogova
  • Publication number: 20140206161
    Abstract: A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure. The first dummy gate structure is removed after forming the protective layer, thereby providing a first trench. A capping layer (e.g., silicon) is formed in the first trench. A metal gate structure may be formed on the capping layer. The protective layer may protect the second dummy gate structure during the removal of the first dummy gate structure.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsu-Hsiu Perng, Zhao-Cheng Chen, Chun-Hsiang Fan, Ming-Huan Tsai
  • Patent number: 8772096
    Abstract: Provided are a method of forming a contact and a method of manufacturing a phase change memory device using the same. The method of forming a contact includes forming on a substrate an insulating layer pattern having first sidewalls extending in a first direction and second sidewalls extending in a second direction perpendicular to the first direction and which together delimit contact holes, forming semiconductor patterns in lower parts of the contact holes, forming isolation spacers on the semiconductor pattern and side surfaces of the first sidewalls to expose portions of the semiconductor patterns, and etching the exposed portions of the semiconductor patterns using the isolation spacers as a mask to divide the semiconductor patterns into a plurality of finer semiconductor patterns.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Pil Ko, Eun-Jung Kim, Yong-Jun Kim
  • Patent number: 8772109
    Abstract: A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jean-Pierre Colinge
  • Patent number: 8754470
    Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu
  • Patent number: 8748973
    Abstract: A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: June 10, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8748977
    Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor layer 2 of a wide band gap semiconductor arranged on a principal surface of a substrate 1; a trench 5 arranged in the semiconductor layer and including a bottom surface, a plurality of main side surfaces, and a plurality of corner side surfaces each connecting together two adjacent main side surfaces; a gate insulating film 6 arranged on the bottom surface, the main side surfaces and the corner side surfaces of the trench 5; and a gate electrode 8 arranged in the trench, wherein the semiconductor layer includes a drift region 2d of a first conductivity type, and a body region 3 of a second conductivity type arranged on the drift region; the trench runs through the body region 3 and has the bottom surface inside the drift region; the corner side surfaces of the trench do not have a depressed portion; the gate insulating film 6 is thicker on the corner side surfaces of the trench than on the main side surfaces o
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventor: Chiaki Kudou
  • Patent number: 8748247
    Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region, and doping top of the semiconductor substrate to form a doped layer at top surface of the semiconductor substrate over the first region and the second region. The method also includes etching the doped layer to form a first sub-fin in the first region and a first sub-fin in the second region, and forming an insulating layer over the semiconductor substrate including the first sub-fin in the first region and the first sub-fin in the second region. Further, the method includes removing top portions of the first sub-fin in the first region and the first sub-fin in the second region and forming corresponding second sub-fins.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Mieno Fumitake
  • Patent number: 8735227
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 27, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8729617
    Abstract: A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: May 20, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Kyun Kim
  • Patent number: 8728890
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer, having a body top surface and a body bottom surface; forming a source; forming an active region contact trench that extends through the source and the body into the drain, wherein bottom surface of the active region contact trench is formed to include at least a portion that is shallower than the body bottom surface; and disposing a contact electrode within the active region contact trench.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: May 20, 2014
    Assignee: Alpha & Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Publication number: 20140134811
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8709893
    Abstract: The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: April 29, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yi Su, Daniel Ng, Anup Bhalla, Jun Lu
  • Publication number: 20140106523
    Abstract: The present invention is a semiconductor device comprising a semiconducting low doped vertical super-thin body (VSTB) formed on Dielectric Body Wall (such as STI-wall as isolating substrate) having the body connection to bulk semiconductor wafer on the bottom side, isolation on the top side, and the channel, gate dielectric, and gate electrode on opposite to STI side surface. The body is made self-aligned to STI hard mask edge allowing tight control of body thickness. Source and Drain are made by etching holes vertically in STI at STI side of the body and filling with high doped crystalline or poly-Si appropriately doped with any appropriate silicides/metal contacts or with Schottky barrier Source/Drain. Gate first or Gate last approaches can be implemented. Many devices can be fabricated in single active area with body isolation between the devices by iso-plugs combined with gate electrode isolation by iso-trenches.
    Type: Application
    Filed: July 11, 2013
    Publication date: April 17, 2014
    Inventors: Viktor Koldiaev, Rimma Pirogova
  • Patent number: 8698235
    Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 15, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8685788
    Abstract: The present invention belongs to the technical field of semiconductor devices and specifically relates to a method for manufacturing a nanowire tunneling field effect transistor (TFET). In the method, the ZnO nanowire required is developed in a water bath without the need for high temperatures and high pressure, featuring a simple solution preparation, convenient development and low cost, as well as constituting MOS devices of vertical structure with nanowire directly, thus omitting the nanowire treatment in the subsequent stage. The present invention has the advantages of simple structure, convenient manufacturing, and low cost, and control of the nanowire channel developed and the MOSFET array with vertical structure made of it though the gate, so as to facilitate the manufacturing of large-scale MOSFET array directly.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 1, 2014
    Assignee: Fudan University
    Inventors: Weining Bao, Chengwei Cao, Pengfei Wang, Wei Zhang
  • Patent number: 8679903
    Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 8673700
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 18, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy
  • Patent number: 8664048
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: March 4, 2014
    Assignee: Northrop Grummen Systems Corporation
    Inventor: John V. Veliadis
  • Publication number: 20140054584
    Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
  • Patent number: 8653504
    Abstract: A complementary tunneling field effect transistor and a method for forming the same are provided. The complementary tunneling field effect transistor comprises: a substrate; an insulating layer, formed on the substrate; a first semiconductor layer, formed on the insulating layer and comprising first and second doped regions; a first type TFET vertical structure formed on a first part of the first doped region and a second type TFET vertical structure formed on a first part of the second doped region, in which a second part of the first doped region is connected with a second part of the second doped region and a connecting portion between the second part of the first doped region and the second part of the second doped region is used as a drain output; and a U-shaped gate structure, formed between the first type TFET vertical structure and the second type TFET vertical structure.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: February 18, 2014
    Assignee: Tsinghua University
    Inventors: Renrong Liang, Jun Xu, Jing Wang
  • Patent number: 8643094
    Abstract: A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Sinopower Semiconductor, Inc.
    Inventors: Sung-Shan Tai, Teng-hao Yeh, Chia-Hui Chen
  • Patent number: 8643096
    Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Eui-Seong Hwang
  • Patent number: 8633095
    Abstract: A semiconductor device with a high voltage compensation component is manufactured by etching a trench into an epitaxial semiconductor material doped with n-type dopant atoms and p-type dopant atoms and disposing a first semiconductor or insulating material along one or more sidewalls of the trench. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for the n-type dopant atoms than the p-type dopant atoms. A second semiconductor material is disposed in the trench along the first semiconductor or insulating material. The second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: January 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Hans Weber
  • Publication number: 20140001541
    Abstract: A transistor including a recessed gate structure having improved doping characteristics and a method for forming such a transistor. The transistor includes a recess in a semiconductor substrate, where the recess is filled with a recessed gate structure including an impurity doped layer and a layer doped with a capture species. The capture species accumulates the impurity and diffuses the impurity to other layers of the recessed gate structure.
    Type: Application
    Filed: December 19, 2012
    Publication date: January 2, 2014
    Applicant: SK HYNIX INC.
    Inventors: Kyong-Bong ROUH, Yong-Seok EUN, Mi-Ri LEE
  • Patent number: 8618604
    Abstract: A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: December 31, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Atsushi Narazaki
  • Patent number: 8613861
    Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: December 24, 2013
    Assignee: Rexchip Electronics Corporation
    Inventors: Hsiao-chia Chen, Sheng-chang Liang, Chien-hua Tsai, Masahiko Ohuchi
  • Patent number: 8603891
    Abstract: Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Shyam Surthi
  • Patent number: 8592902
    Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Texas Instrument Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 8580634
    Abstract: In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a patterned hard mask above the fin, wherein the patterned hard mask has an opening that exposes a portion of the fin, performing a fin reflow process through the opening in the patterned hard mask on the exposed portion of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration, and forming a gate structure that extends at least partially around the nanowire structure.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8574974
    Abstract: Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 5, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Yukimasa Minami
  • Publication number: 20130288440
    Abstract: A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor.
    Type: Application
    Filed: June 21, 2013
    Publication date: October 31, 2013
    Inventors: Dureseti Chidambarrao, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus
  • Patent number: 8563373
    Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung, Soo-Ho Shin
  • Patent number: 8564057
    Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: October 22, 2013
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng
  • Publication number: 20130270512
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 17, 2013
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 8551834
    Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 8, 2013
    Assignee: QuNano AB
    Inventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
  • Patent number: 8541274
    Abstract: In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 24, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Jr., Kangguo Cheng, Ali Khakifirooz
  • Patent number: 8530300
    Abstract: Disclosed is a method of forming a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type, and a semiconductor device with drift regions of a first doping type and compensation regions of a second doping type.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: September 10, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Armin Willmeroth, Anton Mauder, Franz Hirler