Utilizing Gate Sidewall Structure Patents (Class 438/230)
  • Publication number: 20120142151
    Abstract: N-type semiconductor region and P-type semiconductor region are provided in a surface region of a semiconductor substrate. Insulating film and silicon containing film are laminated on the semiconductor substrate. P-type impurities are introduced into a first portion of the silicon containing film above the N-type semiconductor region. The first portion of the silicon containing film is thinned in the thickness direction. N-type impurities are introduced into a second portion of the silicon containing film above the P-type semiconductor region. A mask is provided on the silicon containing film. The first and second portions of the silicon containing film are etched together using the mask as an etching mask to form gate electrode films above the N-type and P-type semiconductor regions respectively. P-type and N-type impurities are introduced into the N-type and P-type semiconductor regions to form P-type and N-type source and drain layers.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 7, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Sasaki
  • Publication number: 20120135572
    Abstract: A gate electrode is formed on a surface of a semiconductor substrate. A resist mask is formed that covers both end faces of the gate electrode in a gate width direction intersecting a gate length direction. Impurity ions are implanted into the semiconductor substrate in an implantation direction having a gate length direction component and a gate width direction component, to form a low-concentration impurity layer overlapping with the gate electrode at both sides of the gate electrode in the surface of the semiconductor substrate. A sidewall is formed that covers a side surface of the gate electrode. Impurity ions are implanted using the gate electrode and the sidewall as a mask, to form a high-concentration impurity layer apart from the gate electrode at both sides of the gate electrode on the surface of the semiconductor substrate.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 31, 2012
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Mayumi SHIBATA
  • Patent number: 8183605
    Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: May 22, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Markus Lenski, Andreas Gehring
  • Patent number: 8174060
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 8173524
    Abstract: Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Anthony I. Chou, Abhishek Dube, Dominic J. Schepis
  • Publication number: 20120104507
    Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and g
    Type: Application
    Filed: November 3, 2010
    Publication date: May 3, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman
  • Publication number: 20120098590
    Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.
    Type: Application
    Filed: August 26, 2011
    Publication date: April 26, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Tathagata Chatterjee, Robert C. Bowen
  • Publication number: 20120097977
    Abstract: A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 26, 2012
    Inventor: Tadashi YAMAGUCHI
  • Publication number: 20120088342
    Abstract: Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.
    Type: Application
    Filed: August 26, 2011
    Publication date: April 12, 2012
    Inventors: Li Ming, Sangpil Sim, Kang-ill Seo, Changwoo Oh, Dongil Bae
  • Patent number: 8154067
    Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
  • Patent number: 8154088
    Abstract: Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: April 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Antoine Khoueir, Subhash Srinivas Pidaparthi, Henry Jim Fulford
  • Publication number: 20120080722
    Abstract: A semiconductor device includes: a semiconductor substrate; a SiGe relaxed layer on the semiconductor substrate; an NMOS transistor on the SiGe relaxed layer; and a PMOS transistor on the SiGe relaxed layer, in which the NMOS transistor includes a tensile strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer; and the PMOS transistor includes a compressive strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer. The loss of the strained semiconductor material can be avoided and meanwhile the stress in the channel can be better maintained.
    Type: Application
    Filed: February 25, 2011
    Publication date: April 5, 2012
    Applicant: Institute of Microelectronics,Chinese Academy of Sciences
    Inventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
  • Publication number: 20120074503
    Abstract: A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: International Business Machines Corporation
    Inventors: Henry K. Utomo, Sameer Hemchand Jain, Ravikumar Ramachandran, Cung D. Tran
  • Patent number: 8138055
    Abstract: In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: March 20, 2012
    Assignees: Infineon Technologies AG, Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann, Jingyu Lian, Yung Fu Chong
  • Publication number: 20120058610
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 8, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Katsuaki Ookoshi, Masatoshi Nishikawa, Yosuke Shimamune
  • Patent number: 8120104
    Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8114729
    Abstract: A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: February 14, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Shashank Ekbote, Kamel Benaissa, Greg C. Baldwin, Borna Obradovic
  • Patent number: 8114730
    Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: February 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abraham Yoo, Hee-Sung Kang, Heon-Jong Shin
  • Patent number: 8105960
    Abstract: A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Carl J. Radens
  • Patent number: 8097517
    Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: January 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Jung Shin
  • Publication number: 20120001254
    Abstract: In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors.
    Type: Application
    Filed: January 13, 2011
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Peter Javorka, Roman Boschke
  • Publication number: 20110281410
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Application
    Filed: July 26, 2011
    Publication date: November 17, 2011
    Inventors: JINPING LIU, Alex KH See, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8058123
    Abstract: A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 15, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Jinping Liu, Hai Cong, Binbin Zhou, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia
  • Publication number: 20110269278
    Abstract: In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.
    Type: Application
    Filed: December 9, 2010
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Andreas Kurz, Uwe Griebenow, Thilo Scheiper
  • Patent number: 8048730
    Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes an isolation area formed on a semiconductor substrate to define NMOS and PMOS areas, a gate insulating layer and a gate formed on each of the NMOS and PMOS areas, a primary gate spacer formed at sides of the gate, LDD areas formed in the semiconductor substrate at sides of the gate, a secondary gate spacer formed at sides of the primary gate spacer, source and drain areas formed in the semiconductor substrate at sides of the gate of the PMOS area; and source and drain areas formed in the semiconductor substrate at sides of the gate of the NMOS area, wherein the source and drain areas of the NMOS area are deeper than the source and drain areas of the PMOS area.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: November 1, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Eun Jong Shin
  • Patent number: 8043912
    Abstract: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate, a second polysilicon layer formed on the element-isolating insulation film, a first silicide layer formed on the first polysilicon layer. And the device further comprising a second silicide layer formed on the second polysilicon layer and being thicker than the first silicide layer.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Matsuda
  • Patent number: 8030154
    Abstract: In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper surface of the gate structure and on an exposed surface of the semiconductor substrate that is adjacent to the gate structure. An upper surface of the metal semiconductor alloy is converted to an oxygen-containing protective layer. The sidewall spacers are removed using an etch that is selective to the oxygen-containing protective layer. A strain-inducing layer is formed over the gate structure and the semiconductor surface, in which at least a portion of the strain-inducing layer is in direct contact with the sidewall surface of the gate structure. In another embodiment, the oxygen-containing protective layer of the metal semiconductor alloy is provided by a two stage annealing process.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 4, 2011
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc.
    Inventors: Ahmet S. Ozcan, Christian Lavoie, Zhen Zhang, Bin Yang
  • Publication number: 20110233688
    Abstract: A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhibin Ren, Kevin K. Chan, Chung-Hsun Lin, Xinhui Wang
  • Patent number: 8026136
    Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: September 27, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yen-Hao Shih, Min-Ta Wu, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
  • Patent number: 8021944
    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide forming region and non-silicide forming region; forming a photoresist pattern as a non-salicide pattern by patterning the photoresist film, so as to cover the non-silicide forming region and open the silicide forming region, with an overhang structure that a bottom is removed more compared to a top; forming a metal film on a top of the photoresist pattern and overall the semiconductor substrate in the silicide forming region; stripping the photoresist pattern and the metal film on the photoresist pattern; and forming a silicide metal film by annealing the metal film remaining on the semiconductor substrate. Therefore, the present invention simplifies a salicide process of a semiconductor device, making it possible to improve yields.
    Type: Grant
    Filed: November 29, 2008
    Date of Patent: September 20, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: In-Cheol Baek
  • Publication number: 20110195550
    Abstract: A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.
    Type: Application
    Filed: January 14, 2011
    Publication date: August 11, 2011
    Inventors: Chong-Kwang CHANG, Sung-Hon Chi, Hong-Jae Shin, Yong-Jin Chung, Young-Mook Oh, Ju-Beom Yi
  • Patent number: 7993998
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: August 9, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ding-Yuan Chen, Chen-Hua Yu
  • Patent number: 7994012
    Abstract: To improve characteristics of a semiconductor device having a nonvolatile memory. There is provided a semiconductor device having a nonvolatile memory cell that performs memory operations by transferring a charge to/from a charge storage film, wherein the nonvolatile memory cell includes a p well formed in a principal plane of a silicon substrate, and a memory gate electrode formed over the principal plane across the charge storage film, and wherein a memory channel region located beneath the charge storage film of the principal plane of the silicon substrate contains fluorine.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuyoshi Shiba
  • Patent number: 7993995
    Abstract: Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Amlan Majumdar, Renee Tong Mo, Zhibin Ren, Jeffrey Sleight
  • Patent number: 7985638
    Abstract: A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: July 26, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masao Okihara
  • Patent number: 7985641
    Abstract: A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 26, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Young Suk Kim, Yosuke Shimamune
  • Patent number: 7968401
    Abstract: A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: June 28, 2011
    Inventors: Martin A. Hilkene, Kartik Santhanam, Yen B. Ta, Peter I. Porshnev, Majeed A. Foad
  • Patent number: 7968414
    Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
  • Publication number: 20110129971
    Abstract: In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.
    Type: Application
    Filed: October 8, 2010
    Publication date: June 2, 2011
    Inventors: Stephan Kronholz, Matthias Kessler, Andreas Kurz
  • Publication number: 20110127614
    Abstract: In sophisticated transistor elements, an additional silicon-containing semiconductor material may be provided after forming the drain and source extension regions, thereby reducing the probability of forming metal silicide regions, such as nickel silicide regions, which may extend into the channel region, thereby causing a significant increase in series resistance. Consequently, an increased degree of flexibility in adjusting the overall transistor characteristics may be achieved, for instance, by selecting a reduced spacer width and the like.
    Type: Application
    Filed: October 15, 2010
    Publication date: June 2, 2011
    Inventors: Thilo Scheiper, Sven Beyer, Jan Hoentschel, Uwe Griebenow
  • Patent number: 7947589
    Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: May 24, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ramachandran Muralidhar, Marwan H. Khater
  • Patent number: 7943462
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: May 17, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Thilo Scheiper, Jan Hoentschel, Markus Lenski
  • Patent number: 7935592
    Abstract: In a case of using a silicon nitride film as an offset spacer for forming an extension region of a transistor, an oxide protective surface is formed by oxygen plasma processing on the surface of the silicon nitride film.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 3, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Watanabe
  • Patent number: 7935590
    Abstract: A method of manufacturing a metal oxide semiconductor is provided. The method includes forming an offset spacer and a disposable spacer around the offset spacer. Then, forming a plurality of epitaxial layers outside the disposable spacer and removing the disposable spacer. In addition, the method includes forming a plurality of source/drain extension areas in the substrate outside the offset spacer and the epitaxial layers. Because the source/drain extension areas are formed after the selective epitaxial growth process, the thermal of the selective epitaxial growth process does not damage the source/drain extension areas.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 3, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Bang-Chiang Lan, Chen-Hua Tsai, Yu-Hsin Lin, Tsung-Lung Tsai, Cheng-Tzung Tsai
  • Patent number: 7923321
    Abstract: A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: April 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Chen Lai, Kong-Beng Thei, Harry Chuang, Gary Shen
  • Patent number: 7906385
    Abstract: A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: March 15, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Markus Lenski, Frank Wirbeleit, Anthony Mowry
  • Patent number: 7902021
    Abstract: A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Anadi Srivastava
  • Patent number: 7872312
    Abstract: A semiconductor device includes a first gate electrode formed in a first region on a semiconductor substrate with a first gate insulating film sandwiched therebetween; and a second gate electrode formed in a second region on the semiconductor substrate with a second gate insulating film sandwiched therebetween. The first gate insulating film includes a first high dielectric constant insulating film with a first nitrogen concentration and the second gate insulating film includes a second high dielectric constant insulating film with a second nitrogen concentration higher than the first nitrogen concentration.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: January 18, 2011
    Assignee: Panasonic Corporation
    Inventor: Hisashi Ogawa
  • Patent number: 7855135
    Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: December 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Isaac Lauer, Renee T. Mo, Jeffrey W. Sleight
  • Patent number: 7851299
    Abstract: The present invention provides a semiconducting device including a substrate including at least one semiconducting region and isolation regions; a gate structure atop the substrate having a gate dielectric layer positioned on the semiconducting region and a metal layer atop the gate dielectric layer, the gate structure having a width equal to or greater than the width of the at least one semiconducting region; and a contact structure including a base having a first width equal to the width of the gate structure and an upper surface having a second width, wherein the first width is greater than the second width. In one embodiment, the contact structure includes a polysilicon conductor and dielectric spacers, wherein each spacer of the dielectric spacer abuts a sidewall of the polysilicon conductor. In another embodiment, the contact structure includes a polysilicon conductor having a tapered sidewall.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventor: Wesley C. Natzle