Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up HBT, reduction in base-collector junction capacity. For the collector-up HBT, window structures around the sidewalls of a collector are used to etch either the emitter layer disposed directly under the external base layer, or an emitter contact layer For the emitter-up HBT, window structures around the sidewalls of an emitter are used to etch either the collector layer disposed directly under the external base layer, or a collector contact layer. In both HBTs, the external base layer is supported by a columnar structure to ensure mechanical strength.

Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (V?CB of less than 1 V).

Abstract: A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a mask for depositing the base contacts. In forming the T-top, its dimensions may be varied, thereby allowing the spacing between the base contacts and emitter to be adjusted.

Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Abstract: The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.

Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.

Abstract: A method of manufacturing a bipolar-complementary metal oxide semiconductor (BiCMOS) is provided. A gate in a CMOS area and a conductive layer pattern defining an opening, which opens an active region in a bipolar transistor area, are simultaneously formed by patterning a gate conductive layer. Thereafter, bipolar transistor manufacturing processes are performed while CMOS manufacturing processes are performed. Accordingly, the number of masks is decreased, and degradation of device characteristics is prevented.

Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

Abstract: The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.

Abstract: A method for manufacturing a bipolar transistor, comprising the steps of: growing on the substrate a first semiconductor; depositing an encapsulation layer etchable with respect to the first semiconductor, forming a sacrificial block at the location of the base-emitter junction; exposing the first semiconductor around spacers formed around said block; forming a second semiconductor, then a third semiconductor etchable with respect to the second semiconductor layer, the encapsulation layer, and the spacers, the sum of the thicknesses of the second semiconductor and the sacrificial layer being substantially equal to the sum of the thicknesses of the encapsulation layer and of the sacrificial block; removing the block and the encapsulation layer; depositing a fourth semiconductor; removing the third semiconductor; and etching an insulating layer to maintain it on the emitter walls and between said emitter and the second semiconductor.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III–V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to promote carrier transport from the emitter region toward the collector region by providing, in the base region, several spaced apart quantum size regions of different thicknesses, with the thicknesses of the quantum size regions being graded from thickest near the collector to thinnest near the emitter.

Abstract: A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.

Abstract: An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) and if the edge terminal region (120) has a part near the substrate which is arranged in the cutout (142) and a part remote from the substrate which is arranged outside the cutout (142) and overlaps the base terminal region (139).

Abstract: According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated between the first and second link spacers, where the first and second link spacers have a height that is substantially less than a height of the sacrificial post. The bipolar transistor also comprises a conformal layer situated over the sacrificial post and the first and second link spacers. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer, the first and second link spacers, the sacrificial post, and the base. The sacrificial planarizing layer may comprise, for example, an organic material such as an organic BARC (“bottom anti-reflective coating”).

Abstract: According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.

Abstract: A transistor includes a base, a collector, and an emitter comprising a group III/VI semiconductor. Microcircuits having at least one metal oxide semiconductor (MOS) transistor and the previously described transistor are provided. Processes for manufacturing a transistor and a BiMOS microcircuit are also provided.

Abstract: A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.

Abstract: One embodiment is a method for fabricating the base of a bipolar transistor where the method comprises placing a first wafer in an undoped epi chamber. Next a first undoped base layer is grown over the first wafer. After growing the first undoped base layer, the first wafer is transferred from the undoped epi chamber into a separate doped epi chamber. A first doped base layer is then grown over the first undoped based layer in the doped epi chamber. While the first wafer is being processed in the doped epi chamber, a second wafer can be processed in the undoped epi chamber. Another embodiment is a structure produced by the disclosed method and yet another embodiment comprises a transfer chamber, a transfer arm, a bake chamber, and a separate undoped epi chamber and a doped epi chamber for practicing the disclosed method.

Abstract: A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

Abstract: A bipolar transistor is provided which includes a collector region, an intrinsic base layer including a single-crystal semiconductor overlying the collector region, and an emitter disposed within a first opening overlying the intrinsic base layer. The bipolar transistor includes a raised extrinsic base, which in turn includes a raised extrinsic base layer and a link-up region which electrically connects the raised extrinsic base layer to the intrinsic base layer. The link-up region also self-aligns the raised extrinsic base to the emitter. The link-up region is disposed in a second opening separate from the first opening and in an undercut region extending from the second opening below the raised extrinsic base layer.

Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, higher order silanes are employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: A heterojunction bipolar transistor (HBT) is disclosed that includes successive emitter, base and collector and sub-collector epitaxial layers and emitter, base and collector contact metals contacting the emitter, base and sub-collector layers respectively. A passivation material is included that covers the uncovered portions of the layers and covers substantially all of the contact metals. The passivation material has a planar surface and a portion of each of the contact metals protrudes from the surface. Planar metals are included on the planar surface, each being isolated from the others and in electrical contact with a respective contact metal. A method for fabricating an HBT is also disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation region includes a recessed surface and a non-recessed surface which are formed utilizing lithography and etching. A SiGe layer is formed on the substrate as well as the recessed non-recessed surfaces of each isolation region, the SiGe layer includes polycrystalline Si regions and a SiGe base region. A patterned insulator layer is formed on the SiGe base region; and an emitter is formed on the patterned insulator layer and in contact with the SiGe base region through an emitter window opening.

Abstract: A semiconductor device includes a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor of the base region is also put into contact with the collector region. Here, the second connection conductor is exclusively connected to the base region, and a partial region of that portion of the base region which lies outside the emitter region, as seen in projection, lying below the second connection conductor is given a smaller flux of dopant atoms. The bipolar transistor is provided with a pn clamping diode which is formed between the partial region and the collector region.

Abstract: The present invention discloses a process of fabricating a semiconductor device comprising the steps of: forming a collector layer of a first conductivity type at a portion of a surface of a semiconductor substrate; forming a collector opening portion in a first insulating layer formed on the semiconductor substrate; epitaxially growing, on the semiconductor substrate of the collector opening portion, a semiconductor layer including a layer of a second conductivity type constituting a base layer; sequentially layering, on the semiconductor substrate, an etching stopper layer against dry etching and a masking layer against wet etching; exposing a part of the etching stopper layer by removing a part of the masking layer by means of dry etching; and by subjecting the exposed etching stopper layer to a wet etching treatment using the remaining masking layer as a mask, forming a base junction opening portion through the etching stopper layer and the masking layer.

Abstract: A semiconductor component includes: a semiconductor substrate (110); an epitaxial semiconductor layer (120) above the semiconductor substrate; a bipolar transistor (770, 870) in the epitaxial semiconductor layer; and a field effect transistor (780, 880) in the epitaxial semiconductor layer. A portion of the epitaxial semiconductor layer forms a base of the bipolar transistor and a gate of the field effect transistor, and the portion of the epitaxial semiconductor layer has a substantially uniform doping concentration. In the same or another embodiment, a different portion of the epitaxial semiconductor layer forms an emitter of the bipolar transistor and a channel of the field effect transistor, and the different portion of the epitaxial semiconductor layer has a substantially uniform doping concentration that can be the same as or different from the substantially uniform doping concentration of the portion of the epitaxial semiconductor layer.

Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.

Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.

Abstract: Selectively implanting carbon in a transistor lowers the collector-to-emitter breakdown (BVCEO) of the transistor. This transistor, with the lowered BVCEO, is then used as a “trigger” device in an Electrostatic Discharge (ESD) power clamp comprising a first low breakdown trigger device and a second high breakdown clamp device. ESD power clamps are constructed using epitaxial base pseudomorphic Silicon Germanium heterojunction transistors in a common-collector Darlington configuration.

Abstract: A bipolar junction transistor (BJT) requires the fabrication of a BJT structure and of a support post which is adjacent to, but physically and electrically isolated from, the BJT structure. The BJT structure includes a semi-insulating substrate, a subcollector, a collector, a base, and an emitter. Metal contacts are formed on the subcollector and emitter to provide collector and emitter terminals. Contact to the structure's base is accomplished with a metal contact which extends from the top of the support post to the edge of the base nearest the support post. The contact bridges the physical and electrical separation between the support post and the base and provides a base terminal for the device. The base contact need extend over the edge of the base by no more than the transfer length associated with the fabrication process. This results in the smaller base contact area over the collector than would otherwise be necessary, and a consequent reduction in base-collector capacitance.

Abstract: A disclosed embodiment is a method for fabricating a SiGe layer, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.

Abstract: A power amplifier includes a substrate, a heat sink for dissipating heat, and a heterojunction bipolar transistor (HBT) disposed on the substrate. The HBT includes a collector, a base, and at least an emitter. The power amplifier further includes an emitter electrode directly connecting the heat sink and the emitter of the HBT. The emitter electrode is a flip-chip bump, and the heat sink is a metal layer that sandwiches the HBT with the substrate. Alternatively, the emitter electrode is a backside via that penetrates the substrate, and the heat sink is a metal layer, disposed on the substrate opposite the HBT.

Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.

Abstract: In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.

Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base. The heterojunction bipolar transistor further comprises a first nitride spacer and a second nitride spacer situated on the base, where the first nitride spacer and the second nitride spacer are separated by a distance substantially equal to a critical dimension. For example, the first nitride spacer and the second nitride spacer may comprise LPCVD or RTCVD silicon nitride. According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter situated between said first nitride spacer and said second nitride spacer, where the emitter has a width substantially equal to the critical dimension. The emitter may, for example, comprise polycrystalline silicon. In another embodiment, a method that achieves the above-described heterojunction bipolar transistor is disclosed.

Abstract: A method for forming a heterojunction bipolar transistor (HBT) includes forming an etch mask atop an emitter cap layer of the HBT to expose a portion of the emitter cap layer, and selectively etching the exposed portion of the emitter cap layer to (1) form a reentry feature and (2) to expose a portion of the emitter layer. The method further includes selectively etching the exposed portion of the emitter layer to expose a portion of the base layer, and forming a metal layer over the exposed portion of the base layer and the exposed portion of the emitter cap layer.

Abstract: According to one exemplary embodiment, a method for fabricating a bipolar transistor, such as a heterojunction bipolar transistor (“HBT”), comprises fabricating a first inner spacer and a second inner spacer on a top surface of a base. The method further comprises forming a first outer spacer adjacent to the first inner spacer and a second outer spacer adjacent to the second inner spacer. According to this exemplary embodiment, the method further comprises depositing an emitter between the first and second inner spacers on the top surface of the base. The method may further comprise depositing an intermediate oxide layer on the first and second outer spacers after forming the first and second outer spacers. The method may further comprise depositing an amorphous layer on the intermediate oxide layer. The method may also comprise depositing an antireflective coating layer on the amorphous layer.

Abstract: A method is provided for etching quaternary interface layers of InxGa1−xAsyP1−y which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H2O2 that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.

Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

Abstract: According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base, where the emitter window stack does not comprise a polysilicon layer. The method further comprises etching an emitter window opening in the emitter window stack. The method further comprises depositing an emitter layer in the emitter window opening and over the antireflective coating layer and etching the emitter layer to form an emitter. The method further comprises etching a first portion of the base oxide layer not covered by the emitter using a first etchant, thereby causing the first portion of the base oxide layer to have a thickness less than a thickness of a second portion of the base oxide layer covered by the emitter.

Abstract: A bipolar heterojunction transistor (HBT) includes a collector layer, a base layer formed on the collector layer, a first transition layer formed on the base layer, an emitter layer formed on the first transition layer, a second transition layer formed on the emitter layer, and an emitter cap layer formed on the second transition layer. Each of the first and second transition layers is formed of a composition that contains an element, the mole fraction of which is graded in such a manner that the conduction band of the HBT is continuous through the base layer, the first and second transition layers, the emitter layer and the emitter cap layer.

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: When InP DHBTs are located in parallel to a crystallographical direction of <011>, there are several advantages in the aspect of device property such as reliability. But, in case of a direction parallel to a general <011>, there exists the limitation in reducing base-collector parasitic capacitance only by collector over-etching technique due to poor lateral-etching characteristic of the InP collector. To overcome such a problem mentioned above and improve device performance, the present invention provides a method of reducing parasitic capacitance using underneath crystallographically selective wet etching, thereby providing a self-alignable, structurally stable device.

Abstract: A method of making vertical diodes and transistors in SiC is provided. The method according to the invention uses a mask (e.g., a mask that has been previously used for etching features into the device) for selective epitaxial growth or selective ion implantation. In this manner, the gate and base regions of static induction transistors and bipolar junction transistors can be formed in a self-aligned process. A method of making planar diodes and planar edge termination structures (e.g., guard rings) is also provided.

Abstract: An epitaxial layer structure that achieves reliable, high speed, and low noise device performance in indium phosphide (InP) based heterojunction bipolar transistors (HBTs) for high data rate receivers and optoelectronic integrated circuits (OEIC). The layer consists of an n+InGaAs subcollector, an n+InP subcollector, an unintentionally doped InGaAs collector, a carbon-doped base, an n-type InP emitter, an n-type InGaAs etch-stop layer, an n-type InP emitter, and an InGaAs cap layer.