Including Diode Patents (Class 438/237)
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Publication number: 20130001696Abstract: A gate electrode and an electrode for protective diode are coupled to each other. An insulating film below the electrode for protective diode makes a leak current flow between the electrode for protective diode and an electron transit layer and an electron supply layer when a voltage equal to or more than a given value is applied to the gate electrode. The given value is higher than a voltage by which a HEMT is on-operated and lower than a breakdown voltage of a gate insulating film.Type: ApplicationFiled: June 26, 2012Publication date: January 3, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi Akiyama, Yoshiyuki Kotani, Toshihiro Wakabayashi, Masato Miyamoto
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Patent number: 8343828Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.Type: GrantFiled: November 28, 2011Date of Patent: January 1, 2013Assignee: Micron Technology, Inc.Inventors: Gurtej Sandhu, Bhaskar Srinivasan
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Publication number: 20120329222Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.Type: ApplicationFiled: September 6, 2012Publication date: December 27, 2012Applicant: SK HYNIX INC.Inventors: Mi Ra CHOI, Jang Uk LEE
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Patent number: 8334179Abstract: A semiconductor system is described, which is made up of a highly n-doped silicon substrate and a first n-silicon epitaxial layer, which is directly contiguous to the highly n-doped silicon substrate, and having a p-doped SiGe layer, which is contiguous to a second n-doped silicon epitaxial layer and forms a heterojunction diode, which is situated above the first n-doped silicon epitaxial layer and in which the pn-junction is situated within the p-doped SiGe layer. The first n-silicon epitaxial layer has a higher doping concentration than the second n-silicon epitaxial layer. Situated between the two n-doped epitaxial layers is at least one p-doped emitter trough, which forms a buried emitter, a pn-junction both to the first n-doped silicon epitaxial layer and also to the second n-doped silicon epitaxial layer being formed, and the at least one emitter trough being completely enclosed by the two epitaxial layers.Type: GrantFiled: September 17, 2008Date of Patent: December 18, 2012Assignee: Robert Bosch GmbHInventors: Ning Qu, Alfred Goerlach
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Publication number: 20120306009Abstract: A semiconductor structure comprises a semiconductor layer of a first conductivity type, trenches extending into the semiconductor layer, and a conductive layer of a second conductivity type lining sidewalls and bottom of each trench and forming PN junctions with the semiconductor layer. A first plurality of the trenches are disposed in a field effect transistor region that comprises a body region of the first conductivity type, source regions of the second conductivity type in the body region, and gate electrodes isolated from the body region and the source regions by a gate dielectric. A second plurality of the trenches are disposed in a Schottky region that comprises a conductive material contacting mesa surfaces of the semiconductor layer between adjacent ones of the second plurality of the trenches to form Schottky contacts. The conductive material also contacts the conductive layer proximate an upper portion of the second plurality of the trenches.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Inventor: Suku Kim
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Publication number: 20120306023Abstract: A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Yu Ma, Fang-Tsun Chu, Kvei-Feng Yen, Yao-Bin Wang
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Patent number: 8318550Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.Type: GrantFiled: April 8, 2011Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventor: Durai Vishak Nirmal Ramaswamy
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Patent number: 8309958Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.Type: GrantFiled: August 31, 2010Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Jun Hirota, Yoko Iwakaji, Moto Yabuki
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Publication number: 20120280307Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.Type: ApplicationFiled: May 2, 2011Publication date: November 8, 2012Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Yi Su, Daniel Ng, Anup Bhalla, Hong Chang, Jongoh Kim, John Chen
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Patent number: 8304816Abstract: An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the amorphous silicon layer, and a transfer gate formed over the substrate adjacent to the photodiode and transferring photoelectrons received from the photodiode.Type: GrantFiled: August 24, 2011Date of Patent: November 6, 2012Assignee: Intellectual Ventures II LLCInventors: Myoung-Shik Kim, Hyung-Jun Kim
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Patent number: 8304822Abstract: Provided is a pixel for picking up an image signal capable of suppressing an occurrence of a cross-talk. The pixel for picking up an image signal includes a substrate surrounded by a trench, a photodiode, and a pass transistor. The photodiode is formed at an upper portion of the substrate and includes a P-type diffusion area and an N-type diffusion area which are joined with each other in a longitudinal direction. The pass transistor is formed at the upper portion of the substrate and includes the one terminal that is the joined P-type diffusion area and the N-type diffusion area, the other terminal that is a floating diffusion area, and a gate terminal disposed between the two terminals. The pixel for picking up an image signal is surrounded by the trench which penetrates the substrate from the upper portion to the lower portion of the substrate, and the trench is filled with an insulator.Type: GrantFiled: August 10, 2007Date of Patent: November 6, 2012Assignee: Siliconfile Technologies Inc.Inventor: Do Young Lee
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Patent number: 8298887Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.Type: GrantFiled: June 25, 2010Date of Patent: October 30, 2012Assignee: Applied Materials, Inc.Inventors: Xinhai Han, Nagarajan Rajagopalan, Ji Ae Park, Bencherki Mebarki, Heung Lak Park, Bok Hoen Kim
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Layout method of semiconductor device with junction diode for preventing damage due to plasma charge
Patent number: 8288223Abstract: A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.Type: GrantFiled: February 2, 2012Date of Patent: October 16, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Young Kim, Jong-Hak Won -
Publication number: 20120248530Abstract: An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.Type: ApplicationFiled: April 4, 2011Publication date: October 4, 2012Inventors: Sik Lui, Yi Su, Daniel Ng, Anup Bhalla
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Publication number: 20120252177Abstract: A gate-edge diode is made in a diode region of a substrate and a non-volatile memory cell is made in an NVM region of the substrate. A first dielectric layer is formed on the substrate in the diode region and the NVM region. A first conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first conductive layer. A second conductive layer is formed over the second dielectric layer. A first mask is formed over the diode region having a first pattern. The first pattern is of a plurality of fingers and a second mask over the NVM region has a second pattern. The second pattern is of a gate stack of the non-volatile memory cell. An etch is performed through the second conductive layer, the second dielectric layer, and the first conductive layer to leave the first pattern of the plurality of fingers in the diode region and the second pattern of the gate stack in the NVM region.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Inventor: Bradley P. Smith
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Patent number: 8252645Abstract: A method for manufacturing a trenched semiconductor power device includes a step of forming said semiconductor power device with a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The method further includes the steps of covering the MOSFET cell with an insulation layer and applying a contact mask for opening a source-body contact trench extending through the source and body regions into an epitaxial layer underneath for filling a contact metal plug therein. And, the method further includes a step of forming an embedded Schottky diode by forming a Schottky barrier layer near a bottom of the source-body contact trench below the contact metal plug with the Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source.Type: GrantFiled: August 7, 2009Date of Patent: August 28, 2012Assignee: Force—Mos Technology CorporationInventor: Fwu-ruan Hshieh
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Patent number: 8247258Abstract: A method for fabricating CMOS image sensor device includes providing a P-type semiconductor substrate. The semiconductor substrate includes a surface region. The method includes forming a first dielectric layer having a first thickness overlying a first region of the semiconductor substrate. The method includes providing an N type impurity region in a portion of the semiconductor substrate underneath the first dielectric layer to cause formation of a photodiode device region characterized by at least the N type impurity region and the P type substrate. A second dielectric layer having a second thickness is formed in a second region of the surface region. The second dielectric layer is formed within a portion of the first region within the first thickness of the first dielectric layer. The method includes forming a polysilicon gate layer overlying at least the second region to form a contact member coupled to the second region.Type: GrantFiled: October 27, 2008Date of Patent: August 21, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Jianping Yang, Hong Zhu, Jieguang Huo
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Patent number: 8241978Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.Type: GrantFiled: August 6, 2009Date of Patent: August 14, 2012Assignee: Anpec Electronics CorporationInventors: Wei-Chieh Lin, Li-Cheng Lin, Hsin-Yu Hsu, Ho-Tai Chen, Jen-Hao Yeh, Guo-Liang Yang, Chia-Hui Chen, Shih-Chieh Hung
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Method of forming a vertical diode and method of manufacturing a semiconductor device using the same
Patent number: 8241979Abstract: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.Type: GrantFiled: August 20, 2010Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jin Park, Kong-Soo Lee, Yong-Woo Hyung, Young-Sub You, Jae-Jong Han -
Patent number: 8236676Abstract: An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body.Type: GrantFiled: November 26, 2007Date of Patent: August 7, 2012Assignee: Infineon Technologies Austria AGInventors: Frank Pfirsch, Hans-Joachim Schulze, Franz-Josef Niedernostheide
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Publication number: 20120193701Abstract: A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.Type: ApplicationFiled: May 5, 2011Publication date: August 2, 2012Inventor: Wei-Chieh Lin
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Patent number: 8232159Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.Type: GrantFiled: February 22, 2012Date of Patent: July 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Ki Ho Yang
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Patent number: 8232160Abstract: A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor.Type: GrantFiled: February 24, 2012Date of Patent: July 31, 2012Assignee: Hynix Semiconductor Inc.Inventor: Nam Kyun Park
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Patent number: 8222678Abstract: A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other.Type: GrantFiled: August 17, 2009Date of Patent: July 17, 2012Assignee: Excelliance MOS CorporationInventor: Chu-Kuang Liu
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Publication number: 20120175699Abstract: A power semiconductor device having a self-aligned structure and super pinch-off regions is disclosed. The on-resistance is reduced by forming a short channel without having punch-through issue. The on-resistance is further reduced by forming an on-resistance reduction implanted drift region between adjacent shield electrodes, having doping concentration heavier than epitaxial layer without degrading breakdown voltage with a thick oxide on bottom and sidewalls of the shield electrode. Furthermore, the present invention enhance the switching speed comparing to the prior art.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: FORCE MOS TECHNOLOGY CO., LTD.Inventor: Fu-Yuan HSIEH
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Publication number: 20120175704Abstract: A monolithically-integrated dual surge protective device and its fabrication method are disclosed. The exemplary dual surge protective device includes a LDMOS device and a diode assembly which is consisted. of multiple diodes series-wound on back-to-back basis and whose one end is connected to drain electrode of the LDMOS device and the other-end is connected to gate electrode of the LDMOS device. The diode assembly can be fabricated directly in the gate electrode area of the LDMOS device after fabrication of the LDMOS device is completed. The protective device is equivalent to combination of diodes and LDMOS in respect to operating principles and structures, with the advantage of enhanced effect of surge prevention and cost reduction of surge device as it can be integrated into a chip.Type: ApplicationFiled: December 30, 2011Publication date: July 12, 2012Applicant: NORTH CHINA UNIVERSITY OF TECHNOLOGYInventor: Yanfeng Jiang
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Patent number: 8217453Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.Type: GrantFiled: August 7, 2009Date of Patent: July 10, 2012Assignee: Texas Instruments IncorporatedInventor: Sameer P. Pendharkar
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Publication number: 20120161248Abstract: A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within the substrate adjacent to the gate structure. A drain region is formed within the substrate adjacent to the gate structure. A first clamping region and second clamping region below the source region and drain region. A trench is formed through the source region. The trench allows the width of the source region to be reduced to 0.94 to 1.19 micrometers. A plug is formed through the trench. A source tie is formed through the trench over the plug. An interconnect structure is formed over the source region, drain region, and gate structure. The semiconductor device can be used in a power supply to provide a low voltage to electronic equipment such as a portable electronic device and data processing center.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Patrick M. Shea, Samuel J. Anderson
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Publication number: 20120161232Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.Type: ApplicationFiled: December 28, 2011Publication date: June 28, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Farzan Farbiz, Akram Salman
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Publication number: 20120161225Abstract: The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area.Type: ApplicationFiled: December 28, 2010Publication date: June 28, 2012Inventors: Tiesheng Li, Lei Zhang
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Publication number: 20120156840Abstract: A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor.Type: ApplicationFiled: February 24, 2012Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Nam Kyun PARK
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LAYOUT METHOD OF SEMICONDUCTOR DEVICE WITH JUNCTION DIODE FOR PREVENTING DAMAGE DUE TO PLASMA CHARGE
Publication number: 20120149160Abstract: A layout method of junction diodes for preventing damage caused by plasma charge includes forming an active layer to form a plurality of active regions in a unit layout pattern; forming a gate layer to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions to form a junction diode in at least one active region between the first and second conductive type active regions.Type: ApplicationFiled: February 2, 2012Publication date: June 14, 2012Inventors: Soo-Young Kim, Jong-Hak Won -
Patent number: 8187932Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.Type: GrantFiled: October 15, 2010Date of Patent: May 29, 2012Assignee: SanDisk 3D LLCInventors: Natalie Nguyen, Paul Wai Kie Poon, Steven J. Radigan, Michael Konevecki, Raghuveer S. Makala
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Publication number: 20120126317Abstract: The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates.Type: ApplicationFiled: November 18, 2010Publication date: May 24, 2012Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Daniel Ng, Anup Bhalla, Xiaobin Wang
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Patent number: 8168999Abstract: A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the IGBT cell region; a third semiconductor region on the second side in the diode cell region; a fourth semiconductor region on the first side surrounding the active element cell area; a fifth semiconductor region on the first side surrounding the fourth semiconductor region; and a sixth semiconductor region on the second side below the fourth semiconductor region. The second semiconductor region, the third semiconductor region and the sixth semiconductor region are electrically coupled with each other.Type: GrantFiled: March 31, 2009Date of Patent: May 1, 2012Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Kenji Kouno
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Patent number: 8169053Abstract: Provided are resistive random access memories (RRAMs) and methods of manufacturing the same. A RRAM includes a storage node including a variable resistance layer, a switching device connected to the storage node, and a protective layer covering an exposed part of the variable resistance layer. The protective layer includes at least one of aluminum oxide and titanium oxide. The variable resistance layer is a metal oxide layer.Type: GrantFiled: October 20, 2008Date of Patent: May 1, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-hwan Kim, Young-soo Park, Myung-jae Lee, Xianyu Wenxu, Seung-eon Ahn, Chang-bum Lee
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Patent number: 8168466Abstract: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.Type: GrantFiled: June 1, 2007Date of Patent: May 1, 2012Assignee: Semiconductor Components Industries, LLCInventors: Mohammed Tanvir Quddus, Shanghui L. Tu, Antonin Rozsypal, Zia Hossain
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Publication number: 20120098058Abstract: A semiconductor device and a method for forming the semiconductor device wherein the semiconductor comprises: a trench MOSFET, formed on a semiconductor initial layer, comprising a well region, wherein the semiconductor initial layer has a first conductivity type and wherein the well region has a second conductivity type; an integrated Schottky diode next to the trench MOSFET, comprising a anode metal layer contacted to the semiconductor initial layer; a trench isolation structure, coupled between the trench MOSFET and integrated Schottky diode, configured to resist part of lateral diffusion from the well region; wherein the well region comprises an overgrowth part which laterally diffuses under the trench isolation structure and extends out of it.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Inventors: Lei Zhang, Tiesheng Li
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Patent number: 8163612Abstract: Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric.Type: GrantFiled: December 17, 2009Date of Patent: April 24, 2012Assignee: International Business Machines CorporationInventors: Erik M Dahlstrom, Alvin J Joseph, Robert M Rassel, David C Sheridan
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Patent number: 8158475Abstract: A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.Type: GrantFiled: September 10, 2010Date of Patent: April 17, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chun-Lin Tsai, Chien-Chih Chou
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Publication number: 20120080769Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.Type: ApplicationFiled: October 1, 2010Publication date: April 5, 2012Inventors: Umesh Sharma, Harry Yue Gee, Der Min Liou, David D. Marreiro, Sudhama C. Shastri
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Patent number: 8143655Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.Type: GrantFiled: October 11, 2007Date of Patent: March 27, 2012Assignee: International Rectifier CorporationInventor: Davide Chiola
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Patent number: 8133765Abstract: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.Type: GrantFiled: November 16, 2010Date of Patent: March 13, 2012Assignee: Infineon Technologies AGInventors: Uwe Hodel, Wolfgang Soldner
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Layout method of semiconductor device with junction diode for preventing damage due to plasma charge
Patent number: 8133778Abstract: Provided is a layout method of junction diodes for preventing damage caused by plasma charge. The layout method includes operations of forming an active layer so as to form a plurality of active regions in a unit layout pattern; forming a gate layer so as to form a plurality of gate regions on the active regions; forming a first conductive type doping region in at least one of the plurality of active regions within a well layer where a second conductive type well region is formed so as to form a first conductive type active region; forming a second conductive type doping region in at least one of the plurality of active regions outside of the second conductive type well region so as to form a second conductive type active region; and forming a second conductive type doping region connected with the gate regions so as to form a junction diode in at least one active region between the first and second conductive type active regions.Type: GrantFiled: March 12, 2008Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Young Kim, Jong-Hak Won -
Patent number: 8129726Abstract: A light-emitting diode (LED) package having electrostatic discharge (ESD) protection function and a method of fabricating the same adopt a composite substrate to prepare an embedded diode and an LED, and use an insulating layer in the composite substrate to isolate some individual embedded diodes, such that the LED device has the ESD protection.Type: GrantFiled: July 29, 2008Date of Patent: March 6, 2012Assignee: Industrial Technology Research InstituteInventors: Chih-Tsung Shih, Chen-Peng Hsu, Kuan-Chieh Tu, Hung-Lieh Hu, Bing-Ru Chen, Shih-Tsai Huang, Hsin-Yun Tsai
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Patent number: 8129746Abstract: A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor.Type: GrantFiled: December 18, 2009Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventor: Nam Kyun Park
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Patent number: 8129814Abstract: An integrated circuit includes a Schottky diode having a cathode defined by an n-type semiconductor region, an anode defined by a cobalt silicide region, and a p-type region laterally annularly encircling the cobalt silicide region. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation. An n+-type contact region is laterally separated by the p-type region from the first silicide region and a second cobalt silicide region is formed in the n-type contact region. The silicided regions are defined by openings in a silicon blocking dielectric layer. Dielectric material is left over the p-type region. The p-type region may be formed simultaneously with source/drain regions of a PMOS transistor.Type: GrantFiled: April 12, 2011Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Sameer Prakash Pendharkar, Eugen Pompiliu Mindricelu
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Patent number: 8129237Abstract: A vertical light-emitting diode (VLED) structure fabricated with a SixNy layer responsible for providing increased light extraction out of a roughened n-doped surface of the VLED are provided. Such VLED structures fabricated with a SixNy layer may have increased luminous efficiency when compared to conventional VLED structures fabricated without a SixNy layer. Methods for creating such VLED structures are also provided.Type: GrantFiled: May 15, 2008Date of Patent: March 6, 2012Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventor: Chuong Anh Tran
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Publication number: 20120049270Abstract: A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.Type: ApplicationFiled: August 30, 2010Publication date: March 1, 2012Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
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Publication number: 20120049287Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: ApplicationFiled: July 26, 2011Publication date: March 1, 2012Applicant: PFC DEVICE CORPORATIONInventors: Mei-Ling Chen, Hung-Hsin Kuo, Kou-Liang Chao