Having Diverse Electrical Device Patents (Class 438/23)
  • Patent number: 7259031
    Abstract: Photonic interconnect reconfigurably couples integrated circuits such as microprocessor, memory or other logic components. Detector, modulator, broad-band coupler and waveguide elements provide transmit and receive capability on CMOS substrate. Computer-implemented design software and reusable component library automate photonic and circuit design and simulation for manufacturability.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: August 21, 2007
    Assignee: Luxtera, Inc.
    Inventors: Alexander G. Dickinson, Lawrence C. Gunn, III, Philip M. Neches, Andrew Shane Huang
  • Patent number: 7248131
    Abstract: Monolithic devices that include an acoustic resonator vertically integrated with electronic circuitry are described. In one aspect, a monolithic integrated device includes a substrate, electronic circuitry supported by the substrate, an acoustic isolator over the electronic circuitry, and an acoustic resonator on the acoustic isolator. A method of fabricating the monolithic device also is described.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: July 24, 2007
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: R. Shane Fazzio, Thomas E. Dungan
  • Patent number: 7195939
    Abstract: Semiconductor devices in an optoelectronic integrated circuit are electrically isolated from each other by using planar lateral oxidation to oxidize a buried semiconductor layer vertically separating the semiconductor devices.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: March 27, 2007
    Assignee: Xerox Corporation
    Inventors: Christopher L. Chua, Philip D. Floyd, Thomas L. Paoli, Decai Sun
  • Patent number: 7172969
    Abstract: A method and system is described for preparing a film stack, and forming a feature in the film stack using a plurality of dry etching processes. The feature formed in the film stack can include a gate structure having a critical dimension of approximately 25 nm or less. This critical dimension can be formed in the polysilicon layer using four mask layers.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 6, 2007
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: Annie Xia, Hiromasa Mochiki, Arpan P Mahorowala
  • Patent number: 7125733
    Abstract: A method for producing an emission module having at least two vertically emitting lasers in which an optically active laser layer is arranged on a substrate and at least one upper covering layer is arranged on said laser layer. In a first etching step, upper mesa regions are formed by etching the upper covering layer, wherein the etching depth of the first etching step is chosen such that the first etching step is ended above the optically active laser layer, and the first etching step is carried out such that the resulting distance between adjacent upper mesa regions is so small that the radiation generated by the finished lasers can be coupled directly into a single optical waveguide. In a second etching step, the optically active layer is severed to form lower mesa regions, the second etching step being a wet-chemical or dry-chemical etching step with a predominantly chemical etching component.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: October 24, 2006
    Assignee: Infineon Technologies AG
    Inventor: Gunther Steinle
  • Patent number: 7067336
    Abstract: An electron-emitting device having favorable electron emitting characteristic stable for a long time, which is manufactured by a method comprising the steps of disposing an electrically conductive member having a second gap on a substrate, and applying a voltage to the electrically conductive member while irradiating at least the second gap with an electron beam from electron emitting means disposed apart from the electrically conductive member in an atmosphere comprising a carbon compound.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: June 27, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Kyogaku, Hironobu Mizuno, Takeo Tsukamoto, Hiroyuki Hashimoto, Koki Nukanobu
  • Patent number: 7064353
    Abstract: A relatively small ESD protection diode is formed on the same chip as a light emitting diode. In one embodiment, the ESD diode is a mesa-type diode isolated from the light emitting diode by a trench. To reduce the series resistance of the ESD diode, the PN junction and metal contact to the semiconductor material is made long and expands virtually the width of the chip. Various configurations of the PN junction and the N and P metal contacts for the ESD diode are described for increasing the breakdown voltage and for improved testing.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: June 20, 2006
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventor: Jerome C. Bhat
  • Patent number: 7045400
    Abstract: The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 16, 2006
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 7026182
    Abstract: To provide a semiconductor device, such as semiconductor laser, having no need of complicated process, ensuring a high yield and mass-productivity necessary for cost reduction, and exhibiting excellent initial characteristics and reliability, nitride semiconductor layers containing a plurality of group III elements are formed on a base body surface having recess (opening) such that the nitride semiconductor layer varies in at least one of composition ratio of the group III elements, band gap energy, refractive index, electrical conductivity and specific resistance within the layer in response to the recess of the base body. In addition, by heating the structure in an atmosphere containing hydrogen and using a layer containing Al as an etching stop layer, controllability and production yield can be improved without influences from fluctuation in etching depth, or the like. Further, etching and re-growth can be conducted consecutively to provide an inexpensive process.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: April 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Shin-Ya Nunoue
  • Patent number: 7023022
    Abstract: A light-emitting package includes a substantially transparent substrate having a first surface and a second surface including a lens. The package also includes a light-emitting diode (LED) adapted to emit light having a predetermined wavelength, the LED being secured over the first surface of the substantially transparent substrate. The second surface of the substrate defines a principal light emitting surface of the package. The lens at the second surface has a grating pattern that matches the predetermined wavelength of the light emitted from the LED for controlling the emission geometry of the light emitted by the package. The grating pattern has a radial configuration including a series of circles that are concentric.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: April 4, 2006
    Assignee: Emcore Corporation
    Inventors: Ivan Eliashevich, Robert F. Karlicek, Hari Venugopalan
  • Patent number: 7016655
    Abstract: A system that provides packaging for a surface acoustic wave filter in such a way that the surface acoustic wave filter is capable of integration with a number of additional electronic devices on an integrated substrate. The surface acoustic wave filter is mounted in a “flip chip” configuration that enables the surface of the surface acoustic wave filter to be protected from a molding compound during and after the encapsulation of the surface acoustic wave filter and other circuitry contained on the integrated substrate. The manner in which the surface acoustic wave filter is packaged provides a great reduction in cost and occupied real estate on the integrated substrate, in that, the surface acoustic wave filter is mounted in such as way as not to require conventionally used ceramic packaging that encases the surface acoustic wave filter. An air gap is preserved between the surface acoustic wave filter side of the surface acoustic wave filter and the integrated substrate on which it is mounted.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: March 21, 2006
    Assignee: Skyworks Solutions, Inc.
    Inventor: Nooshin D. Vakilian
  • Patent number: 6967117
    Abstract: The present invention discloses a method for producing a high brightness LED (light emitting diode). The method primarily comprises steps of: a) providing a temporary substrate for epitaxy; b) forming LED epitaxial layers on said temporary substrate, wherein said LED epitaxial layers with pn junction; c) providing a permanent substrate; d) forming a layered structure between said permanent substrate and said LED epitaxial layers, wherein said layered structure has properties of reflection, adhesion, diffusion barrier and buffer; and e) forming a first electrode and a second electrode on proper position to supply enough energy for said LED epitaxial layers. The LED manufactured in accordance with the present invention can exhibit high brightness and excellent mechanical strength during manufacturing.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: November 22, 2005
    Assignee: National Chung-Hsing University
    Inventors: Ray-Hua Horng, Tung-Hsing Wu, Shao-Hua Huang
  • Patent number: 6927424
    Abstract: A light emitting diode is composed of a generally T-shaped body section (36) and a resin forming section (37) projected on a front surface of the body section (36). The body section (36) has an upright portion (32) inserted into a hole (51) provided in a motherboard (50) and base portions (31a and 31b) which extend from the upright portion and which are mounted on a peripheral edge of the hole (51). The resin forming section (37) includes a non-translucent frame (40) extending from a front surface of the upright portion (32) and an extension part (41) further projecting forwardly larger than the frame. The extension part (41) has a mounted portion (42) mounted on the peripheral edge of the hole (51) of the motherboard (50). Mounted in the concave portion (44) provided in the frame (40) is a light emitting diode element (34), which is sealed by a sealing body (45) of a translucent resin.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: August 9, 2005
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Hidemoto Uekusa
  • Patent number: 6916673
    Abstract: The invention relates to a method for producing an optical transmitting and receiving device (1, 1a) comprising a light emitting transmission element (3, 3a) and a receiving element (4, 4a) which converts this light into an electrical magnitude. The transmission and receiving elements are inserted into a silicon substrate. The optical transmitting and receiving device (1) is preferably inserted in a monolithic manner into a common substrate, comprising a sequence of superimposed layers for the light emitting transmission element (3) and the light receiving element (4). An electrically insulating intermediate layer (9, 9a) is incorporated between the transmission and receiving element.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: July 12, 2005
    Assignee: Micronas GmbH
    Inventors: Ulrich Sieben, Günter Igel
  • Patent number: 6895667
    Abstract: Methods for patterning a metal over a substrate and devices formed using the methods are disclosed. A patterned die having at least one raised portion and having a metal layer over the die is pressed onto a thin metal film over a substrate, such that the metal layer over the raised portion of the patterned die contacts portions of the thin metal film. Pressure is then applied such that the metal layer and the thin metal film cold-weld to one another. The patterned die is removed, such that the portions of the metal layer cold-welded to the thin metal film break away from the die and remain cold-welded to the thin metal film over the substrate, in substantially the same pattern as the patterned die.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: May 24, 2005
    Assignee: The Trustees of Princeton University
    Inventors: Stephen R. Forrest, Changsoon Kim
  • Patent number: 6890780
    Abstract: The present invention provides a method and associated structure for forming an electrostatically-doped carbon nanotube device. The method includes providing a carbon nanotube having a first end and a second end. The method also includes disposing a first metal contact directly adjacent to the first end of the carbon nanotube, wherein the first metal contact is electrically coupled to the first end of the carbon nanotube, and disposing a second metal contact directly adjacent to the second end of the carbon nanotube, wherein the second metal contact is electrically coupled to the second end of the carbon nanotube.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: May 10, 2005
    Assignee: General Electric Company
    Inventor: Ji Ung Lee
  • Patent number: 6865074
    Abstract: The invention relates to a method of producing an electronic unit of a radio system and an electronic unit of a radio system. The electronic unit comprises a mechanical part, a circuit board attached to the mechanical part and an electronic component connected to the circuit board. The method comprises mounting (1702) the electronic component in a cavity provided for the electronic component in the mechanical part; placing (1704) the circuit board on the electronic component and the mechanical part; connecting (1706) the electronic component and the circuit board together using electric coupling members for aligning them with respect to each other and for forming an electrical connection between electric connecting means of the circuit board and electric connecting means of the electronic component; and attaching (1708) the electronic component and the circuit board to each other and to the mechanical part automatically so that the electronic component will be in contact with the mechanical part.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: March 8, 2005
    Assignee: Nokia Corporation
    Inventors: Pasi Lehtonen, Kimmo Huhtala, Marko Kuusikko
  • Patent number: 6852627
    Abstract: Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: February 8, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Warren M. Farnworth
  • Patent number: 6831301
    Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tim Murphy, Lee Gotcher
  • Patent number: 6821793
    Abstract: The disclosure is directed toward an optical excitation/detection device that includes an arrayed plurality of photodetectors and discrete photoemitters, as well as a method for making such a device. A CMOS fabricated photodetector array includes an arrayed plurality of photoreceptor areas and photoemitter areas, wherein each photoreceptor area includes a CMOS integrated photoreceptor and each photoemitter area includes at least two buried electric contact pads. The CMOS array is selectively etched back at the locations of the photoemitter areas for regions to reveal the buried contact pads. A plurality of discrete semiconductor photoemitter devices (such as, for example, light emitting diodes) are inserted into, and mechanically retained within, the regions of the CMOS fabricated photodetector array.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: November 23, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Edward Verdonk, Richard J. Pittaro, Shahida Rana, David Andrew King, Frederick A. Stawitcke, Richard D. Pering
  • Patent number: 6821804
    Abstract: This invention describes new LEDs having light extraction structures on or within the LED to increase its efficiency. The new light extraction structures provide surfaces for reflecting, refracting or scattering light into directions that are more favorable for the light to escape into the package. The structures can be arrays of light extraction elements or disperser layers. The light extraction elements can have many different shapes and are placed in many locations to increase the efficiency of the LED over conventional LEDs. The disperser layers provide scattering centers for light and can be placed in many locations as well. The new LEDs with arrays of light extraction elements are fabricated with standard processing techniques making them highly manufacturable at costs similar to standard LEDs. The new LEDs with disperser layers are manufactured using new methods and are also highly manufacturable.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: November 23, 2004
    Assignee: Cree, Inc.
    Inventors: Brian Thibeault, Michael Mack, Steven DenBaars
  • Patent number: 6812058
    Abstract: Data is encoded in a solid state image sensor that includes a sensor pixel array by varying the color processing applied to at least some of the border pixels of the sensor pixel array. Data may be encoded in the color processing by varying the pattern of a color filter mosaic and by varying a pattern of a microlens array in accordance with a predetermined scheme. This scheme includes omission of color filter material and omission of the microlens array from selected pixels. The data, typically encoded in a binary format, is read by illuminating the sensor pixel array and by processing the output signals from the border pixels. The encoded data may include color process codes, mask revision codes and product codes.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics Ltd.
    Inventor: Carl Dennis
  • Publication number: 20040206965
    Abstract: A light emitting device may include a light emitting layer such as an organic semiconductor material, one or more feedback structures, and a coupling structure. The one or more feedback structures may cause light emitted by the light emitting layer to be fed back through it along an axis in the plane of the device, thereby promoting the stimulated emission of light in the light emitting layer. The coupling structure couples some fraction of the feedback light out of the device. The coupled light may be emitted along an axis substantially normal to the plane of the device or at predetermined angles. The coupling and feedback structures may have a corrugated structure, a continuous variation of refractive index along an axis in the device plane, a period refractive index, or any combination thereof. The coupling and feedback structures may be separate, share common portion or combined together.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventor: Allan Kenneth Evans
  • Patent number: 6773943
    Abstract: A display unit having a sufficient luminance and a method of fabricating the display unit are provided. The display unit includes micro-sized semiconductor light emitting devices fixedly arrayed on a plane of a base body of the display unit at intervals. Micro-sized GaN based semiconductor light emitting devices formed by selective growth are each buried in a first insulating layer made from an epoxy resin except an upper end portion and a lower end surface thereof, and electrodes of each of the light emitting devices are extracted. These light emitting devices are fixedly arrayed on the upper plane of the base body at intervals. A second insulating layer made from an epoxy resin is formed on the plane of the base body so as to cover the semiconductor light emitting devices each of which has been buried in the first insulating layer.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: August 10, 2004
    Assignee: Sony Corporation
    Inventors: Toyoharu Oohata, Hideharu Nakajima, Yoshiyuki Yanagisawa, Toshiaki Iwafuchi
  • Patent number: 6756290
    Abstract: A method for making a semiconductor device having a pattern of highly doped regions located some distance apart in a semiconductor substrate and regions of low doping located between the highly doped regions. A diffusion barrier material is applied to the semiconductor substrate at the location of the regions of low doping by imprinting with the barrier material in the pattern of the regions of low doping. The doping material is applied after or before imprinting with barrier material so that the highly doped regions are formed essentially between the barrier material in the substrate.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 29, 2004
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventor: Jan Hendrik Bultman
  • Patent number: 6730934
    Abstract: This invention relates an optoelectronic material comprising a uniform medium with a controllable electric characteristic; and semiconductor ultrafine particles dispersed in the medium and having a mean particle size of 100 nm or less, and an application device using the same.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 4, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuka Yamada, Takehito Yoshida, Shigeru Takeyama, Yuji Matsuda, Katsuhiko Mutoh
  • Patent number: 6727110
    Abstract: A method and apparatus for fabricating silica-based waveguide devices on a substrate using a low temperature PECVD process using a TEOS source material for depositing waveguide layers containing silica, the apparatus being arranged, in use, in a manner such that a liquid source material containing silicon is used during the PECVD.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: April 27, 2004
    Assignee: Redfern Integrated Optics PTY LTD
    Inventor: Michael Bazylenko
  • Patent number: 6706544
    Abstract: The light emitting device according to the present invention is characterized in that a gate electrode comprising plurality of conductive films is formed, and concentration of impurity regions in an active layer are adjusted with making use of selectivity of the conductive films in etching and using them as masks. The present invention reduces the number of photolithography steps in relation to manufacturing the TFT for improving yield of the light emitting device and shortening manufacturing term thereof, by which a light emitting device and an electronic appliance are inexpensively provided.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: March 16, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Fukunaga, Jun Koyama, Kazutaka Inukai
  • Patent number: 6627468
    Abstract: The present invention provides a method for manufacturing an optical element to be used for an optical system and an optical instrument using the optical system, and a method for manufacturing a device using the optical instrument, wherein the optical element is manufactured by the steps including the steps for processing a high purity silica glass by lithography, and the hydrogen molecule content is adjusted after manufacturing the optical element.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: September 30, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keiko Chiba
  • Patent number: 6555440
    Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: April 29, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Frank Sigming Geefay
  • Publication number: 20030049876
    Abstract: A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment.
    Type: Application
    Filed: February 27, 2002
    Publication date: March 13, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Masahito Mori, Naoshi Itabashi, Masaru Izawa
  • Patent number: 6521471
    Abstract: The invention concerns a semiconductor opto-electronic component comprising at least two optically active structures (20, 30), at least one of which consists of a detector (30), characterized in that the detector or detectors (30) comprise a first active portion (33) able to detect a signal at a given wavelength and a second inactive portion (34) only slightly sensitive to the signal to be detected and exposed to the non-guided stray light conveyed in the component.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: February 18, 2003
    Assignee: ALCATEL
    Inventors: Franck Mallecot, Christine Chaumont, Arnaud Leroy, Antonina Plais
  • Publication number: 20030003618
    Abstract: A method for manufacturing an electrostatic actuator comprises a vibrating plate, an electrode plate facing the vibrating plate, and a vibrating chamber formed between the electrode plate and the vibrating plate, wherein the vibrating plate is displaced by electrostatic force, by applying voltage between the vibrating plate and the electrode plate, the method comprises: a process for forming a pressure compensating chamber communicating with the vibrating chamber; a process for forming a displacement plate at a portion of the pressure compensating chamber, displaceable according to external atmospheric pressure, into a warped form curved so as to protrude in a direction away from the facing inner wall of the pressure compensating chamber; and a process for shutting off and sealing the pressure compensating chamber from the external atmosphere, along with the vibrating chamber.
    Type: Application
    Filed: August 8, 2002
    Publication date: January 2, 2003
    Inventors: Masahiro Fujii, Hiroyuki Maruyama, Kazuhiko Sato, Koji Kitahara, Tomohiro Makigaki, Shigeo Nojima, Taro Takekoshi
  • Publication number: 20020137246
    Abstract: A circuit-incorporating light receiving device includes an integrated circuit and a photodiode. The integrated circuit and the photodiode are provided on a single semiconductor substrate. The integrated circuit includes a transistor having a polycrystalline silicon as an emitter diffusion source and an electrode. Elements included in the integrated circuit are isolated from each other using local oxidization.
    Type: Application
    Filed: May 23, 2002
    Publication date: September 26, 2002
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Takahiro Takimoto, Naoki Fukunaga, Isamu Ohkubo, Toshimitsu Kasamatsu, Mutsumi Oka, Masaru Kubo
  • Publication number: 20020127753
    Abstract: A method of manufacturing a CMOS thin film transistor (TFT) active matrix organic EL device using six mask processes. The manufacturing methods is simpler than previous manufacturing methods, resulting in high manufacturing yield and low production cost.
    Type: Application
    Filed: January 7, 2002
    Publication date: September 12, 2002
    Inventor: Keun Ho Jang
  • Publication number: 20020072138
    Abstract: A method for making optoelectronic devices with interdigitated arrays of photonic devices is disclosed wherein an array of first type photonic devices and sacrificial device(s) is hybridized to a driver circuitry substrate, the sacrificial devices are removed, and an array of second type photonic devices is hybridized into the spaces left by removal of the sacrificial devices.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 13, 2002
    Inventors: John A. Trezza, Gregory K. Dudoff
  • Publication number: 20020045285
    Abstract: As a method of fabricating aspherical microstructures, a protruding microstructure is formed on a substrate, an aspherical-profile forming layer is formed on the substrate and the protruding microstructure, and the aspherical-profile forming layer is hardened. An aspherical profile is formed on the protruding microstructure due to a surface tension of the aspherical-profile forming layer in the step of forming the aspherical-profile forming layer, and the aspherical profile is maintained through the step of hardening the aspherical-profile forming layer.
    Type: Application
    Filed: October 4, 2001
    Publication date: April 18, 2002
    Inventors: Takashi Ushijima, Takayuki Yagi
  • Publication number: 20020042155
    Abstract: In an optical semiconductor device including a semiconductor substrate, an active layer formed on the semiconductor substrate, a pnpn-type current blocking layer formed on a side of the active layer, and a carrier recombination layer on the semiconductor substrate on the side of the active layer, a structure of the active layer is different from a structure of the carrier recomibination layer.
    Type: Application
    Filed: November 1, 2001
    Publication date: April 11, 2002
    Inventor: Yasutaka Sakata
  • Patent number: 6352872
    Abstract: A silicon-on-insulator (SOI) device having a double gate, comprising: a supporting substrate; a first insulating layer formed over the supporting substrate; a first silicon layer formed over the first insulating layer, the first silicon layer including a first impurity region of a first conductivity disposed in a central portion thereof and intrinsic regions disposed at the both sides of the first impurity region; a second insulating layer formed over the first silicon layer; a second silicon layer formed over the second insulating layer, the second silicon layer including a second impurity region of a second conductivity disposed in a central portion thereof and third impurity regions of first conductivities disposed at the both sides of the second impurity region; a third insulating layer formed over the second impurity region; and a polysilicon layer doped with impurity ions of first conductivities, formed over the third insulating layer.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: March 5, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Hyung Ki Kim, Jong Wook Lee
  • Patent number: 6344670
    Abstract: The solid-state image sensor comprises a semiconductor substrate, a plurality of photoelectric conversion sections formed within respective isolated active regions on the semiconductor substrate, an image area wherein unit cells comprising the plurality of photoelectric conversion sections and a signal scanning circuit are arranged in a two-dimensional array form, and signal lines for reading signals from the respective unit cells within the image pick-up area, wherein the respective photoelectric conversion sections being formed by at least two ion implantations.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: February 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Yamaguchi, Hisanori Ihara, Hirofumi Yamashita, Hidetoshi Nozaki, Ikuko Inoue
  • Publication number: 20020001864
    Abstract: To provide a semiconductor device, such as semiconductor laser, having no need of complicated process, ensuring a high yield and mass-productivity necessary for cost reduction, and exhibiting excellent initial characteristics and reliability, nitride semiconductor layers containing a plurality of group III elements are formed on a base body surface having recess (opening) such that the nitride semiconductor layer varies in at least one of composition ratio of the group III elements, band gap energy, refractive index, electrical conductivity and specific resistance within the layer in response to the recess of the base body. In addition, by heating the structure in an atmosphere containing hydrogen and using a layer containing Al as an etching stop layer, controllability and production yield can be improved without influences from fluctuation in etching depth, or the like. Further, etching and re-growth can be conducted consecutively to provide an inexpensive process.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Ishikawa, Shin-Ya Nunoue
  • Patent number: 6316278
    Abstract: Methods and apparatus for fabricating a multiple display modular assembly. In one example of a method, a first flexible layer is coupled to a substrate, a second flexible layer is coupled to the first flexible layer, and a third flexible layer is coupled to the second flexible layer. Each of the flexible layers may be generated from a separate web-line process. In one example, one flexible layer may have a display plane with a driver backplane, a second flexible layer may have a fine interconnect, and a third flexible layer may have gross interconnect. The multiple flexible layer modular assembly may apply to either flexible or rigid displays.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: November 13, 2001
    Assignee: Alien Technology Corporation
    Inventors: Jeffrey Jay Jacobsen, Glenn Wilhelm Gengel, Gordon S. W. Craig
  • Patent number: 6294398
    Abstract: The present invention relates to patterning methods for organic devices, and more particularly to patterning methods using a die. The method includes depositing a first layer of organic materials over a substrate; depositing a second layer of an electrode material over the first layer of organic materials; pressing a patterned die having a raised portion onto the second layer; and removing the patterned die. Preferably the patterned die is coated with a metal. Optionally the method includes depositing additional layers over the substrate prior to pressing the patterned die.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: September 25, 2001
    Assignee: The Trustees of Princeton University
    Inventors: Changsoon Kim, Paul E. Burrows, Stephen R. Forrest
  • Patent number: 6261855
    Abstract: A mesa structure including an active layer is formed by selective growth on a semiconductor substrate and a layer containing aluminum is grown on the topmost part of the mesa structure. This aluminum-containing layer is then oxidized and used as a mask to form current blocking layers.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: July 17, 2001
    Assignee: NEC Corporation
    Inventor: Naofumi Suzuki
  • Patent number: 6238085
    Abstract: A sensor having an active sensing material exposed to the substance to be detected and an active reference material that is shielded from the substance to be detected. Thermocouples having a set of junctions proximate to the active sensing material and another set of junctions to the active reference material for measuring the temperatures at the respective materials. The junctions are connected differentially in that a difference of the two temperatures is measured. A heater is proximate and common to the two materials. Heat pulses may be applied to the materials via the heater and the temperatures are measured. If ambient factors or substances affect the active sensing material, its thermal response will be different than that of the active reference material, and a differential pulse-like indication of temperature will be detected.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: May 29, 2001
    Assignee: Honeywell International Inc.
    Inventors: Robert E. Higashi, Barrett E. Cole
  • Patent number: 6221683
    Abstract: The invention relates to a method for producing a light-emitting component. A sequence of layers including at least one active layer is formed on the front face of a basic substrate consisting of semiconductor material. Subsequently, the basic substrate is at least partially removed and the sequence of layers is connected to an external substrate. The basic substrate is removed by wet-chemical etching in an etching agent that acts selectively on the material of the basic substrate. A first metallic contact layer is then applied to an end surface of the sequence of layers, and a second metallic contact layer is applied to an end surface of the external substrate. The sequence of layers is connected to the external substrate by connecting the first metallic contact layer to the second metallic contact layer using heat, by means of eutectic bonding.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: April 24, 2001
    Assignee: Osram Opto Semiconductor GmbH & Co. OHG
    Inventors: Ernst Nirschl, Olaf Schönfeld
  • Patent number: 6221684
    Abstract: An n-cap layer is formed on a top surface of p-type clad layers, the p-type clad layer is a top layer of a stacked structure having a pn-junction for emitting carriers into light-emitting region of a GaN based light-emitting device, thus increasing the activation ratio of acceptor impurities in the p-type clad layers. The n-cap layer is used also as a current blocking layer, thereby constructing a current-blocked structure. The n-cap layer should preferably be made of InuAlvGa1−u−vN (0<u, v<1) deposited as thick as 1.0 micron or more. The present invention will easily provide a high luminous efficiency GaN based semiconductor light-emitting device without using any complicated processes such as electron-beam irradiation or thermal annealing.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Masayuki Ishikawa
  • Patent number: 6159760
    Abstract: A method of fabricating oxide-apertured vertical cavity surface emitting lasers involving the steps of: i) defining, during the fabrication of one or more VCSELs on an electronic chip, a number of mesa structures of different sizes; ii) selectively oxidizing the chip and mesa structures to produce an oxide-aperture for each structure; iii) inspecting the chip to determine which one of the mesas is desired or optimal; iv) choosing an appropriate metalization mask that serves to metalize and electrically connect only that desired mesa structure; and v) depositing, a dielectric top mirror on that electrically connected mesa. Advantageously, the method may be practiced using a variety of fabrication techniques and apparatus that are compatible with conventional devices. A distinguishing characteristic of our inventive method, is that only a desired or optimal mesa is completed while the remaining mesas on a particular chip remain unprocessed.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: December 12, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Keith Wayne Goossen, Martin C. Nuss
  • Patent number: 6101204
    Abstract: An integrated laser/modulator ("ILM") operating with reduced chirping is formed on a single semiconductor substrate. A reduction in chirping and any resultant wavelength dispersion is realized by precisely controlling the length of a window region incorporated in the ILM in order to isolate the ILM's active regions from any residual reflections.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: August 8, 2000
    Inventor: Wilbur Dexter Johnston, Jr.
  • Patent number: 6087194
    Abstract: Composite units of an optical semiconductor device and a supporting substrate are disclosed, in which the rear surface of the optical semiconductor device is provided with one or more electrode patterns and the top surface of the supporting substrate is provided with one or more electrode patterns. The optical semiconductor device and the supporting substrate are fixed to each other by once melting and solidifying one or more solder bumps which intervene between the one or more electrode patterns provided on the rear surface of the optical semiconductor device and the one or more electrode patterns provided on the top surface of the supporting substrate. A good grade of accuracy in the mutual geometric position of the optical semiconductor device and the supporting substrate is obtained in a horizontal direction due to a phenomenon called "the self alignment results" in this specification, in which a molten metal is inclined to become a ball based on surface tension.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: July 11, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hisao Matsukura, Yasuhiko Kudou, Hajime Hotta, Akio Hirakawa, Masaki Sugawara, Jiro Utsunomiya, Kiyoshi Kurosawa