Having Diverse Electrical Device Patents (Class 438/23)
  • Patent number: 6087194
    Abstract: Composite units of an optical semiconductor device and a supporting substrate are disclosed, in which the rear surface of the optical semiconductor device is provided with one or more electrode patterns and the top surface of the supporting substrate is provided with one or more electrode patterns. The optical semiconductor device and the supporting substrate are fixed to each other by once melting and solidifying one or more solder bumps which intervene between the one or more electrode patterns provided on the rear surface of the optical semiconductor device and the one or more electrode patterns provided on the top surface of the supporting substrate. A good grade of accuracy in the mutual geometric position of the optical semiconductor device and the supporting substrate is obtained in a horizontal direction due to a phenomenon called "the self alignment results" in this specification, in which a molten metal is inclined to become a ball based on surface tension.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: July 11, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hisao Matsukura, Yasuhiko Kudou, Hajime Hotta, Akio Hirakawa, Masaki Sugawara, Jiro Utsunomiya, Kiyoshi Kurosawa
  • Patent number: 6074887
    Abstract: The present invention is directed to fabricating a MOSFET-controlled FEA, in which the emitter array and the cathode electrode are separated and connected to each other by a MOSFET, the cathode electrode and the n-well beneath the emitter array thereby being used as a source and a drain of the MOSFET.
    Type: Grant
    Filed: September 27, 1997
    Date of Patent: June 13, 2000
    Assignees: Korean Information & Communication Co., Ltd., Jong Duk Lee
    Inventors: Jong Duk Lee, Donghwan Kim
  • Patent number: 6060333
    Abstract: A method of fabricating a liquid crystal display device including a field effect transistor includes forming a gate electrode on an electrically insulating substrate, the gate electrode being located in a transistor region of the substrate; forming an electrically insulating film on the substrate and covering the gate electrode; forming source and drain electrodes on the electrically insulating film on opposite sides of the gate electrode in the transistor region; forming a display electrode on the electrically insulating substrate in a display region of the substrate, adjacent the transistor region, the drain electrode being electrically connected to the display electrode; and forming, in the transistor region, a semiconductor film of a .pi.-conjugated polymer on the source and drain electrodes and on the electrically insulating film between the source and drain electrodes in the transistor region; arranging a transparent plate, including a transparent electrode, opposite and spaced from the .pi.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: May 9, 2000
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Sumitomo Chemical Company, Ltd.
    Inventors: Toshihiko Tanaka, Syuji Doi, Hiroshi Koezuka, Akira Tsumura, Hiroyuki Fuchigami
  • Patent number: 6054335
    Abstract: A III-V compound light emitter is integrated with Si-based actuators. The Proposed devices take advantage of the superior optical properties of III-V compounds and the superior mechanical properties of Si, as well as mature fabrication technologies of Si-Micro-Electro-Mechanical Systems (MEMS). The emitter can be a light emitting diode (LED), a vertical cavity surface emitting laser (VCSEL) or an edge emitting laser. Electro or magnetic based actuation from Si-based actuators provides linear or angular movement of the light emitter.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: April 25, 2000
    Assignee: Xerox Corporation
    Inventors: Decai Sun, Ross D. Bringans, Christopher L. Chua, Philip D. Floyd, Eric Peeters, Joel A. Kubby, Alex T. Tran
  • Patent number: 6037188
    Abstract: The present invention provides a photosensitive semiconductor device comprising a sealing body composed of a resin material for sealing photosensitive semiconductor elemental devices, a inside of the sealing body having a light-transmissive property, a surface of the sealing body composed of the resin material containing carbon.Owing to the above-described construction, the present invention can provide a photosensitive semiconductor device which eliminates the need for a mold resin forming process for forming only a lightproof film and is capable of simplifying a manufacturing process thereof and being rendered compact in size.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: March 14, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroyasu Torazawa
  • Patent number: 6033232
    Abstract: A method of fabricating a photodiode and at least one MOS device within a first active region and a second active region, respectively, of a substrate is disclosed. First, a gate structure is formed on the substrate within the second active region, and lightly-doped regions are formed by introducing first dopants into the substrate through the gate structure as masking. Then, a diffusion region is formed in the substrate within the first active region by ion implantation. Then, an insulating layer is formed to overlie the first and second active region, a portion of which within the second active region is thereafter patterned to sidewall spacers on the sidewalls of the gate structure. Subsequently, heavily-doped regions are formed by introducing second dopants throughout the second active region into the substrate by the gate structure and sidewall spacers as masking. In addition, the insulating layer can be thinned before the step of patterning the insulating layer to form the sidewall spacers is performed.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: March 7, 2000
    Assignee: Powerchip Semiconductor Corp.
    Inventors: James H. C. Lin, Chih-Wei Hsiung
  • Patent number: 6017811
    Abstract: A method for manufacturing a semiconductor structure having improved light mitting characteristics includes the step of exposing a semiconductor substrate, such as a silicon wafer, to an unbiased etching solution comprised of an acid, water, and an oxidizing agent to form a porous region having interstitial spaces in the semiconductor structure. Next, an electrically conductive contact structure is formed in the interstitial spaces and on the semiconductor structure. The large surface area at the interface junction between the electrical contact layer and the porous region is believed to enhance the intensity of light emitted by the porous region by allowing increased electrical current flow across the interface junction.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: January 25, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael J. Winton, Stephen D. Russell
  • Patent number: 6013538
    Abstract: A multiple layer patterning system with an undercut allows the deposition of a material onto a substrate from a direction substantially perpendicular to the substrate, followed by the angular deposition of a protective cap. Because of the angular deposition, the protective cap extends into the undercut and completely covers and surrounds any previously exposed surface of the material. The material is thereby protected from subsequent exposure to substances that may be deleterious.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: January 11, 2000
    Assignee: The Trustees of Princeton University
    Inventors: Paul Burrows, Stephen R. Forrest, Peifang Tian
  • Patent number: 6013537
    Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the devices perform characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: January 11, 2000
    Assignee: International Business Machines Corporation
    Inventor: Daniel M. Kuchta
  • Patent number: 5976953
    Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: November 2, 1999
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Matthew Zavracky, Duy-Phach Vu, Brenda Dingle
  • Patent number: 5940683
    Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: August 17, 1999
    Assignee: Motorola, Inc.
    Inventors: Paige M. Holm, Chan-Long Shieh, Curtis D. Moyer
  • Patent number: 5893721
    Abstract: A method of fabricating an active matrix LED array includes forming layers of material on a substrate, which layers cooperate to emit light when activated. Row and column dividers are formed in the layers to divide the layers into an array of LEDs arranged in rows and columns. One FET is formed on the row dividers in association with each LED and a source of each FET is connected to an anode of the associated LED. Row and column buses are formed on the row and column dividers, respectively, and the drain of each FET is connected to an adjacent row bus with the gate of each FET being connected to an adjacent column bus. A cathode for each LED is connected as a common terminal for all of the LEDs in the array.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: April 13, 1999
    Assignee: Motorola, Inc.
    Inventors: Rong-Ting Huang, Phil Wright, Paige M. Holm
  • Patent number: 5891746
    Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: April 6, 1999
    Assignee: International Business Machines Corporation
    Inventor: Daniel M. Kuchta
  • Patent number: 5759872
    Abstract: A passive region is provided adjacent the mirror surface of a laser. A mesa is formed with an end face parallel to the mirror surface to be formed. The passive region is grown against the end face, and the mirror surface is formed therein by cleaving. The passive region is provided exclusively at the area of the active region. The passive region is provided at the area of the active region preferably in the following manner: two depressions are formed in the layer structure of the laser at the area of the mirror surface to be formed, reaching down to the active layer. Then a portion of the active layer situated between the depressions is selectively removed, whereupon the passive region is grown starting from the depressions in the tubular cavity thus formed.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: June 2, 1998
    Inventors: Raymond Van Roijen, Petrus J.A. Thijs, Patrick H. Van Gestel
  • Patent number: 5665654
    Abstract: A method for forming an electrical connection between a semiconductor die and a corresponding electrical component mounted within an electrical device is provided. The method includes wire bonding metal wires to the bond pads of the die and then severing the metal wires to form loose leads attached to the bond pads. With the die mounted to the electrical device, the loose leads are bonded to the electrical component using a bonding tip. In an illustrative embodiment, the electrical device is a field emission display package and the electrical component is conductive traces for the package. Advantageous, the method can be used to form the electrical connection between the die mounted in a sealed space and the corresponding electrical component which is outside of the sealed space.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: September 9, 1997
    Assignee: Micron Display Technology, Inc.
    Inventor: Darryl M. Stansbury
  • Patent number: 5656548
    Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: August 12, 1997
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Matthew Zavracky, Duy-Phach Vu, Brenda Dingle
  • Patent number: 5633176
    Abstract: A semiconductor substrate is utilized to integrally form a drive circuit and a pixel array to produce a transparent semiconductor device for a light valve comprising a pixel array region and a drive circuit region on a major face of the semiconductor substrate. A stopper film is formed on the major face of the semiconductor substrate at the pixel array region, and a pixel array is formed over the silicon oxide stopper film. A drive circuit is formed on the drive circuit region, and silicon oxide posts are embedded in the major face of the semiconductor substrate at the drive circuit region. A thickness of the semiconductor substrate is then selectively removed from a back face opposite to the major face thereof to reach the stopper film. After the selective removing step, the portion of the semiconductor substrate under the pixel region is completely removed while a portion of the semiconductor substrate under the drive circuit region remains.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: May 27, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Yoshikazu Kojima, Kunihiro Takahashi, Tsuneo Yamazaki, Tadao Iwaki