Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
  • Patent number: 8766346
    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Xiangxin Rui, Sergey Barabash
  • Patent number: 8765547
    Abstract: An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Shu-Jen Han, George S. Tulevski
  • Patent number: 8748258
    Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam Shahidi
  • Patent number: 8741712
    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: June 3, 2014
    Assignees: Intermolecular, Inc., Elpidia Memory, Inc.
    Inventors: Tony P. Chiang, Wim Y. Deweerd, Sandra G Malhotra
  • Patent number: 8735243
    Abstract: A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew W. Copel, Bruce B. Doris, Vijay Narayanan, Yun-Yu Wang
  • Patent number: 8728901
    Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: May 20, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas Davenport, John Cronin
  • Patent number: 8722504
    Abstract: A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 13, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Wim Deweerd, Hiroyuki Ode
  • Patent number: 8716833
    Abstract: A method of manufacturing a semiconductor device including forming on a substrate an insulating interlayer through which a capacitor contact is interposed; forming on the insulating interlayer a first upper electrode having an opening through which the capacitor contact is exposed; forming a first dielectric layer pattern on a lateral wall of the opening; forming a lower electrode on the first dielectric layer pattern formed in the opening and the capacitor contact; forming a second dielectric layer pattern on the lower electrode formed in the opening and the first dielectric layer pattern; and forming on the second dielectric layer pattern a second upper electrode so as to fill the opening and to contact the first upper electrode. The semiconductor device may prevent a lower electrode of a capacitor from collapsing.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-woong Koo
  • Patent number: 8709890
    Abstract: An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8710567
    Abstract: The semiconductor device of the present invention includes a silicon substrate having a logic region and a RAM region, an NMOS transistor formed in the logic region, and an NMOS transistor formed in the RAM region. The NMOS transistor has a stack structure obtained by sequentially stacking the gate insulating film and the metal gate electrode over the silicon substrate. The NMOS transistor has a cap film containing an element selected from a group consisting of lanthanum, ytterbium, magnesium, strontium, and erbium as a composition element between the silicon substrate and metal gate electrode. The cap film is not formed in the NMOS transistor.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiko Moriya
  • Patent number: 8709891
    Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 29, 2014
    Assignee: 4D-S Ltd.
    Inventors: Zhida Lan, Dongmin Chen
  • Patent number: 8697517
    Abstract: The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Hak-Lay Chuang, Ming Zhu, Lee-Wee Teo
  • Patent number: 8697516
    Abstract: A capacitor (110), wherein the capacitor (110) comprises a capacitor dielectric (112) comprising a dielectric matrix (114) of a first value of permittivity, and a plurality of nanoclusters (116) of a second value of permittivity which is larger than the first value of permittivity which are at least partially embedded in the dielectric matrix (114), wherein the plurality of nanoclusters (116) are formed in the dielectric matrix (114) by spontaneous nucleation.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: April 15, 2014
    Assignee: NXP, B.V.
    Inventors: Yukiko Furukawa, Jinesh Balakrishna Pillai Kochupurackal, Johan Hendrik Klootwijk, Frank Pasveer
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Patent number: 8685819
    Abstract: A method for making a crossbar array of crossed conductive or semi-conductive access lines on a substrate, the crossbar array including on a crossbar array insulator, in a plane parallel to the substrate, a first level of lines including a plurality of first lines parallel with each other made of a conductive or semi-conductive material; on the first level of lines, a second level of lines including a plurality of second lines parallel with each other made of a conductive or semi-conductive material, the second lines being substantially perpendicular to the first lines. The method includes forming, on the substrate, a first cavity of substantially rectangular shape; forming a second cavity of substantially rectangular shape superimposed to the first cavity, the first and second cavities intersecting each other perpendicularly so as to form a resultant cavity.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: April 1, 2014
    Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche Scientifique, Universite Joseph Fourier
    Inventors: Julien Buckley, Karim Aissou, Thierry Baron, Gabriel Molas
  • Patent number: 8685815
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8679913
    Abstract: A film is formed so that the atomic numbers ratio of Sr to Ti, i.e., Sr/Ti, in the film is not less than 1.2 and not more than 3. The film is then annealed in an atmosphere containing not less than 0.001% and not more than 80% of O2 at 500° C. or above. An SrO film forming step or a TiO film forming step are repeated a plurality of times so that a sequence, in which a plurality of SrO film forming steps or/and a plurality of TiO film forming steps are performed continuously, is included. When Sr is oxidized after the adsorption of Sr, O3 and H2O are used as an oxidizing agent.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: March 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Yumiko Kawano, Susumu Arima, Akinobu Kakimoto, Toshiyuki Hirota, Takakazu Kiyomura
  • Patent number: 8664061
    Abstract: The present invention provides systems, methods and apparatus for manufacturing a memory cell. The invention includes forming a feature having sidewalls in a first dielectric material; forming a first conductive material on the sidewalls of the feature; depositing a layer of a second dielectric material on the conductive material; and exposing the second dielectric material to oxidizing species and ultraviolet light to oxidize the second dielectric material. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: March 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Juan Carlos Rocha-Alvarez, Sanjeev Baluja
  • Patent number: 8659066
    Abstract: An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8658493
    Abstract: An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening (51t) where a portion of a top electrode is exposed and an opening (51b) where a portion of a bottom electrode is exposed are formed in the aluminum oxide film. Thereafter, films (23 to 26) are formed and a resist pattern (92) is formed. Then, etching of the films (23 to 26) is performed with using the resist pattern (92) as a mask thereby forming contact holes (27t) and (27b). At this time, since the openings (51t) and (51b) are formed in the aluminum oxide film, the aluminum oxide film is not required to be processed. Consequently, the contact holes (27t) and (27b) can be formed easily.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: February 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8659062
    Abstract: A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8648992
    Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 11, 2014
    Assignees: Mitsubishi Materials Corporation, STMicroelectronics(Tours) SAS
    Inventors: Hideaki Sakurai, Toshiaki Watanabe, Nobuyuki Soyama, Guillaume Guegan
  • Patent number: 8647988
    Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 11, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
  • Patent number: 8647943
    Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode materials are conductive molybdenum oxide.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 11, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Y. Deweerd, Edward L Haywood, Sandra G Malhotra, Hiroyuki Ode
  • Patent number: 8633118
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 21, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8623725
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 8617949
    Abstract: A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
  • Patent number: 8603877
    Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: December 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Noel Rocklein, Chris Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
  • Patent number: 8604532
    Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Win K. Luk, Jin Cai
  • Patent number: 8603876
    Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Win K. Luk, Jin Cai
  • Patent number: 8592979
    Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hei-Seung Kim, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee
  • Patent number: 8586430
    Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kenji Komeda
  • Patent number: 8574985
    Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: November 5, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Sunil Shanker, Sandra Malhotra, Imran Hashim, Edward Haywood
  • Patent number: 8569819
    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ??cm. Advantageously, the electrode layers are conductive molybdenum oxide.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: October 29, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hiroyuki Ode
  • Patent number: 8563420
    Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: October 22, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Akira Mochida
  • Patent number: 8557713
    Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Hyung-Suk Jung, Yun-Ki Choi
  • Patent number: 8551837
    Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu Chao Lin
  • Patent number: 8552515
    Abstract: Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: October 8, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Publication number: 20130256773
    Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.
    Type: Application
    Filed: May 21, 2013
    Publication date: October 3, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Shanjen Pan, Allan T. Mitchell, Weidong Tian
  • Patent number: 8518791
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8518792
    Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Thomas E. Davenport, John Cronin
  • Patent number: 8513724
    Abstract: A gate insulating film includes an oxygen-containing insulating film and a high dielectric constant insulating film formed on the oxygen-containing insulating film and containing a first metal. The high dielectric constant insulating film further includes a second metal different from the first metal. Part of the high dielectric constant insulating film having the maximum composition ratio of the second metal is away from an interface between the high dielectric constant insulating film and the oxygen-containing insulating film and an interface between the high dielectric constant insulating film and the gate electrode. The second metal exists also in a portion of the oxygen-containing insulating film near the interface between the high dielectric constant insulating film and the oxygen-containing insulating film.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 20, 2013
    Assignee: Panasonic Corporation
    Inventor: Shinji Takeoka
  • Patent number: 8513634
    Abstract: A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and an upper electrode stacked on the second discharge prevention layer. The phase transition layer includes oxygen and exhibits two different resistance characteristics depending on whether an insulating property thereof changed. The first and second discharge prevention layers block discharge of the oxygen from the phase transition layer.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Sung-ho Park, Myoung-jae Lee, Young-soo Park
  • Patent number: 8507355
    Abstract: A method of manufacturing high performance metal-oxide-metal capacitor device that resolves problems with implementing high capacitance in the metal-oxide-metal region by filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and filling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 13, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Youcun Hu, Lei Li, Chaos Zhang, Feng Ji, Yuwen Chen
  • Patent number: 8507967
    Abstract: Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on the storage capacitor region and the higher voltage resistance capacitor region. A first dielectric film may be formed on the lower electrode layer, and the first dielectric film of the storage capacitor region may be selectively removed to expose the lower electrode layer of the storage capacitor region. After forming a second dielectric film on the first dielectric film and the exposed lower electrode layer of the storage capacitor region, an upper electrode layer may be formed on the second dielectric film.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hwa-Sook Shin
  • Patent number: 8501560
    Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 6, 2013
    Assignees: Mitusbishi Materials Corporation, STMicroelectronics(Tours) SAS
    Inventors: Hideaki Sakurai, Toshiaki Watanabe, Nobuyuki Soyama, Guillaume Guegan
  • Patent number: 8491799
    Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin-Ki Jung
  • Patent number: 8492258
    Abstract: A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminum nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminum nitride film and formation of a titanium nitride film are alternately repeated, and at that time, the aluminum nitride film is formed firstly and/or lastly.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 23, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Kazuhiro Harada
  • Patent number: 8486780
    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode layers are conductive molybdenum oxide.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: July 16, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Hiroyuki Ode
  • Publication number: 20130175596
    Abstract: An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Kangguo CHENG, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi