Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
  • Patent number: 7883961
    Abstract: A manufacturing method for a ferroelectric memory device including: forming a lower electrode; forming an electrode oxide film composed of an oxide of a constituent material of the lower electrode; forming a first ferroelectric layer on the lower electrode by reaction between organometallic source material gas and oxygen gas; forming a second ferroelectric layer on the first ferroelectric layer by reaction between organometallic source material gas and oxygen gas; and forming an upper electrode on the second ferroelectric layer. In the method, the oxygen gas in the forming of the first ferroelectric layer is in an amount less than the amount of oxygen necessary for reaction of the organometallic source material gas. In the method, the oxygen gas in the forming of the second ferroelectric layer is in an amount greater than the amount of oxygen necessary for reaction of the organometallic source material gas.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: February 8, 2011
    Assignees: Seiko Epson Corporation, Fujitsu Semiconductor Limited
    Inventors: Hiroaki Tamura, Masaki Kurasawa, Hideki Yamawaki
  • Patent number: 7879739
    Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, James Blackwell, Suman Datta, Jack T. Kavalieros, Mantu K. Hudait
  • Patent number: 7881092
    Abstract: An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: February 1, 2011
    Assignee: Rising Silicon, Inc.
    Inventor: Klaus Ufert
  • Patent number: 7879626
    Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: February 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Ohnishi, Naoyuki Shinmura, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri, Shigeo Ohnishi
  • Patent number: 7880241
    Abstract: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7867788
    Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: January 11, 2011
    Assignees: Freescale Semiconductor, Inc., Centre National de la Recherché Scientifique (CNRS), STMicroelectronics (Crolles 2) SAS
    Inventors: De Come Buttet, Michel Hehn, Stephane Zoll
  • Patent number: 7863060
    Abstract: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH3OH. Preferably, a photoresist mask layer is removed by oxygen plasma between the fluorocarbon and CH3OH plasma etches. A lower hard mask layer made of NiCr or the like is inserted to prevent formation and buildup of Ta etch residues that can cause device shunting.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 4, 2011
    Assignee: MagIC Technologies, Inc.
    Inventors: Rodolfo Belen, Tom Zhong, Witold Kula, Chyu-Jiuh Torng
  • Patent number: 7855114
    Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: December 21, 2010
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Mark Randolph, Hidehiko Shiraiwa
  • Patent number: 7846795
    Abstract: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jie Won Chung
  • Patent number: 7829476
    Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: November 9, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Kaoru Saigoh
  • Patent number: 7820506
    Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 26, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Noel Rocklein, Chris M. Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
  • Patent number: 7816716
    Abstract: Source/drain diffusion layers and a channel region are formed in a polysilicon thin film formed on a substrate made of glass or the like, and furthermore, a gate electrode 6 is formed via a gate insulating film. A silicon hydronitride film is formed on the interlayer dielectric film, whereby the hydrogen concentration in an active element region including a switching thin film transistor can be maintained at a high level, and Si—H bonds in the silicon thin film become stable. In addition, by providing a ferroelectric film on the silicon hydronitride film via a lower electrode formed of a conductive oxide film, whereby the oxygen concentration of the ferroelectric capacitive element layer can be maintained at a high level, and generation of oxygen deficiency in the ferroelectric film is prevented.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: October 19, 2010
    Assignee: NEC Corporation
    Inventor: Hiroshi Tanabe
  • Patent number: 7811834
    Abstract: A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: October 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Im, Ik-Soo Kim, Choong-Man Lee, Jang-Eun Heo, Sung-Ju Lee
  • Patent number: 7804144
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: September 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7799631
    Abstract: A dielectric layer of a capacitor includes a first dielectric layer, a second dielectric layer formed over the first dielectric layer, the second dielectric layer having a dielectric constant lower than that of the first dielectric layer, and a third dielectric layer formed over the second dielectric layer, the third dielectric layer having a dielectric constant higher that of than the second dielectric layer, wherein the third dielectric layer has a greater thickness than each of the first and second dielectric layers.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: September 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Patent number: 7795663
    Abstract: The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped with 0.002-0.05 atom percent of a dopant comprising an element selected from Sc, Cr, Fe, Co, Ni, Ca, Zn, Al, Ga, Y, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu and mixtures thereof and to capacitors comprising such compositions.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: September 14, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Seigi Suh, William J. Borland
  • Patent number: 7790535
    Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: September 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 7790627
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7790558
    Abstract: Method of enhancing stress in a semiconductor device having a gate stack disposed on a substrate. The method utilizes depositing a nitride film along a surface of the substrate and the gate stack. The nitride film is thicker over a surface of the substrate and thinner over a portion of the gate stack.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Haining S. Yang, Huilong Zhu
  • Patent number: 7785958
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Patent number: 7786521
    Abstract: A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an upper electrode formed on the first dielectric layer.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: August 31, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Seon Park, Jae-Sung Roh
  • Patent number: 7776762
    Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7763951
    Abstract: A fuse structure (106) includes a patterned conductor disposed over a passivation layer (302), which is disposed over a substrate (110), such as, for example, an inter-layer dielectric layer of an integrated circuit. A second passivation layer (112) is formed over the integrated circuit including over the fuse structure (106), and then patterned to open a window (108) through the second passivation layer (112) at a location over the fuse structure (106), with the window (108) fully landed by the underlying passivation layer (302). In various aspects of the present invention, the fuse (106) may be programmed either before or after the photoresist layer used in the patterning of the second passivation layer (112) is removed.
    Type: Grant
    Filed: September 18, 2004
    Date of Patent: July 27, 2010
    Assignee: NXP B.V.
    Inventors: Piebe Anne Zijlstra, Elizabeth Ann Killian
  • Patent number: 7759718
    Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yeol Kang, Jong-cheol Lee, Ki-vin Im, Jae-hyun Yeo, Hoon-sang Choi, Eun-ae Chung
  • Patent number: 7754614
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: July 13, 2010
    Assignee: Nanya Technologies Corporation
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Patent number: 7754563
    Abstract: Nanolaminate-structure SrO/TiO films are formed on a lower electrode of a capacitor by molecular layer deposition kept in a rate-determined state by a surface reaction. The nanolaminate-structure SrO/TiO films are formed by alternately laminating one or more and 20 or less SrO molecular layers and one or more and 20 or less TiO molecular layers at 150° C. or more and 400° C. or less and at 10 Torr or more and the atmospheric pressure or less. This makes it possible to obtain the nanolaminate-structure SrO/TiO films with a high permittivity and a high coverage and with no occurrence of crystalline foreign substance.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: July 13, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Naruhiko Nakanishi
  • Patent number: 7745280
    Abstract: A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: June 29, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Yu-Ho Chiang
  • Patent number: 7745279
    Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: June 29, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yee-Chia Yeo, Chenming Hu
  • Patent number: 7741173
    Abstract: A method for forming a capacitor insulation film includes the step of depositing a monoatomic film made of a metal by supplying a metal source including the metal and no oxygen, and depositing a metal oxide film including the metal by using a CVD technique. The method provides the metal oxide film having higher film properties with a higher throughput.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: June 22, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Kenichi Koyanagi, Hiroshi Sakuma
  • Patent number: 7741231
    Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mole vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: June 22, 2010
    Assignee: International Business Machines Corporation
    Inventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
  • Patent number: 7735206
    Abstract: A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 15, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Patent number: 7732852
    Abstract: High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: June 8, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jiong-Ping Lu, Ming-Jang Hwang
  • Patent number: 7732851
    Abstract: A capacitor and a method of fabricating the capacitor are provided herein. The capacitor can be formed by forming two or more dielectric layers and a lower electrode, wherein at least one of the two or more dielectric layers is formed before the lower electrode is formed.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Sung-ho Park, Sang-jun Choi
  • Patent number: 7728376
    Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: June 1, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Matsui, Hiroshi Miki
  • Patent number: 7727777
    Abstract: In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: June 1, 2010
    Inventors: Ebrahim Andideh, Mark Isenberger, Michael Leeson, Mani Rahnama
  • Patent number: 7723199
    Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
  • Patent number: 7723771
    Abstract: A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 25, 2010
    Assignee: Qimonda AG
    Inventors: Tim Boescke, Uwe Schroeder
  • Patent number: 7718551
    Abstract: A method for forming a photoresist layer is provided. The method includes following steps. A wafer is provided in a semiconductor machine. The wafer is spun at a first spin speed. A pre-wet solvent is dispensed on the spinning wafer by using a nozzle disposed at a fixed position. The pre-wet solvent then stops dispensing. The spin speed of the wafer is adjusted from the first spin speed to a second spin speed which is faster than the first spin speed. Thereafter, a photoresist layer is coated on the wafer.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: May 18, 2010
    Assignee: United MIcroelectronics Corp.
    Inventors: Yu-Huan Liu, Chih-Jung Chen, Chih-Chung Huang
  • Patent number: 7718487
    Abstract: A method of manufacturing a ferroelectric layer, including: forming a first ferroelectric layer above a base by a vapor phase method; and forming a second ferroelectric layer above the first ferroelectric layer by a liquid phase method.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: May 18, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Kijima
  • Patent number: 7713831
    Abstract: A method for forming a capacitor in a semiconductor device is disclosed. The method includes forming a storage node electrode on a semiconductor substrate, forming a dielectric layer having a high dielectric constant on the storage node electrode, depositing a plate electrode on the dielectric layer, thereby forming by-product impurities, and removing by-product impurities remaining on the plate electrode by introducing a hydrogen (H) atom-containing gas onto the semiconductor substrate while depositing a capping layer on the plate electrode.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: May 11, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol-Hwan Park, Dong-Su Park, Eun A. Lee, Hye Jin Seo
  • Patent number: 7713812
    Abstract: A substrate with a second semiconductor layer and a second mask film formed thereon is subjected to a heat treatment in an oxidizing atmosphere. Thus, second oxidized regions are formed through oxidization of the second semiconductor layer in regions of the second semiconductor layer that are not covered by the second mask film. At the same time, a second base layer is formed in each region that is interposed by the second oxidized regions. Then, the second mask film is removed, and a third semiconductor layer is selectively grown on the surface of the second base layer that is exposed between the second oxidized regions so as to cover the second oxidized regions, after which the first oxidized regions and the second oxidized regions covering the entire upper surface of the substrate are removed.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: May 11, 2010
    Assignee: Panasonic Corporation
    Inventors: Tetsuzo Ueda, Hisashi Nakayama, Masaaki Yuri
  • Patent number: 7700989
    Abstract: Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7700430
    Abstract: A phase changeable random access memory (PRAM) and methods for manufacturing the same. An example unit cell of a non-volatile memory, such as a PRAM, includes a MOS transistor, connected to an address line and a data line, where the MOS transistor receives a voltage from the data line. The unit cell further includes a phase change material for changing phase depending on heat generated by the voltage and a top electrode, connected to a substantially ground voltage.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Guil Yang, Hong-Sik Jeong, Young-Nam Hwang
  • Patent number: 7691669
    Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Raymond R. Horton, John U. Knickerbocker, Edmund J. Sprogis, Cornelia K. Tsang
  • Patent number: 7687285
    Abstract: A method for manufacturing a ferroelectric memory includes the steps of: forming an iridium film above a substrate; forming an iridium oxide layer on the iridium film; changing the iridium oxide layer into an amorphous iridium layer; oxidizing the amorphous iridium layer to form an iridium oxide portion; forming a ferroelectric film on the iridium oxide portion by a MOCVD method; and forming an electrode on the ferroelectric film.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: March 30, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Hiroaki Tamura
  • Patent number: 7670899
    Abstract: A MIM capacitor includes a lower electrode disposed on a semiconductor substrate. A dielectric layer is disposed on the lower electrode to completely cover an exposed surface of the lower electrode. An upper electrode is disposed on the dielectric layer. A method for forming a MIM capacitor includes forming a lower electrode on a semiconductor substrate. A dielectric layer and an upper metal layer are formed on an entire surface of the substrate to cover the lower electrode. The dielectric and upper metal layers are patterned on the lower electrode.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 2, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Ki Min Lee
  • Patent number: 7670921
    Abstract: A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Douglas D. Coolbaugh, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Anthony K. Stamper, Richard P. Volant
  • Patent number: 7666801
    Abstract: A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more precursor compounds that include aminosilane ligands.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Timothy A. Quick
  • Patent number: 7652377
    Abstract: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors (101) and along a dicing line (110) inside the dicing line (110).
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: January 26, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tetsuo Yaegashi, Kouichi Nagai
  • Patent number: 7651907
    Abstract: A method for fabricating a semiconductor device, the method includes forming an etch stop layer and an insulation layer over a substrate having a first region and a second region, selectively removing the insulation layer and the etch stop layer in the first region to expose parts of the substrate, thereby forming at least two electrode regions on the exposed substrate and a resultant structure, forming a conductive layer over the resultant structure, removing the conductive layer in the second region, removing the insulation layer in the first region and the second region by using wet chemicals, and removing parts of the conductive layer, which formed between the at least two electrode regions in the first region, to form cylinder type electrodes in the first region.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: January 26, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho