Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
  • Patent number: 7465626
    Abstract: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: December 16, 2008
    Assignees: Interuniversitair Microelektronica Centrum vzw, ASM America Inc.
    Inventors: Peijun Jerry Chen, Tsai Wilman, Mathieu Caymax, Jan Willem Maes
  • Patent number: 7462901
    Abstract: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: December 9, 2008
    Assignee: Infineon Technologies AG
    Inventor: Helmut Tews
  • Patent number: 7459371
    Abstract: A method for non-volatile memory fabrication is provided, in which a substrate is provided, a bottom electrode is formed on the substrate, a solution with precursors of Zr and Sr is coated on the bottom electrode, the solution on the bottom electrode surface is dried and then fired to form a resistor layer of SrZrO3, and a top electrode is formed on the resistor layer.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: December 2, 2008
    Assignee: Winbond Electronics Corp.
    Inventors: Tseung-Yuen Tseng, Chih-Yi Liu, Chun-Chieh Chuang
  • Patent number: 7456064
    Abstract: A dielectric material having a high dielectric constant includes a Group III metal oxide and a Group V element. The incorporation of the Group V element in the Group III metal oxide material reduces the number of structural defects in the dielectric material, and reduces both the fixed charge density and the conduction current of the dielectric material.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: November 25, 2008
    Assignee: Agere Systems Inc.
    Inventors: Lalita Manchanda, Martin Laurence Green
  • Patent number: 7449346
    Abstract: A method of manufacturing a ferroelectric thin film with good crystallinity and improved surface roughness includes: forming on a substrate a metal nitride-based precursor layer containing one selected from the group consisting of TiN, ZrxTi(1-x)N (0<x<1), FeN, and NbN; forming on the metal nitride-based precursor layer a mixed gas atmosphere containing oxygen (O2) and one reactive gas selected from the group consisting of PbO(g), Bi2O3(g), and K2O(g); annealing the metal nitride-based precursor layer in the mixed gas atmosphere and forming a ferroelectric thin film containing one selected from the group consisting of PbTiO3, PbZrxTi(1-x)O3 (0<x<1), Bi2Ti2O7, Bi4Ti3O12, BiFeO3, and KNbO3.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Simon Buehlmann
  • Patent number: 7442604
    Abstract: Provided are methods of manufacturing dielectric films including forming a first dielectric film on a wafer using atomic layer deposition (ALD) in a first batch type apparatus, forming a second dielectric film on the first dielectric film using atomic layer deposition in a second batch type apparatus, wherein the second dielectric film has a higher crystallization temperature than the first dielectric film and forming a third dielectric film on the second dielectric film using atomic layer deposition in a third batch type apparatus. Methods of manufacturing metal-insulator-metal (MIM) capacitors using the methods of forming the dielectric films and batch type atomic layer deposition apparatus for forming the dielectric films are also provided.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Jung-hee Chung, Se-hoon Oh, Jong-cheol Lee
  • Patent number: 7439127
    Abstract: A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The method comprises forming a first capacitor electrode in the first semiconductor layer and depositing a dielectric layer comprising Ba1-xCaxTi1-yZryO3 overlying the first capacitor electrode. A conductive material is deposited and patterned to form a second capacitor electrode overlying the dielectric layer, thus forming a capacitor having a high dielectric constant dielectric. An MOS transistor in then formed in a portion of the second semiconductor layer, the MOS transistor, and especially the gate dielectric of the MOS transistor, formed independently of forming the capacitor and electrically isolated from the capacitor.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: October 21, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mario M. Pelella
  • Patent number: 7435641
    Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 14, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Publication number: 20080248618
    Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.
    Type: Application
    Filed: May 8, 2008
    Publication date: October 9, 2008
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7432548
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or more monolayers. Metal electrodes may be disposed on a dielectric containing a silicon lanthanide oxynitride film.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7429515
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: September 30, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7425514
    Abstract: Disclosed are methods of forming dielectric materials using atomic layer deposition (ALD) and methods of forming dielectric layers from such materials on a semiconductor device. The ALD process utilizes a first reactant containing at least one alkoxide group that is chemisorbed onto a surface of a substrate and then reacted with an activated oxidant that contains no hydroxyl group to form a dielectric material exhibiting excellent step coverage and improved leakage current characteristics.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Yeo, Young-Sun Kim, Sung-Tae Kim, In-Sung Park, Gi-Vin Im
  • Patent number: 7422943
    Abstract: Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: September 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-cheol Lee, Young-sun Kim, Jung-hee Chung, Jae-hyoung Choi, Se-hoon Oh, Hong-bum Park
  • Patent number: 7419837
    Abstract: A Pt film (24), a PLZT film (25), and a top electrode film (26) are formed above a semiconductor substrate (11). Next, the top electrode film (26) is patterned. Then, a PLZT film (27) covering an exposed portion of the PLZT film (25) is formed as an evaporation preventing film. Then, heat treatment is performed in an oxidative atmosphere to recover damage sustained to the PLZT film (25). Heat treatment is not performed between patterning of the top electrode film (26) and formation of the PLZT film (27). Thereafter, a ferroelectric capacitor is formed by patterning the PLZT film (25) and the Pt film (24).
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: September 2, 2008
    Assignee: Fujitsu Limited
    Inventor: Wensheng Wang
  • Patent number: 7416904
    Abstract: A fabrication method for forming a semiconductor device having a capacitor is provided. A capacitor dielectric layer is formed by depositing a first layer and a second layer. The second layer is a major portion of the capacitor dielectric layer. The first layer acts as a seed layer, while the second layer is expitaxially grown. The material of the second layer as deposited is partially crystal. Nuclear generation and crystal growth occur separately so that the crystalline characteristic of the capacitor dielectric layer and the capacitance characteristic of the capacitor are enhanced. Moreover, the capacitor dielectric layer is crystallized at a relatively low temperature or for a relatively short time, thereby reducing leakage current as well as reducing deformation in the lower electrode. Optionally, The material of the second layer as deposited is not partially crystal but amorphous.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyoung Choi, Cha-Young Yoo, Suk-Jin Chung, Wan-Don Kim
  • Patent number: 7416936
    Abstract: The present invention relates to a capacitor having a hafnium oxide and aluminum oxide alloyed dielectric layer and a method for fabricating the same. The capacitor includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer, wherein a portion of the dielectric layer contacting one of the lower electrode and the upper electrode is formed by alloying hafnium oxide and aluminum oxide together.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: August 26, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Deok-Sin Kil, Jae-Sung Roh, Hyun-Chul Sohn
  • Patent number: 7413947
    Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes a second capacitor plate (160) located over the insulator (130) and a top-level dielectric layer (199) located at least partially along a sidewall of the second capacitor plate (160).
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: August 19, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: David L. Larkin, Ashish V. Gokhale, Dhaval A. Saraiya, Quang Xuan Mai
  • Patent number: 7413949
    Abstract: A capacitor is formed on an interlayer insulating film formed on a semiconductor substrate. The capacitor includes a bottom electrode made of platinum, a capacitor insulating film made of SrTaBiO (SBT) containing an element absorbing hydrogen such as titanium, for example, in grain boundaries, inter-lattice positions or holes, and a top electrode made of platinum.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: August 19, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takumi Mikawa, Yuji Judai, Shinichiro Hayashi
  • Patent number: 7410812
    Abstract: A method contains the steps of (a) heating a silicon substrate in a reaction chamber; and (b) supplying film-forming gas containing source gas, nitridizing gas, and nitridation enhancing gas to a surface of the heated silicon substrate, to deposit on the silicon substrate an Hf1-xAlxO:N film (0.1<x<0.3) having a higher specific dielectric constant than that of silicon oxide, and incorporating N, by thermal CVD. The method can form an oxide film of Hf1-xAlxO (0<x<0.3) having desired characteristics, as a gate insulation film.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: August 12, 2008
    Assignee: Fujitsu Limited
    Inventor: Masaomi Yamaguchi
  • Patent number: 7407819
    Abstract: A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a first distance from one another, and the bit lines have center lines spaced by a second distance from one another, the second distance being less than the first distance. Three masking steps are required to manufacture the three layers of lines. Older-technology machinery and masks are used to form the two layers of word lines, and new-technology machinery and masks are used to manufacture the bit lines.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: August 5, 2008
    Assignee: Intel Corporation
    Inventor: Mark S. Isenberger
  • Patent number: 7405121
    Abstract: An interlayer insulating film (22) is formed on a semiconductor substrate. A conductive plug (25) is embedded in a via hole formed through the interlayer insulating film. An oxygen barrier conductive film (33) is formed on the interlayer insulating film and being inclusive of an area of the conductive plug as viewed in plan. A capacitor (35) laminating a lower electrode, a dielectric film and an upper electrode in this order is formed on the oxygen barrier film. An intermediate layer (34) is disposed at an interface between the oxygen barrier film and the lower electrode. The intermediate layer is made of alloy which contains at least one constituent element of the oxygen barrier film and at least one constituent element of the lower electrode.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: July 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Wensheng Wang
  • Patent number: 7399666
    Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr3N4) and zirconium oxide (ZrO2) and a method of fabricating such a dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing zirconium oxide using atomic layer deposition using precursor chemicals, followed by depositing zirconium nitride using precursor chemicals, and repeating. Alternatively, the zirconium nitride may be deposited first followed by the zirconium nitride, thus providing a different work function. Such a dielectric may be used as the gate insulator of a MOSFET, a capacitor dielectric, or a tunnel gate insulator in memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because of the reduced leakage current of the physically thicker dielectric layer when compared to an electrically equivalent thickness of silicon dioxide.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7396719
    Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-seok Kim, Hong-bae Park, Bong-hyun Kim, Sung-tae Kim, Jong-wan Kwon, Jung-hyun Lee, Ki-chul Kim, Jae-soon Lim, Gab-jin Nam, Young-sun Kim
  • Patent number: 7393742
    Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substrate and formed in the contact hole, a buffer conductive layer pattern electrically connected to the contact plug and formed on the insulating layer and the contact plug, an etching stopping layer formed on the buffer conductive layer pattern, a gap between the buffer conductive layer pattern and the etching stopping layer, a capacitor lower electrode electrically connected to the buffer conductive layer pattern and formed on the buffer conductive layer pattern. The gap is filled by a portion of the capacitor lower electrode.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-Mo Park
  • Patent number: 7390712
    Abstract: Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The enhanced capacitor includes a first electrode, a dielectric that includes ditantalum pentaoxide, and a second electrode having a compound. The compound includes a first substance and a second substance. The second electrode includes a trace amount of the first substance. The morphology of the semiconductor structure remains stable when the trace amount of the first substance is oxidized during crystallization of the dielectric. In one embodiment, the crystalline structure of the dielectric describes substantially a (001) lattice plane.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: June 24, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Vishnu K. Agarwal, Dan Gealy
  • Patent number: 7387929
    Abstract: The present invention relates to a capacitor in semiconductor device and a method of manufacturing the same, wherein, owing to formation of a lower electrode and an upper electrode into a stack structure of a poly-silicon layer and an aluminum (Al) layer and formation of an alumina (Al2O3) film as a dielectric film, the lower electrode is formed into a stack structure of the poly-silicon layer-aluminum (Al) layer, thus increasing a surface area of electrodes due to the absence of oxidation during annealing, and preventing degeneration of the device, and use of the dielectric film including a high-dielectric constant material layer enables reduction of the dielectric film's thickness. Accordingly, the present invention is capable of increasing capacitance, is capable of reducing leakage current and improving dielectric breakdown characteristics via internal formation of an MIM capacitor, and is capable of reducing production costs by performing a continuous process via use of a single piece of equipment.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: June 17, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun A. Lee, Hai Won Kim
  • Patent number: 7378310
    Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 27, 2008
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Connie Pin-Chin Wang, Zoran Krivokapic, Suzette Keefe Pangrle, Robert Chiu, Lu You
  • Patent number: 7374994
    Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: May 20, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Cho, Yo-sep Min, Young-soo Park, Jung-hyun Lee, June-key Lee, Yong-kyun Lee
  • Patent number: 7374954
    Abstract: The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capacitors in parallel in a ferroelectric capacitor unit for storing data, instead of using a single capacitor, thereby improving storage reliability and stability. In addition, the ferroelectric register obtains a data sensing margin by pumping a cell plate signal into not a power voltage level but a pumping voltage level.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: May 20, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 7374953
    Abstract: A ferroelectric random access memory (FRAM) includes a semiconductor substrate and an interlayer insulating layer on the substrate. A diffusion preventive layer is on the interlayer insulating layer. The diffusion preventive layer and the interlayer insulating layer have two node contact holes formed therein. Node conductive layer patterns are aligned with the node contact holes, respectively, and are disposed so as to protrude upward from the diffusion preventive layer. Lower electrodes are disposed on the diffusion preventive layer that cover the node conductive layer patterns, respectively. Thicknesses of the lower electrodes are gradually reduced from a line extending from upper surfaces of the node conductive layer patterns toward the diffusion preventive layer.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: May 20, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Sook Lee
  • Patent number: 7374998
    Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
  • Patent number: 7371633
    Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 13, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Ho Lee, Nae-In Lee
  • Patent number: 7368300
    Abstract: The present invention relates to a capacitor in a semiconductor device and a method for fabricating the same. The capacitor fabrication method includes the steps of: forming a lower electrode by using a thin film of (Ba,Sr)RuO3 (BSR) on a substrate provided with various device elements; forming a dielectric layer on the lower electrode by using a thin film of barium strontium titanate (BST); and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: May 6, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Duck-Hwa Hong
  • Patent number: 7368298
    Abstract: An Ir film, an IrOx film, a Pt film, a PtO film and a Pt film are formed, and thereafter a PLZT film is formed. Then, heat treatment at 600° C. or lower is performed by the RTA method in an atmosphere containing Ar and O2 to thereby crystallize the PLZT film. Subsequently, an IrOx film and an IrO2 film are formed. Then, these films are patterned at once. Thereafter, an alumina film is formed as a protective film. Subsequently, heat treatment at 650° C. for 60 minutes in an oxygen atmosphere is performed as recovery annealing. Note that no heat treatment is performed from the crystallization of the PLZT film to the recovery annealing.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: May 6, 2008
    Assignee: Fujitsu Limited
    Inventor: Wensheng Wang
  • Patent number: 7368343
    Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Patent number: 7365011
    Abstract: A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Adrien R. Lavoie, Arnel Fajardo, Valery M. Dubin
  • Patent number: 7364964
    Abstract: A highly reliable semiconductor device having a ferroelectric capacitor structure by sufficiently preventing the H2 attack without damaging the function of an interlayer insulating film covering interconnections and the like to obtain a high capacitor performance. The position of a semiconductor substrate mounted on and secured to a substrate support plate in an HDP-CVD system is adjusted in the vertical direction, whereby a second HDP-CVD oxide film is deposited so that voids are formed between aluminum interconnections at lower positions than the height of the aluminum interconnections.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Kazutoshi Izumi
  • Patent number: 7361608
    Abstract: A method for plasma processing a high-k layer includes providing a substrate having a high-k layer formed thereon, on a substrate holder in a process chamber, and creating a plasma in the process chamber to thereby expose the high-k layer to the plasma. RF power is applied to the substrate holder, the RF power having a characteristic to reduce a rate of formation of an oxide interface layer located between the substrate and the high-k layer. A device includes a feature etched in a high-k layer. The etch profile of the device can include a reduced bird's beak, and a surface of the substrate in an etched region can be substantially coplanar with a substrate under a non-etched area.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 22, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Ko, Annie Xia, Lee Chen
  • Patent number: 7361549
    Abstract: The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench structures (105) are formed perpendicular to the surface of the driving unit (100). Deposition of a seed layer (106) on side walls (105a) of the trench structures (105) allows a crystallization agent (107) which has filled the trench structures (105), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: April 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Rainer Bruchhaus, Martin Gutsche
  • Publication number: 20080087945
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or more monolayers. Metal electrodes may be disposed on a dielectric containing a silicon lanthanide oxynitride film.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 17, 2008
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Publication number: 20080087930
    Abstract: A capacitor includes a first electrode having a conductive pattern and an anti-oxidation pattern contacting the conductive pattern and a second electrode overlapping the first electrode. The capacitor further includes a capacitor dielectric layer disposed between the first and second electrodes, and having a blanket dielectric layer and a partial dielectric layer. The blanket dielectric layer is disposed between the first and second electrodes, and the partial dielectric layer is disposed between the blanket dielectric layer and the anti-oxidation pattern.
    Type: Application
    Filed: April 11, 2007
    Publication date: April 17, 2008
    Inventors: Jong-Cheol Lee, Ki-Vin Im, Hoon-Sang Choi, Eun-Ae Chung, Sang-Yeol Kang
  • Publication number: 20080076191
    Abstract: A ferroelectric capacitor stack is formed over a metal-dielectric interconnect layer. After forming the interconnect layer, the surface of the interconnect layer is treated with gas cluster ion beam (GCIB) processing. Prior to this processing, the surface typically includes metal recesses. The GCIB processing smoothes these recesses and provides a more level surface on which to form the ferroelectric capacitor stack. When the ferroelectric capacitor stack is formed on this leveled surface, leakage is reduced and yields increased as compared to the case where GCIB processing is not used.
    Type: Application
    Filed: September 22, 2006
    Publication date: March 27, 2008
    Inventors: Lindsey Hall, Sanjeev Aggarwal, Satyavolu Srinivas Papa Rao
  • Patent number: 7344939
    Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Jarrod Randall Eliason, Glen R. Fox, Richard A. Bailey
  • Patent number: 7344941
    Abstract: Methods of manufacturing a metal-insulator-metal capacitor are provided.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 18, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jung-Gyu Kim
  • Publication number: 20080061345
    Abstract: The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug 46 buried in the insulation layer, a capacitor formed above the insulation layer and the conductor plug and including a lower electrode formed of the first conduction film and the second conduction film formed over the first conduction film and formed of Pt, Pt alloy, Pd or Pd alloy, a capacitor dielectric film formed of a ferroelectric or a high dielectric formed over the lower electrode and an upper electrode formed over the capacitor dielectric film, the capacitor dielectric film contains a first element of Pb or Bi, and the concentration peak of the first element diffused in the lower electrode from the capacitor dielectric film positioning in the interface between the first conduction film and the second conduction film.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 13, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Wensheng Wang
  • Patent number: 7341907
    Abstract: Methods for depositing hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are provided. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers are deposited in single substrate chemical vapor deposition chambers. The hemispherical grained silicon layers and nanocrystalline grain-sized polysilicon layers may be used as electrode layers in semiconductor devices. In one aspect, a two step deposition process is provided to form a nanocrystalline grain-sized polysilicon layer with a reduced roughness.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: March 11, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Ming Li, Kevin Cunningham, Sheeba Panayil, Guangcai Xing, R. Suryanarayanan Iyer
  • Patent number: 7341908
    Abstract: Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: March 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-seok Suh, Seung-man Choi, Hong-jae Shin, Young-jin Wee
  • Publication number: 20080054330
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 7338814
    Abstract: A method for fabricating a ferroelectric capacitive element of this invention includes the steps of forming a lower electrode made of a first conductive film on a substrate; forming a first ferroelectric film including bismuth in a first concentration on the lower electrode; forming a second ferroelectric film including bismuth in a second concentration on the first ferroelectric film; performing annealing after forming the first ferroelectric film and the second ferroelectric film; and forming an upper electrode made of a second conductive film on the second ferroelectric film after the annealing. The first conductive film is a metal film more easily etched than a platinum film, and the second ferroelectric film is formed in such a manner that the second concentration is lower than the first concentration before the annealing.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: March 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshitaka Tatsunari
  • Patent number: 7338854
    Abstract: A method for manufacturing a multilayer ceramic capacitor, in which internal electrodes printed on each of a plurality of dielectric sheets have reduced thicknesses using an absorption member, thereby allowing the multilayer ceramic capacitor to have a high capacity and be minimized. The method includes printing the internal electrodes on each of the dielectric sheets, and stacking the dielectric sheets, wherein the internal electrodes formed on each of the dielectric sheets have a reduced thickness by causing an absorptive member to contact the surface of each of the dielectric sheets provided with the internal electrodes and then separating the absorptive member from the surface so that portions of the internal electrodes having a designated thickness are eliminated, and the dielectric sheets provided with the internal electrodes having the reduced thickness are stacked to form a chip element.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 4, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ho Sung Choo, Seung Hyun Ra, Yong Suk Kim, Jung Woo Lee, Hyo Soon Shin, Hyoung Ho Kim