Abstract: A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor formed above a magnetic tunnel junction formed on the diode. The diode and the first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.

Abstract: An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: The preferred embodiment provides an integrated circuit capacitor that achieves a high capacitance by using an inversion layer in the substrate as the plate counter electrode for the capacitor. The inversion layer is created by forming a trench capacitor in a lightly doped substrate. With a sufficient workfunction difference between the storage node material and the isolation band the surface of the lightly doped substrate inverts, with the inversion charge being supplied by the isolation band. This inversion layer serves as the plate counter electrode for the capacitor.

Abstract: A trench capacitor, in accordance with the present invention, includes a trench formed in a substrate. The trench has a buried plate formed adjacent to a lower portion of the trench. A dielectric collar is formed along vertical sidewalls of the trench. A node diffusion region is formed adjacent to the trench for connecting to a storage node in the trench. A dopant region is formed laterally outward from the trench and adjacent to the collar, and the dopant region includes a profile having a lower portion extending further laterally outward from the trench than an upper portion of the profile wherein operation of a parasitic transistor formed adjacent to the trench between the node diffusion and the buried plate is disrupted by the dopant region. Methods for forming the dopant region are also disclosed and claimed.

Abstract: Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in the forming memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/ EDRAM arrays having a gate conductor guard ring and/or local interconnections are also provided.

Abstract: Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

Abstract: The present invention provides a method for making the bottom electrode of a buried capacitor, which is characterized by protecting the non-bottom electrode region with a LPD oxide layer to prevent the impurities within the doped Si glass remaining in non-bottom electrode region from driving into the substrate during annealing, thus non-desired diffusing region connecting to the bottom electrode will be generated. Consequently, the leakage current existing in conventional buried capacitor will be effectively reduced according to the method of this present invention.

Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more.

Abstract: A method and structure for an integrated circuit chip which includes forming a storage capacitor in a vertical opening in a horizontal substrate, forming a conductive strap laterally extending from the vertical opening and forming a transistor having a channel region extending along a vertical surface, the vertical surface lying outside of and being laterally displaced from the vertical opening, the transistor being electrically connected to the storage capacitor by an outdiffusion of the conductive strap.

Abstract: A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.

Abstract: The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention.

Abstract: The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

Abstract: A method of fabricating a trench cell capacitor can be used in the formation of a DRAM cell. In one embodiment, a trench is formed within a semiconductor substrate. The trench is lined with a dielectric layer, e.g., an ONO layer. After lining the trench, a collar is formed in an upper portion of the trench by forming an oxide layer in the upper portion. A nitride layer on the oxide layer. The trench is then filled with semiconductor material. For example, a semiconductor region can be epitaxially grown to fill the trench.

Abstract: The present invention provides a method for fabricating a trench capacitor, in particular for use in a semiconductor memory cell (100), with an insulation collar (168′; 168″), having the following steps: provision of a substrate (101); formation of a trench (108) in the substrate (101); provision of a first layer (177) on the trench wall; provision of a second layer (178) on the first layer (177) on the trench wall; filling of the trench (108) with a first filling material (152); removal of the first filling material (152) from the upper region of the trench (108) in order to define a collar region; removal of the second layer (178) from the upper region of the trench (108); removal of the first filling material (152) from the lower region of the trench (108); removal of the first layer (177) from the upper region of the trench (108); local oxidation of the upper region of the trench (108) in order to produce the insulation collar (168′; 168″); removal of the first and second layers (1

Abstract: A method of manufacturing a capacitor of a semiconductor device, according to the present invention comprises the steps of heat-treating a Ta2O5 film formed on a metal or metal oxide electrode corresponding to a lower electrode of the capacitor at a temperature lower than a temperature at which the Ta2O5 film is crystallized, and thereafter heat-treating the Ta2O5 film at a temperature higher than or equal to the crystallizing temperature of the Ta2O5 film.

Abstract: A method for forming a contact of a semiconductor device is described, in which a conductive layer pattern is electrically connected to a semiconductor substrate and an interlayer insulating film is formed on the semiconductor substrate including the conductive layer pattern. The interlayer insulating film is etched down to a top surface of the conductive layer pattern using a contact formation mask to form a contact hole. The conductive layer pattern is isotropically etched through the contact hole so as to extend the surface area of the exposed conductive layer pattern and the contact hole is filled with conductive material, forming a contact plug electrically connected to the conductive layer pattern. It is therefore possible to extend the contact area between the conductive layer pattern and a contact plug. As a result, the contact resistance is reduced.

Abstract: A method and structure for manufacturing an integrated circuit device includes forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening, forming an isolation opening in the substrate using the second spacers to align the isolation opening, filling the isolation opening with an isolation material, removing the first spacers and a portion of the second spacers to form a step in the gate opening, (wherein the second spacers comprise at least one conductive strap electrically connected to the storage device) forming a first diffusion region in the substrate adjacent the conductive strap, forming a gate insulator layer over the substrate and the step, forming a gate conductor over a portion of the gate insulator layer above the step, forming a second diffusion region in th

Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

Abstract: A method of manufacturing a capacitor is provided where at least a portion of a silicon surface is amorphized. The amorphized silicon surface is then subjected to an annealing process to form hemispherical silicon grains (HSG) from the amorphized portion of the silicon surface to form at least a portion of a first electrode of the capacitor. A capacitor dielectric is then formed over the hemispherical silicon grains. A second electrode is then formed over the capacitor dielectric.

Abstract: A method of fabricating a self-aligned node contact window starts by forming a bit line on a substrate having a transistor, in which the transistor includes a first source/drain region and a second source/drain region. The bit line is coupled electrically with the first source/drain region of the transistor and there is a cap layer and a first conductive layer formed on the bit line. An insulating layer that is conformal with the bit line, the cap layer and the first conductive layer is formed to serve as an etching stop layer for subsequently forming a conductive spacer. A conductive spacer is formed on the insulating layer of the sidewall of the bit line, the cap layer and the first conductive layer. Using the first conductive layer and the conductive spacer as a mask, an etching process is performed to form a self-aligned node contact window and the second source/drain is thus exposed.

Abstract: A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove being in contact with at least one side face of the impurity-doped region, a conductive layer buried in the trench, and a contact region formed on at least one side face of the impurity-doped region, for connecting the impurity-doped region and the conductive layer. Thus, the area occupied by a unit cell is reduced and integration density can be increased accordingly.

Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

Abstract: A semiconductor structure uses a shallow trench isolation (STI) region to realize a capacitor trench of a reduced size. Consistent with one embodiment of fabricating a memory cell, the invention includes selectively removing portions of a substrate using a patterned mask to form a capacitor trench and an isolation trench at least partially around the capacitor trench. An oxide is formed in the isolation trench and the capacitor trench and the oxide so selectively removed in the capacitor trench. Portions of the substrate defining the base and sidewalls of the capacitor trench are then doped and a capacitor dielectric is formed in the capacitor trench, leaving a portion of the trench unfilled. A polysilicon layer is formed it the unfilled portion of the capacitor trench and over the capacitor dielectric to form a plate of the storage capacitor.

Abstract: Reduced variations in buried layer across the chip is provided. The reduction in variation is achieved by defining the top surface of the buried layer and then the lower surface of the buried layer. This results in improved control buried strap variations, thereby improving performance of the IC.

Abstract: A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide.

Abstract: A method of forming a shallow trench isolation structure is disclosed. A dielectric layer deposited by chemical vapor deposition is used as a sacrificial layer instead of conventional sacrificial oxide layer formed by thermal oxidation. Therefore, the oxide in the trench is further protected and less damaged.

Abstract: A method for forming a semiconductor trench capacitor cell having a buried strap uses a substrate having a trench with a conductor separated from walls of the trench by a dielectric material. A portion of the dielectric material to a level below a top surface of the conductor is removed and at least a portion of the space thus formed is filled with a diffusible material. The buried strap is formed by annealing the conductor, the wall and the diffusible material so that conductive elements from the wall and the conductor diffuse into the diffusible material.

Abstract: A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal silicon seeded from the substrate is grown for the transfer device. At least a portion of the node diffusion is located in single crystal epitaxial silicon extending over the trench. The process eliminates the need for a separate strap masking step.

Abstract: A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulator layer is formed outwardly from the roughened, conformal layer of semiconductor material. A polycrystalline semiconductor plate is formed outwardly from the insulator layer in the trench.

Abstract: A method for forming a trench capacitor in a substrate, including a buried plate of the trench capacitor, is disclosed. The method includes forming a trench within the substrate. The trench has a trench interior surface. The method further includes forming an oxide collar within the trench. The oxide collar covers a first portion of the trench interior surface, leaving a second portion of the trench interior surface uncovered with the oxide collar. There is also included doping the second portion of the trench interior surface with a first dopant using a plasma-enhanced doping process. The plasma-enhanced doping process being configured to cause the first dopant to diffuse into the second portion substantially without depositing an additional layer on the trench interior surface. Additionally, there is included driving the first dopant into the substrate using a high temperature process to form the buried plate.

Abstract: A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.

Abstract: A method for forming a capacitor in a semiconductor body is provided. The method includes the step of forming a trench in a portion of a surface of the semiconductor body. The trench having sidewalls and a bottom. A doped film is deposited over the surface of the semiconductor body. Portions of the doped film are deposited over the sidewalls and bottom of the trench. The semiconductor body is heated and the doped film to produce a liquid phase interface region therebetween while diffusing dopant in the doped film into a region of the semiconductor body. The interface region is cooled to return such interface region to a solid phase. The doped film and the interface region are removed from the semiconductor body while leaving the doped region in the semiconductor body. A dielectric film is deposited over the doped region of the semiconductor body.

Abstract: The method sequence results in a conductive connection between two zones of a first conductivity type. In particular, one of the zones is a source/drain zone of a transistor. Instead of the conventional additional nitride layer, the connection is produced by implanting directly into the third insulation layer, which is present anyway, and by utilizing the fact that the third insulation layer forms the lateral spacers on the gatestack disposed on the region of the second conductivity type.

Abstract: A silicon oxide layer is formed on the wafer to act as a pad layer. A silicon nitride layer is then formed on the silicon oxide layer to have a thickness approximate 1500-2000 angstroms. At least one trench is then created in the wafer. Then, an ion implantation process is performed with at least one titled angle to dope ions into the surface of the trenches. A LPD-oxide is selectively deposited in the trench. Then, a polysilicon layer is formed on the LPD-oxide and on the surface of the silicon nitride layer. Next, the polysilicon layer is etched to generate polysilicon side-wall spacers. The LPD-oxide is etched using the polysilicon side-wall spacers and the silicon nitride layer as an etching mask. The polysilicon side-wall spacers are then removed. A first conductive layer is formed on the silicon nitride layer, and refilled into the first trenches. The first conductive layer is then etched to at least to expose the LPD-oxide. The LPD-oxide is removed.

Abstract: A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.

Abstract: A dynamic random access memory (DRAM) cell is formed with a buried strap which is routed through an isolation trench. This structure frees space in the transfer gate such that the location of the buried strap is not a limiting factor for decreasing the size of DRAM cells.

Abstract: A semiconductor device includes (a) a first conductivity type semiconductor substrate having a plurality of trenches formed therein, the trenches defining a plurality of device regions between adjacent trenches, (b) a second conductivity type diffusion layer formed at least around an outer surface of each of the device regions, (c) an insulating film formed on the inner surface of each of the trenches to cover a part of the second conductivity type diffusion layer therewith, (d) a plate electrode formed within each of the trenches, (e) a gate electrode formed above the second conductivity type diffusion layer and (f) a gate insulating film interposed between the gate electrode and the second conductivity type diffusion layer to isolate the gate electrode from the second conductivity type diffusion layer. This semiconductor device eliminates the need for the second conductivity type diffusion layer to serve as a capacitor electrode in contact with a switching transistor.

Abstract: Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.

Abstract: A silicon oxide, a silicon nitride layer are patterned to define trenches region. Then, a recess portion is formed in the substrate. Subsequently, a second silicon oxide, a second silicon nitride layer are formed on the recess portion. Then, a glass layer is formed on the second silicon nitride layer and refilled into the recess portion. An etching step is performed to etch the glass layer, the second silicon nitride layer and the second silicon oxide layer to the surface of the substrate. Trenches are then created in the substrate. Then, ion implantation processes are performed to dope ions into the trenches. A dielectric layer is then deposited along the surface of the trenches and on the surface of the second silicon oxide layer, the second silicon nitride layer. A polysilicon layer is deposited on the dielectric layer and refilled into the trenches. Then, an etching back is used to etch the polysilicon layer to form a field plate.

Abstract: A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium silicide bridge) is described. It is based on an isolation trench having a top portion with vertical sides and a lower portion with sloping sides. With the filled trench in place, along with a polysilicon gate and gate oxide, the thinner, lightly doped, N type layer is formed using ion implantation. Spacers are then formed on the gate but, prior to the second ion implant step, a few hundred Angstroms of silicon is selectively removed from the surface. This causes the trench filler material to extend above the wafer surface and the spacers to extend above the gate. A deeper, more strongly N-type, layer is then formed in the usual way, followed by the standard SALICIDE process for making contact to source, gate, and drain.

Abstract: A method for forming a contact is disclosed. A buried impurity region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type. First and second well regions of a first and second conductivity types, respectively, are also formed in the semiconductor substrate. The second well region overlaps the first well region and contacts and surrounds the buried impurity region. A surface impurity concentration of the first well region is greater than a surface impurity concentration of the second well region. A contact to the second well region is formed.

Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.