Stacked Capacitor Patents (Class 438/253)
  • Patent number: 10665391
    Abstract: Disclosed herein is an apparatus that includes a bottom electrode, a top electrode, and a dielectric film disposed between the bottom electrode and the top electrode. The bottom electrode includes TiN having more (111) crystal orientation than (200) crystal orientation.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kei Hirata
  • Patent number: 10665569
    Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Chih-Chieh Yeh
  • Patent number: 10651198
    Abstract: A semiconductor device includes lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate, upper gate electrodes on the lower gate electrodes in the first direction, and channel structures extending through the lower and upper gate electrodes in the first direction. Each channel structure includes a lower channel structure, an upper channel structure, and a landing pad interconnecting the lower and upper channel structures. The first channel structure includes a first landing pad having a horizontal width substantially greater than that of the lower channel structure of the first channel structure at a first vertical level. The second channel structure located closest to the first channel structure includes a second landing pad having a horizontal width substantially greater than that of the lower channel structure of the second channel structure at a second vertical level lower than the first vertical level.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-cheon Baek, Boh-chang Kim
  • Patent number: 10644169
    Abstract: A method of manufacturing a varactor transistor includes providing a semiconductor structure including a semiconductor fin and an initial insulator layer on the semiconductor fin, and forming a plurality of gate structures spaced apart from each other and surrounding a portion of the semiconductor fin. The gate structures include a first dummy gate structure on a first edge of the semiconductor fin, a second dummy gate structure on a second edge of the semiconductor fin, and a first gate structure between the first and second dummy gate structures and spaced apart from the first and second dummy gate structures. The first and second dummy gate structures and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 5, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10615112
    Abstract: A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim
  • Patent number: 10614956
    Abstract: A multilayer capacitor includes a body including dielectric layers and a plurality of first and second internal electrodes having an average thickness less than 1 ?m; and first and second external electrodes each including first and second conductive layers including first and second head portions and first and second band portions, and first and second conductive resin layers each covering the first and second conductive layers. An average thickness of the dielectric layers may be greater than the average thickness of the first and second internal electrodes, and portions of the first and second internal electrodes overlapping an end of the first or second band portion in a width direction of the body may be formed as first and second extending portions having a width relatively greater than those of other portions of the first and second internal electrodes, respectively.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Do Young Jeong, Je Jung Kim, Do Yeon Kim
  • Patent number: 10593676
    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes two first gate structures and a multilayer insulating structure. The multilayer insulating structure includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially from bottom to top. The width of the second insulating layer is equal to that of the third insulating layer, and smaller than that of the first insulating layer. The width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer. The memory device includes a capacitor contact plug formed between the first gate structures. The capacitor contact plug includes a first contact element, a buffering layer, and a second contact element. The second contact element has a top surface wider than its bottom surface.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Shu-Ming Lee, Tzu-Ming Ou Yang
  • Patent number: 10546915
    Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
  • Patent number: 10535613
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • Patent number: 10529569
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10529719
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Patent number: 10461147
    Abstract: A method of fabricating a semiconductor device, the method including: forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 29, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takuo Narusawa
  • Patent number: 10403634
    Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sung-Min Hwang, Joon-Sung Lim, Gilsung Lee, Eunsuk Cho
  • Patent number: 10381432
    Abstract: A pattern is defined in a dielectric layer. The dielectric layer includes a low-k dielectric region and a high-k dielectric region. The high-k dielectric region includes a phase change material which is an alloy of tantalum and nitrogen and is a high-k insulator in a deposited state. The pattern includes a first set of features in the low-k dielectric region and a second set of features in the high-k dielectric region. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A metal layer is deposited in the first and second set of features. Thus, a set of conductive lines is formed in the low-k dielectric region and a metal insulator metal capacitor in the high-k dielectric region.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10373960
    Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daeik Kim, Semyeong Jang, Jemin Park, Yoosang Hwang
  • Patent number: 10332745
    Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Sun, Ruilong Xie, Wenhui Wang, Yulu Chen, Erik Verduijn, Zhengqing John Qi, Guoxiang Ning, Daniel J. Dechene
  • Patent number: 10297549
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 10256045
    Abstract: A capacitor that includes a porous metal base material, a first buffer layer formed by an atomic layer deposition method on the porous metal base material, a dielectric layer formed by an atomic layer deposition method on the first buffer layer, and an upper electrode formed on the dielectric layer.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiromasa Saeki, Noriyuki Inoue, Takeo Arakawa, Naoki Iwaji
  • Patent number: 10170625
    Abstract: Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 10158023
    Abstract: A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes: patterning a substrate to form a plurality of trenches in the substrate and at least one semiconductor fin between the trenches; forming a plurality of insulators in the trenches; forming a patterned photoresist on the insulators, wherein sidewalls of the semiconductor fin are partially covered by the patterned photoresist, and at least one area of the sidewalls is exposed by the patterned photoresist; by using the patterned photoresist as a mask, partially removing the semiconductor fin from the at least one area of the sidewalls exposed by the patterned photoresist so as to form at least one recess on the sidewalls of the semiconductor fin; removing the patterned photoresist after forming the at least one recess; and forming a gate stack to partially cover the semiconductor fin and the insulators.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Sheng Lin, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Patent number: 10128016
    Abstract: Disclosed is an EUV system element having a hydrogen diffusion barrier including a region implanted with species (e.g., ions energetic neutral atoms) of a non-hydrogen gaseous material. Also disclosed is a method of making such a component including the step of implanting species of a non-hydrogen gaseous material to form a hydrogen diffusion barrier and a method of treating an EUV system element including the step of implanting species of a non-hydrogen gaseous material to prevent hydrogen adsorption and diffusion. Also disclosed is subjecting an EUV system element to a flux of non-hydrogen gas ions to displace hydrogen ions in one or more layers of the EUV system element with the non-hydrogen gas species so that the gas ions protect the EUV system element against hydrogen damage.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 13, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Karl Robert Umstadter
  • Patent number: 10121661
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10079237
    Abstract: A semiconductor memory device may include: a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area; a plurality of bottom electrodes, on the substrate, which are in parallel with a top surface of the substrate and a first direction in parallel with a top surface of the substrate, and are arranged along a second direction intersecting the first direction; and a support structure pattern, in a flat plate shape, which connects the bottom electrodes to each other, supports the bottom electrodes onto the substrate, and includes a plurality of open areas, wherein a first profile, which is a horizontal cross-sectional profile in the edge area of the support structure pattern, has a wave shape.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-hoon Kim, Won-chul Lee
  • Patent number: 10042767
    Abstract: An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: August 7, 2018
    Assignee: SK hynix Inc.
    Inventors: Jong-Young Cho, Eung-Rim Hwang, In-Hoe Kim, Young-Min Na, Gwang-Won Lee
  • Patent number: 10008558
    Abstract: A method for fabricating an advanced metal insulator metal capacitor structure includes providing a pattern in a dielectric layer. The pattern includes a set of features in the dielectric layer. A first metal layer is deposited in the set of features in the dielectric layer. A phase change material layer is deposited over the metal layer in the set of features in the dielectric layer. The phase change material is an alloy of tantalum and nitrogen and is an insulator in a deposited state. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A second metal layer is deposited on the top surface layer of the phase change layer. In another aspect of the invention, a device is produced using the method.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10008410
    Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Chul Park, Ji Woon Im, Dai Hong Kim, Il Woo Kim, Hyun Seok Lim
  • Patent number: 9941290
    Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacaturing Co., Ltd.
    Inventor: Chih-Hung Hsieh
  • Patent number: 9793161
    Abstract: A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Veeraraghavan S. Basker
  • Patent number: 9773911
    Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are disposed in the trenches. The semiconductor fin includes a first portion embedded between the insulators; a necking portion disposed on the first portion, the necking portion being uncovered by the insulators; and a second portion disposed on the necking portion, wherein a width of the necking portion is less than a width of the first portion. The gate stack partially covers the semiconductor fin, the at least one recess and the insulators.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Sheng Lin, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Patent number: 9768070
    Abstract: Provided is a method for manufacturing a semiconductor device, which can secure a sufficient margin in a process of forming a self-aligned contact. The method includes forming a plurality of gate structures arranged in parallel on a substrate and being spaced apart from each other, each of the plurality of gate structures including a conductive layer and a capping layer formed on the conductive layer, forming a first insulation layer between each of the plurality of gate structures, recessing top portions of the plurality of gate structures, forming a block layer along a top surface of the first insulation layer and the recessed top portions of the plurality of gate structures, forming a hardmask layer on the block layer, forming a hardmask pattern on each of the plurality of gate structures by planarizing a top portion of the block layer and a top portion of the hardmask layer, and forming a second insulation layer along a top surface of the block layer and top surfaces of the hardmask patterns.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Suk Lee, Dong-Kwon Kim
  • Patent number: 9761655
    Abstract: Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Lawrence A. Clevenger, Hemanth Jagannathan, Roger A. Quon
  • Patent number: 9743861
    Abstract: A system for transitioning from a first footwear type to a second footwear type is usable with an article of footwear including a sensor system with a plurality of force sensors engaged with an article of footwear and configured to sense force exerted by a foot of a user and an electronic module configured to collect data based on force input from the sensors and to wirelessly transmit data generated by the sensor system. An electronic device includes a processor that receives the data from the electronic module, compares the data to a footstrike template corresponding to a desired footstrike pattern of a footwear transitional program, determines whether a deviation from the footstrike template exists, and generates an indication to the user when the deviation from the desired footstrike pattern is determined to exist. The desired footstrike pattern corresponds to a preferred footstrike of the second type of footwear.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: August 29, 2017
    Assignee: NIKE, Inc.
    Inventors: Anna Antonia Giedwoyn, Lee Peyton, Christopher L. Andon
  • Patent number: 9711464
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Patent number: 9679812
    Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsun Wang, Shih-Wen Liu, Fu-Kai Yang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 9660018
    Abstract: A method of fabricating a semiconductor device, including forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: May 23, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takuo Narusawa
  • Patent number: 9633986
    Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 25, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 9583498
    Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Patent number: 9559107
    Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 31, 2017
    Assignee: International Businesss Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Patent number: 9553096
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai, Xiaomeng Chen, Chen-Jong Wang
  • Patent number: 9553157
    Abstract: A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: January 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ahmet S. Ozcan, Viraj Y. Sardesai, Kathryn T. Schonenberg, Cung D. Tran
  • Patent number: 9536840
    Abstract: A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A graphene layer is a sheet like layer made of pure carbon, at least one atom thick with atoms arranged in a regular hexagonal pattern. A graphene layer may be disposed between any number of adjacent tiers in the 3DIC. In exemplary embodiments, the graphene layer provides an electromagnetic interference shield between adjacent tiers or layers in the 3DIC to reduce crosstalk between the tiers. In other exemplary embodiments, the graphene layer(s) can be disposed in the 3DIC to provide a heat sink that directs and dissipates heat to peripheral areas of the 3DIC. In some embodiments, the graphene layer(s) are configured to provide both EMI shielding and heat shielding.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: January 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Yang Du
  • Patent number: 9455402
    Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: September 27, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Yu Lin, Feng-Min Lee, Kuang-Hao Chiang, Ming-Hsiu Lee
  • Patent number: 9418998
    Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Eun Kim, Hoon Jeong, Jae-Hyun Kim, Dong-Won Lee, Jung-Gu Han, Ji-Hye Hwang
  • Patent number: 9379114
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Won Jeong, Wonchul Lee
  • Patent number: 9368494
    Abstract: A semiconductor device with neck fins comprises a substrate, a plurality of fins having a lower portion and a neck upper portion on the substrate, and insulators disposed between each fin and flush with the lower portion of the fins.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: June 14, 2016
    Assignee: NANYA TECHNOLOGY CORP.
    Inventor: Wei-Ming Liao
  • Patent number: 9346239
    Abstract: A method is used to provide a pattern of a functional material for example on a receiving element. To provide this pattern, a laser-engraveable patternable element is imagewise exposed with laser-engraving radiation. This element has a laser-engraveable layer comprising a thermoplastic elastomeric interpolymer alloy. This interpolymer alloy comprises a non-crosslinked halogenated polymer, a partially crosslinked polyolefin, and a polyester. A laser-engraved patterned element is formed that has a relief image in the laser-engraveable layer, and this relief image can be contacted with a suitable functional material that is then transferred to the receiving element to provide the desired pattern.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: May 24, 2016
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Lawrence A. Rowley, Christine Joanne Landry-Coltrain
  • Patent number: 9349736
    Abstract: The instant disclosure relates to a method for manufacturing high-strength structural stacked capacitor. The novel feature of the instant disclosure is forming a part of upper electrode layer to cover the first/outer surface of each of the lower electrode layers before removing the sacrificial layer, and forming another part of upper electrode layer to cover the second/inner surface of each of the lower electrode layers after removing the sacrificial layer. Hence, the structure strength of the lower electrode layer in all process steps has been improved.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 24, 2016
    Assignee: Inotera Memories, Inc.
    Inventors: Hai-Han Hung, Yi-Ren Lin
  • Patent number: 9337279
    Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Häberlen
  • Patent number: 9337053
    Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: May 10, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan Doebler
  • Patent number: 9331140
    Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongkyun Park, Han-Young Kim, Joon Kim, Hyun Park, Junghwan Oh, Minhee Cho