Stacked Capacitor Patents (Class 438/253)
  • Patent number: 11361895
    Abstract: The invention comprises an inverter/converter yielding high frequency harmonics and/or non-sixty Hertz output coupled to a high frequency inductor-capacitor filter apparatus. For example, an inverter/converter apparatus is provided that uses a silicon carbide transistor to output power having a carrier frequency modulated by a fundamental frequency and a set of harmonic frequencies, where the minimum carrier frequency is above that usable by an iron-steel inductor, such as greater than ten kiloHertz at fifty or more amperes. An inductor-capacitor filter, comprising an inductor having a distributed gap core material, receives power output from the inverter/converter and processes the power by passing the fundamental frequency while reducing amplitude of the harmonic frequencies.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 14, 2022
    Inventors: Hans Wennerstrom, Grant A. MacLennan, Edward Handy
  • Patent number: 11302626
    Abstract: A semiconductor memory device, and a method of manufacturing the same, includes: a gate stack structure including interlayer insulating layers and conductive patterns stacked in a first direction; a channel structure penetrating the gate stack structure; a peripheral contact plug spaced apart from the gate stack structure on a plane intersecting the channel structure, the peripheral contact plug extending in the first direction; and a capacitor spaced apart from the gate stack structure and the peripheral contact plug on the plane, the capacitor having an area wider than an area of the peripheral contact plug.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11289153
    Abstract: A memory device is disclosed, in which node contacts extend into a substrate, where they are come into electrical connection with active areas. This allows greater contact areas between the node contacts and the active areas and electrical connection of the node contacts with high ion concentration portions of the active areas. As a result, even when voids are formed in the node contacts, the node contacts can still possess desired connection performance. For node contacts allowed to contain voids, this enables them to be fabricated faster with lower difficulty, thus increasing manufacturing throughput of the memory device.
    Type: Grant
    Filed: June 20, 2021
    Date of Patent: March 29, 2022
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jianfang Wang, Peng Guo, Baoyu Li, Yuanbao Wang
  • Patent number: 11289487
    Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
  • Patent number: 11270933
    Abstract: A semiconductor device comprises a substrate including a cell array region and a peripheral circuit region that surrounds the cell array region. The cell array region includes landing pads disposed on the substrate and first bottom electrodes disposed on and connected to corresponding landing pads. The peripheral circuit region includes conductive lines disposed on the substrate, a first conductive pad disposed on and spaced apart from the conductive lines, a dielectric pattern disposed between the conductive lines and the first conductive pad, and a plurality of second bottom electrodes disposed on and connected in common to the first conductive pad. A height of each of the first bottom electrodes is greater than a height of each of the second bottom electrodes. Top surfaces of the first bottom electrodes are located at a same level as a level of top surfaces of the second bottom electrodes.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Il Han, Sunghee Han
  • Patent number: 11233058
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing an wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 25, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Chang-Hyeon Nam, Injoon Yeo
  • Patent number: 11233057
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 25, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Patent number: 11226552
    Abstract: A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hungbae Ahn, Sangoh Park, Sunggon Jung
  • Patent number: 11222896
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11211253
    Abstract: Methods and apparatuses for critical dimension (CD) control of substrate features using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include etching to form a mask pattern of features on a substrate having a width that is less than a desired width of structures to be subsequently formed by the mask pattern of features, conformally depositing a passivation layer by ALD that increases the width of the mask pattern of features to the desired width, and etching a layer of the substrate to a desired depth to form the plurality of structures having the desired width.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 28, 2021
    Assignee: Lam Research Corportation
    Inventors: Xiang Zhou, Yoshie Kimura, Duming Zhang, Chen Xu, Ganesh Upadhyaya, Mitchell Brooks
  • Patent number: 11192782
    Abstract: Provided are a method for preparing a silicon wafer with a rough surface and a silicon wafer, for solving the problem that a viscous force is likely to be generated when a smooth surface of the silicon wafer approaches another film layer. The method includes: depositing a porous oxide film layer on a surface of the first silicon planar layer that has been subjected to planar planarization, and then etching the porous oxide film layer by XeF2 vapor etching, during which XeF2 gas passes through the porous oxide film layer to etch the first silicon planar layer in an irregular way. Therefore, the first silicon planar layer has a greater surface roughness. When the silicon wafer approaches to another film layer, the viscous force generated therebetween is reduced, improving the sensitivity of the MEMS device and reducing the probability of out-of-work MEMS devices.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: December 7, 2021
    Assignee: AAC ACOUSTIC TECHNOLOGIES (SHENZHEN) CO., LTD.
    Inventors: Wooicheang Goh, Lieng Loo, Kahkeen Lai
  • Patent number: 11189570
    Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-a Kim, Yong-kwan Kim, Se-keun Park, Ho-in Ryu
  • Patent number: 11164937
    Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, You-Hua Chou, Hsing-Yuan Huang, Cheng-Yu Hung
  • Patent number: 11112922
    Abstract: A capacitive touch sensor comprises a plurality of electrodes on a substrate, and a position of a finger touching the sensor is determined by monitoring output signal changes caused by changes in capacitance caused by the present of the finger over or near the electrodes. The disclosure provides a capacitive touch sensor apparatus comprising a substrate and a plurality of touch sensor electrodes arranged on the substrate. Each of the electrodes comprises a respective primary electrode strip and a respective one or more electrode strip branches extending from the primary electrode strip.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 7, 2021
    Assignee: 1004335 ONTARIO INC. CARRYING ON BUSINESS AS A D METRO
    Inventors: Robert Donald McCulloch, Guy Michael Amyon Farquharson Duxbury, Albert M. David, Gueorgui Pavlov
  • Patent number: 11092567
    Abstract: Embodiments of the invention are directed to a sensor that includes a sensing circuit and a probe communicatively coupled to the sensing circuit. The probe includes a three-dimensional (3D) sensing surface coated with a recognition element and configured to, based at least in part on the 3D sensing surface interacting with a predetermined material, generate a first measurement. In some embodiments, the 3D sensing surface is shaped as a pyramid, a cone, or a cylinder to increase the sensing surface area over a two-dimensional (2D) sensing surface. In some embodiments, the 3D sensing surface facilitates penetration of the 3D sensing surface through the wall of the biological cell.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Eugene J. O'Sullivan, Sufi Zafar
  • Patent number: 11031553
    Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: June 8, 2021
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli
  • Patent number: 10978512
    Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae-Yeon Lee
  • Patent number: 10971496
    Abstract: A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Hwan Kim, Ji Young Kim, Bong Soo Kim
  • Patent number: 10964703
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose an etch stop layer in the preliminary pattern; forming a dielectric layer on a sidewall of the opening; performing a first etching process to penetrate the etching stop layer and form a hole; performing a second etching process to expand a portion of the hole in the substrate; removing the dielectric layer; and depositing a conductive preliminary pattern on the sidewall of the opening and in the hole.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 30, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Chang-Hyeon Nam, Injoon Yeo
  • Patent number: 10872783
    Abstract: The invention relates to a method for structuring a nitride layer (2), comprising the following steps: A) providing a nitride layer (2) formed with silicon nitride of a first type, B) defining regions (40) of said nitride layer (2) to be transformed, and C) inserting the nitride layer (2) into a transformation chamber for the duration of a transformation period, said transformation period being selected such that—at least 80% of the nitride layer (2) regions (40) to be transformed are transformed into oxide regions (41) formed with silicon oxide, and—remaining nitride layer (2) regions (21) remain at least 80% untransformed.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 22, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Andreas Rueckerl, Roland Zeisel, Simeon Katz
  • Patent number: 10861861
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Patent number: 10847378
    Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
  • Patent number: 10840193
    Abstract: A semiconductor device includes a semiconductor substrate 101 containing a circuit region CR and a chip outer peripheral region PR provided adjacent thereto, a first interlayer-insulating film 102 provided on the semiconductor substrate 101, a second interlayer-insulating film 104 provided on the first interlayer-insulating film 102, a first step ST1 provided between the semiconductor substrate 101 and the first interlayer-insulating film 102 so that the chip outer peripheral region PR side is lower than the circuit region CR side in the chip outer peripheral region PR, and a second step ST2 located on the circuit region CR side relative to the first step ST1 and provided in the second interlayer-insulating film 104 in the chip outer peripheral region PR.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 17, 2020
    Assignee: ABLIC INC.
    Inventor: Hiroyuki Utsunomiya
  • Patent number: 10797056
    Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-A Kim, Yong-Kwan Kim, Se-Keun Park, Joo-Young Lee, Cha-Won Koh, Yeong-Cheol Lee
  • Patent number: 10770593
    Abstract: Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros, Matthew V. Metz, Anand S. Murthy, Chandra S. Mohapatra
  • Patent number: 10756164
    Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 25, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10707314
    Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seje Takaki, Jongsun Sel, Hisakazu Otoi, Chao Feng Yeh
  • Patent number: 10693019
    Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
  • Patent number: 10685969
    Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure includes a first work function layer with a first thickness. The ROM device structure includes an isolation structure formed over the substrate, and the isolation structure is adjacent to the first gate structure. The isolation structure includes a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness. The ROM device structure also includes a first contact structure formed over the substrate, and the first contact structure is between the first gate structure and the isolation structure.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Hung Hsieh
  • Patent number: 10665569
    Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Chih-Chieh Yeh
  • Patent number: 10665391
    Abstract: Disclosed herein is an apparatus that includes a bottom electrode, a top electrode, and a dielectric film disposed between the bottom electrode and the top electrode. The bottom electrode includes TiN having more (111) crystal orientation than (200) crystal orientation.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kei Hirata
  • Patent number: 10651198
    Abstract: A semiconductor device includes lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate, upper gate electrodes on the lower gate electrodes in the first direction, and channel structures extending through the lower and upper gate electrodes in the first direction. Each channel structure includes a lower channel structure, an upper channel structure, and a landing pad interconnecting the lower and upper channel structures. The first channel structure includes a first landing pad having a horizontal width substantially greater than that of the lower channel structure of the first channel structure at a first vertical level. The second channel structure located closest to the first channel structure includes a second landing pad having a horizontal width substantially greater than that of the lower channel structure of the second channel structure at a second vertical level lower than the first vertical level.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-cheon Baek, Boh-chang Kim
  • Patent number: 10644169
    Abstract: A method of manufacturing a varactor transistor includes providing a semiconductor structure including a semiconductor fin and an initial insulator layer on the semiconductor fin, and forming a plurality of gate structures spaced apart from each other and surrounding a portion of the semiconductor fin. The gate structures include a first dummy gate structure on a first edge of the semiconductor fin, a second dummy gate structure on a second edge of the semiconductor fin, and a first gate structure between the first and second dummy gate structures and spaced apart from the first and second dummy gate structures. The first and second dummy gate structures and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 5, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10614956
    Abstract: A multilayer capacitor includes a body including dielectric layers and a plurality of first and second internal electrodes having an average thickness less than 1 ?m; and first and second external electrodes each including first and second conductive layers including first and second head portions and first and second band portions, and first and second conductive resin layers each covering the first and second conductive layers. An average thickness of the dielectric layers may be greater than the average thickness of the first and second internal electrodes, and portions of the first and second internal electrodes overlapping an end of the first or second band portion in a width direction of the body may be formed as first and second extending portions having a width relatively greater than those of other portions of the first and second internal electrodes, respectively.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Do Young Jeong, Je Jung Kim, Do Yeon Kim
  • Patent number: 10615112
    Abstract: A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim
  • Patent number: 10593676
    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes two first gate structures and a multilayer insulating structure. The multilayer insulating structure includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially from bottom to top. The width of the second insulating layer is equal to that of the third insulating layer, and smaller than that of the first insulating layer. The width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer. The memory device includes a capacitor contact plug formed between the first gate structures. The capacitor contact plug includes a first contact element, a buffering layer, and a second contact element. The second contact element has a top surface wider than its bottom surface.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Shu-Ming Lee, Tzu-Ming Ou Yang
  • Patent number: 10546915
    Abstract: A buried metal-insulator-metal (MIM) capacitor with landing pads is formed between first and second semiconductor substrates. The landing pads provide increased area for contacting which may decrease the contact resistors of the capacitor. The area of the buried MIM capacitor can be varied to provide a tailored capacitance. The buried MIM capacitor is thermally stable since the MIM capacitor includes refractory metal or metal alloy layers as the capacitor plates.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten, Joshua Rubin
  • Patent number: 10535613
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • Patent number: 10529719
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Patent number: 10529569
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Patent number: 10461147
    Abstract: A method of fabricating a semiconductor device, the method including: forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 29, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Takuo Narusawa
  • Patent number: 10403634
    Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sung-Min Hwang, Joon-Sung Lim, Gilsung Lee, Eunsuk Cho
  • Patent number: 10381432
    Abstract: A pattern is defined in a dielectric layer. The dielectric layer includes a low-k dielectric region and a high-k dielectric region. The high-k dielectric region includes a phase change material which is an alloy of tantalum and nitrogen and is a high-k insulator in a deposited state. The pattern includes a first set of features in the low-k dielectric region and a second set of features in the high-k dielectric region. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A metal layer is deposited in the first and second set of features. Thus, a set of conductive lines is formed in the low-k dielectric region and a metal insulator metal capacitor in the high-k dielectric region.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10373960
    Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daeik Kim, Semyeong Jang, Jemin Park, Yoosang Hwang
  • Patent number: 10332745
    Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Sun, Ruilong Xie, Wenhui Wang, Yulu Chen, Erik Verduijn, Zhengqing John Qi, Guoxiang Ning, Daniel J. Dechene
  • Patent number: 10297549
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bernhard Sell, Oleg Golonzka
  • Patent number: 10256045
    Abstract: A capacitor that includes a porous metal base material, a first buffer layer formed by an atomic layer deposition method on the porous metal base material, a dielectric layer formed by an atomic layer deposition method on the first buffer layer, and an upper electrode formed on the dielectric layer.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 9, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiromasa Saeki, Noriyuki Inoue, Takeo Arakawa, Naoki Iwaji
  • Patent number: 10170625
    Abstract: Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 1, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 10158023
    Abstract: A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes: patterning a substrate to form a plurality of trenches in the substrate and at least one semiconductor fin between the trenches; forming a plurality of insulators in the trenches; forming a patterned photoresist on the insulators, wherein sidewalls of the semiconductor fin are partially covered by the patterned photoresist, and at least one area of the sidewalls is exposed by the patterned photoresist; by using the patterned photoresist as a mask, partially removing the semiconductor fin from the at least one area of the sidewalls exposed by the patterned photoresist so as to form at least one recess on the sidewalls of the semiconductor fin; removing the patterned photoresist after forming the at least one recess; and forming a gate stack to partially cover the semiconductor fin and the insulators.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Sheng Lin, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Patent number: 10128016
    Abstract: Disclosed is an EUV system element having a hydrogen diffusion barrier including a region implanted with species (e.g., ions energetic neutral atoms) of a non-hydrogen gaseous material. Also disclosed is a method of making such a component including the step of implanting species of a non-hydrogen gaseous material to form a hydrogen diffusion barrier and a method of treating an EUV system element including the step of implanting species of a non-hydrogen gaseous material to prevent hydrogen adsorption and diffusion. Also disclosed is subjecting an EUV system element to a flux of non-hydrogen gas ions to displace hydrogen ions in one or more layers of the EUV system element with the non-hydrogen gas species so that the gas ions protect the EUV system element against hydrogen damage.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 13, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Karl Robert Umstadter