Abstract: A method of fabricating a semiconductor device, the method including: forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.

Abstract: A semiconductor memory device includes a cell array region and a peripheral circuit region. The cell array region includes an electrode structure including a plurality of electrodes sequentially stacked on a body conductive layer, and vertical structures penetrating the electrode structure so as to be connected to the body conductive layer. The peripheral circuit region includes a remaining substrate on the body conductive layer. The remaining substrate includes a buried insulating layer, and a peripheral active layer that is provided on the buried insulating layer and is substantially single-crystalline.

Abstract: A pattern is defined in a dielectric layer. The dielectric layer includes a low-k dielectric region and a high-k dielectric region. The high-k dielectric region includes a phase change material which is an alloy of tantalum and nitrogen and is a high-k insulator in a deposited state. The pattern includes a first set of features in the low-k dielectric region and a second set of features in the high-k dielectric region. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A metal layer is deposited in the first and second set of features. Thus, a set of conductive lines is formed in the low-k dielectric region and a metal insulator metal capacitor in the high-k dielectric region.

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: A capacitor that includes a porous metal base material, a first buffer layer formed by an atomic layer deposition method on the porous metal base material, a dielectric layer formed by an atomic layer deposition method on the first buffer layer, and an upper electrode formed on the dielectric layer.

Abstract: Methods of forming a compact FinFET OTP/MTP cell and a compact FDSOI OTP/MTP cell and resulting devices are provided. Embodiments include providing a substrate having a BOX layer; forming fins on the BOX layer with a gap in between; forming first and second gates, laterally separated, over and perpendicular to the fins; forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of a fin or both fins; forming a S/D region in each of the fins adjacent to the first and second gates, respectively, remote from the at least one third gate; utilizing each of the first and second gates as a WL; utilizing each third gate as a SL or connecting a SL to the S/D region; and connecting a BL to the S/D region or the at least one third gate.

Abstract: A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes: patterning a substrate to form a plurality of trenches in the substrate and at least one semiconductor fin between the trenches; forming a plurality of insulators in the trenches; forming a patterned photoresist on the insulators, wherein sidewalls of the semiconductor fin are partially covered by the patterned photoresist, and at least one area of the sidewalls is exposed by the patterned photoresist; by using the patterned photoresist as a mask, partially removing the semiconductor fin from the at least one area of the sidewalls exposed by the patterned photoresist so as to form at least one recess on the sidewalls of the semiconductor fin; removing the patterned photoresist after forming the at least one recess; and forming a gate stack to partially cover the semiconductor fin and the insulators.

Abstract: Disclosed is an EUV system element having a hydrogen diffusion barrier including a region implanted with species (e.g., ions energetic neutral atoms) of a non-hydrogen gaseous material. Also disclosed is a method of making such a component including the step of implanting species of a non-hydrogen gaseous material to form a hydrogen diffusion barrier and a method of treating an EUV system element including the step of implanting species of a non-hydrogen gaseous material to prevent hydrogen adsorption and diffusion. Also disclosed is subjecting an EUV system element to a flux of non-hydrogen gas ions to displace hydrogen ions in one or more layers of the EUV system element with the non-hydrogen gas species so that the gas ions protect the EUV system element against hydrogen damage.

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Abstract: A semiconductor memory device may include: a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area; a plurality of bottom electrodes, on the substrate, which are in parallel with a top surface of the substrate and a first direction in parallel with a top surface of the substrate, and are arranged along a second direction intersecting the first direction; and a support structure pattern, in a flat plate shape, which connects the bottom electrodes to each other, supports the bottom electrodes onto the substrate, and includes a plurality of open areas, wherein a first profile, which is a horizontal cross-sectional profile in the edge area of the support structure pattern, has a wave shape.

Abstract: An electronic device is provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate including a first region in which a plurality of memory cells are disposed and a second region adjacent to the first region; a first interlayer insulating layer disposed over the substrate; a plurality of first memory cells penetrating through the first interlayer insulating layer in the first region, an uppermost portion of each memory cell of the first memory cells having a first conductive carbon-containing pattern; and a first insulating carbon-containing pattern located over the first interlayer insulating layer in the second region.

Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

Abstract: A method for fabricating an advanced metal insulator metal capacitor structure includes providing a pattern in a dielectric layer. The pattern includes a set of features in the dielectric layer. A first metal layer is deposited in the set of features in the dielectric layer. A phase change material layer is deposited over the metal layer in the set of features in the dielectric layer. The phase change material is an alloy of tantalum and nitrogen and is an insulator in a deposited state. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A second metal layer is deposited on the top surface layer of the phase change layer. In another aspect of the invention, a device is produced using the method.

Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.

Abstract: A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings.

Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are disposed in the trenches. The semiconductor fin includes a first portion embedded between the insulators; a necking portion disposed on the first portion, the necking portion being uncovered by the insulators; and a second portion disposed on the necking portion, wherein a width of the necking portion is less than a width of the first portion. The gate stack partially covers the semiconductor fin, the at least one recess and the insulators.

Abstract: Provided is a method for manufacturing a semiconductor device, which can secure a sufficient margin in a process of forming a self-aligned contact. The method includes forming a plurality of gate structures arranged in parallel on a substrate and being spaced apart from each other, each of the plurality of gate structures including a conductive layer and a capping layer formed on the conductive layer, forming a first insulation layer between each of the plurality of gate structures, recessing top portions of the plurality of gate structures, forming a block layer along a top surface of the first insulation layer and the recessed top portions of the plurality of gate structures, forming a hardmask layer on the block layer, forming a hardmask pattern on each of the plurality of gate structures by planarizing a top portion of the block layer and a top portion of the hardmask layer, and forming a second insulation layer along a top surface of the block layer and top surfaces of the hardmask patterns.

Abstract: Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.

Abstract: A system for transitioning from a first footwear type to a second footwear type is usable with an article of footwear including a sensor system with a plurality of force sensors engaged with an article of footwear and configured to sense force exerted by a foot of a user and an electronic module configured to collect data based on force input from the sensors and to wirelessly transmit data generated by the sensor system. An electronic device includes a processor that receives the data from the electronic module, compares the data to a footstrike template corresponding to a desired footstrike pattern of a footwear transitional program, determines whether a deviation from the footstrike template exists, and generates an indication to the user when the deviation from the desired footstrike pattern is determined to exist. The desired footstrike pattern corresponds to a preferred footstrike of the second type of footwear.

Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

Abstract: Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.

Abstract: A method of fabricating a semiconductor device, including forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film.

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.

Abstract: A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening.

Abstract: A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A graphene layer is a sheet like layer made of pure carbon, at least one atom thick with atoms arranged in a regular hexagonal pattern. A graphene layer may be disposed between any number of adjacent tiers in the 3DIC. In exemplary embodiments, the graphene layer provides an electromagnetic interference shield between adjacent tiers or layers in the 3DIC to reduce crosstalk between the tiers. In other exemplary embodiments, the graphene layer(s) can be disposed in the 3DIC to provide a heat sink that directs and dissipates heat to peripheral areas of the 3DIC. In some embodiments, the graphene layer(s) are configured to provide both EMI shielding and heat shielding.

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Abstract: Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit line structure and is on a sloped surface of the bit line structure. Moreover, in some embodiments, a level of the sloped surface of the bit line structure becomes lower as the sloped surface approaches the sidewall of the bit line structure.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include storage node pads disposed adjacent to each other between word lines but spaced apart from each other by an isolation pattern. Accordingly, it is possible to prevent a bridge problem from being caused by a mask misalignment. This enables to improve reliability of the semiconductor device.

Abstract: A semiconductor device with neck fins comprises a substrate, a plurality of fins having a lower portion and a neck upper portion on the substrate, and insulators disposed between each fin and flush with the lower portion of the fins.

Abstract: The instant disclosure relates to a method for manufacturing high-strength structural stacked capacitor. The novel feature of the instant disclosure is forming a part of upper electrode layer to cover the first/outer surface of each of the lower electrode layers before removing the sacrificial layer, and forming another part of upper electrode layer to cover the second/inner surface of each of the lower electrode layers after removing the sacrificial layer. Hence, the structure strength of the lower electrode layer in all process steps has been improved.

Abstract: A method is used to provide a pattern of a functional material for example on a receiving element. To provide this pattern, a laser-engraveable patternable element is imagewise exposed with laser-engraving radiation. This element has a laser-engraveable layer comprising a thermoplastic elastomeric interpolymer alloy. This interpolymer alloy comprises a non-crosslinked halogenated polymer, a partially crosslinked polyolefin, and a polyester. A laser-engraved patterned element is formed that has a relief image in the laser-engraveable layer, and this relief image can be contacted with a suitable functional material that is then transferred to the receiving element to provide the desired pattern.

Abstract: A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer.

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.

Abstract: An integrated circuit having an array of APS cells. Each cell in the array has at least one transistor source or drain region that is raised relative to a channel region formed in a semiconductor substrate. The raised source or drain region includes doped polysilicon deposited on the surface of the semiconductor body and a region of the bodyextending to the channel region that has been doped to an opposite doping type from that of the channel region by diffusion of dopants from the deposited polysilicon.

Abstract: A semiconductor device comprises: a semiconductor substrate including a cell region and a peripheral region; an insulating film formed on the top portion of the semiconductor substrate of the cell region; a bit line contact hole including the etched insulating film to expose the semiconductor substrate; a bit line contact plug buried in the bit line contact plug; and a bit line formed on the top portion of the bit line contact plug to have the same width as that of the bit line contact plug. The thickness of the insulating film around a cell bit line is minimized so as to vertically form a profile of the cell bit line, thereby improving an overlay margin of a storage node contact and an active region.

Abstract: Method and system for manufacturing CMOS image sensing device with reduced blooming. The method includes a step for providing a substrate material. The substrate material can be characterized by a first dimension and a second dimension. In addition, the method includes a step for defining an active region on the substrate material. The active region is characterized by a third dimension and a fourth dimension. The method further includes a step for defining a non-active region on the substrate material. The non-active region is different from the active region. The non-active region is characterized by a fifth dimension and a sixth dimension, the non-active region including a silicon material. The method includes a step for defining a depletion region within the active region. In addition, the method includes a step for forming an n-type region positioned above the depletion region.

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

Abstract: Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

Abstract: A method for fabricating a reservoir capacitor of a semiconductor device where a first peripheral circuit region and a second peripheral circuit region are defined comprises: forming a gate on an upper portion of a semiconductor substrate of the second peripheral circuit region; forming an interlayer insulating film on the entire upper portion of the semiconductor substrate including the gate; etching the interlayer insulating film of the second peripheral circuit region to form a bit line contact hole; forming a bit line material and a sacrificial film on the upper portion of the interlayer insulating film including the bit line contact hole; and etching the sacrificial film of the first peripheral circuit region to form a trench that exposes the bit line material.

Abstract: A first array of semiconductor fins and a second array of semiconductor fins are provided on a bulk semiconductor portion of a bulk semiconductor substrate. Each semiconductor fin of the first and second arrays is spaced apart by a first gap, and the outermost semiconductor fins of the first and second arrays of semiconductor fins are spaced apart by a second gap that is wider than the first gap. A sacrificial material is formed which completely fills the first gap, but not the second gap. An etch is employed to provide trenches into the bulk semiconductor portion which have sidewall surfaces self aligned to sidewall surfaces of sacrificial spacer structures that are formed during this etch. A trench isolation structure is formed into each trench and thereafter a functional gate structure is formed surrounding each semiconductor fin.

Abstract: A method of fabricating an array substrate includes: forming a line or an electrode on a substrate on which a pixel region is defined, forming a protection layer on the line or the electrode, the protection layer formed of silicon nitride (SiNX), forming photoresist patterns on the protection layer, and loading the substrate having the photoresist pattern into a chamber of a dry etching apparatus, and performing a first dry etching process on the protection layer exposed between the photoresist patterns using a first gas mixture containing nitrogen trifluoride (NF3) gas to form a contact hole exposing the line or the electrode.

Abstract: A semiconductor device includes a silicon substrate, a shield which is disposed on the silicon substrate and includes a conductive material, a capacitor electrode disposed on the shield, and at least one pillar member which is provided between the shield and the silicon substrate and includes a conductive material. The pillar member may be disposed at a location other than a location of a through-hole.

Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film.