Including Additional Field Effect Transistor (e.g., Sense Or Access Transistor, Etc.) Patents (Class 438/258)
  • Patent number: 8722488
    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, and a material layer covering the gate stack layers is formed on the semiconductor substrate. Subsequently, a part of the material layer is removed to form a sacrificial layer between the gate stack layers, and a spacer at the opposite lateral sides of the gate stack layers. Furthermore, a patterned mask covering the gate stack layers and the spacer and exposing the sacrificial layer is formed, and the sacrificial layer is removed.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: May 13, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ping-Chia Shih
  • Patent number: 8716089
    Abstract: A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Publication number: 20140097481
    Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Yoann Goasduff
  • Patent number: 8679915
    Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kan Yasui, Digh Hisamoto, Tetsuya Ishimaru, Shin-ichiro Kimura
  • Patent number: 8673716
    Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: March 18, 2014
    Assignee: Spansion LLC
    Inventors: Mark T. Ramsbey, Tazrien Kamal, Jean Y. Yang, Emmanuil Lingunis, Hidehiko Shiraiwa, Yu Sun
  • Patent number: 8673717
    Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes forming pillars with a doped silicon region on the substrate. An electrically conductive gate material is deposited between and over the pillars. The gate material is etched such that the gate material partially fills a space between the pillars. The pillars are then etched such that a pair of pillars from the pillars include an insulating material over the doped silicon region. A gate contact is deposited between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level, and the insulating material extends below the contact interface level.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. BrightSky, Chung H. Lam, Gen P. Lauer
  • Patent number: 8674431
    Abstract: A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Kamiya
  • Patent number: 8669158
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: March 11, 2014
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Patent number: 8658497
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Publication number: 20140048864
    Abstract: In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction.
    Type: Application
    Filed: February 27, 2013
    Publication date: February 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenji AOYAMA
  • Patent number: 8653580
    Abstract: Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Sung Lim, Jongho Park, Okcheon Hong, Jung-Hwan Park
  • Patent number: 8652906
    Abstract: A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: February 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Walter Rieger, Markus Zundel
  • Publication number: 20140008713
    Abstract: A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Elgin Quek, Shyue Seng Tan
  • Patent number: 8623726
    Abstract: A method of processing a semiconductor structure may include preparing a vertical channel memory structure for filling of a physical isolation trench formed therein. The physical isolation trench may be formed between active structures adjacent to each other and extending in a first direction. The active structures may have channels adjacent to sides of the active structures that are opposite to sides of the active structures that are adjacent to the physical isolation trench. The method may further include filling the physical isolation trench in connection with application of a multi-dielectric layer (ex. an oxide-nitride-oxide (ONO) layer), a polysilicon liner and/or an oxide film. A corresponding apparatus and method for integrating such a structure with a planar periphery are also provided.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: January 7, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Fong Huang, Tzung-Ting Han
  • Patent number: 8618586
    Abstract: An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 8614126
    Abstract: A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: December 24, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Yao-Sheng Lee, Johann Alsmeier
  • Publication number: 20130328117
    Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.
    Type: Application
    Filed: June 9, 2012
    Publication date: December 12, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Mads HOMMELGAARD, Andrew HORCH, Martin NISET
  • Patent number: 8598005
    Abstract: A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: December 3, 2013
    Assignee: Spansion LLC
    Inventors: Simon Siu-Sing Chan, Hidehiko Shiraiwa, Chuan Lin, Lei Xue, Kenichi Ohtsuka, Angela Tai Hui
  • Publication number: 20130307047
    Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 21, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu SAKUMA, Haruka KUSAI, Yasuhito YOSHIMIZU, Masahiro KIYOTOSHI
  • Patent number: 8587051
    Abstract: Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 19, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Patent number: 8581316
    Abstract: Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Ayako Inoue, Kazuhiro Tsumura
  • Patent number: 8574987
    Abstract: A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: November 5, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8569828
    Abstract: A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshitake Yaegashi
  • Publication number: 20130270623
    Abstract: According to one embodiment, a semiconductor memory device has plural memory cells arranged on a semiconductor substrate, plural select transistors for selecting the memory cell for carrying out record or read, and an insulating film arranged between adjacent memory cells and between adjacent select transistors. The memory cell and select cell transistors include gates extending the same distance from the substrate, and an insulator between adjacent select cell transistors, between the select cell transistors and the memory transistors, and between adjacent memory transistors, the height of the insulator between the select cell transistors is higher than between the select cell transistors and the memory transistors, and between adjacent memory transistors. An insulating layer deposited thereover is deposited having an in situ flatness, without further planarization.
    Type: Application
    Filed: March 8, 2013
    Publication date: October 17, 2013
    Inventors: Ryota SUZUKI, Tatsuya Kato
  • Patent number: 8556645
    Abstract: A connector includes a body configured to latchingly connect to a complementary connector element in a latching direction and an arm projecting from the body at an angle to the axis. The arm is configured to shift from a first position with its distal end a first distance from the axis to a second position with its distal end a second distance from the axis, and the body is removable from the complementary connector element when the arm is in the second position. The connector includes a force redirection element connected to the body and an extension member in contact with the force redirection element. The force redirection element is configured such that when a force is applied to the extension member in a direction opposite the latching direction, the arm is shifted from the first position toward the second position.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 15, 2013
    Assignee: CommScope, Inc. of North Carolina
    Inventor: Charles Thomas Crain
  • Patent number: 8557658
    Abstract: The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: October 15, 2013
    Assignee: Taiwan Semiconductor Manufacting Company, Ltd.
    Inventors: Shih Wei Wang, Chun Juang Lin
  • Publication number: 20130267072
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.
    Type: Application
    Filed: February 28, 2013
    Publication date: October 10, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, JR., Mehul D. Shroff
  • Patent number: 8546863
    Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: October 1, 2013
    Assignee: NXP B.V.
    Inventors: Almudena Huerta, Michiel Jos Van Duuren, Nader Akil, Dusan Golubovic, Mohamed Boutchich
  • Publication number: 20130248971
    Abstract: Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.
    Type: Application
    Filed: March 19, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoichi MIYAZAKI, Koichi MATSUNO
  • Publication number: 20130248963
    Abstract: A memory cell array including a plurality of memory cell units arrayed in a matrix configuration along a first direction and a second direction which is perpendicular direction to the first direction, each memory cell unit including a plurality of memory cell transistors, a first select gate transistor and a second select gate transistor, word lines extending to the first direction, and a first insulating film formed on an upper surface of the memory cell array, a first embedded wiring layer embedded in the first embedded wiring layer, the first embedded wiring layer including a wiring portion commonly connected to a source region of each first select gate transistor, wherein the first embedded wiring layer has an inclined pattern which extends in a direction not parallel to either of the first and the second directions.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto TAKEKIDA
  • Publication number: 20130250700
    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 26, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Publication number: 20130248970
    Abstract: A method of manufacturing a nonvolatile semiconductor storage device includes filling an element isolation trench with a sacrificial film; etching a laminate of films to form a plurality of first and second gate electrodes such that the first gate electrodes are disposed in a first region, and the second gate electrodes are disposed in a second region adjacent to the first region; removing the sacrificial film; forming a resist having an opening in the first region; forming a barrier insulating film so as to at least cover an edge of the opening; etching back the barrier insulating film and thereafter removing the resist film; forming an insulating film to form an unfilled gap in the element isolation trench located below the second gate electrode, the second region, and the third region.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoki KAI, Satoshi Nagashima
  • Publication number: 20130240974
    Abstract: A semiconductor device has a semiconductor substrate, a pair of select gate transistors provided on a first region of the semiconductor substrate, a plurality of memory cell transistors provided on a second region provided between the pair of select gate transistors on the semiconductor substrate, a gate electrode of each of the memory cell transistors, the gate electrode provided on the second region via a first insulating film, and including a charge storage layer, an intermediate insulating film, and a control gate electrode film stacked therein, a groove exposed a sidewall of the semiconductor substrate on the first region; and a gate electrode of each of the select gate transistors, the gate electrode including the control gate electrode film formed on the sidewall via a second insulating film.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 19, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenta YAMADA
  • Patent number: 8536006
    Abstract: A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8518775
    Abstract: A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with replacement metal gate (RMG) and high-k/metal gate (HKMG) modules. Embodiments include forming two substrate portions having upper surfaces at different heights, forming non-volatile gate stacks over the substrate portion with the lower upper surface, and forming high-voltage gate stacks and logic gate stacks over the other substrate portion. Embodiments include the upper surfaces of the non-voltage gate stacks, the high-voltage gate stacks, and the logic gate stacks being substantially coplanar.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: August 27, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Huang Liu, Alex Kai Hung See, Hai Cong, Zheng Zou
  • Publication number: 20130207175
    Abstract: A nonvolatile semiconductor storage device including a first transistor comprising a first gate electrode including a charge storage layer, an interelectrode insulating film, and a control electrode layer; a second transistor comprising a second gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; and a third transistor comprising a third gate electrode including a lower electrode, an upper electrode, and an upper silicide portion above the upper electrode; wherein the lower electrodes of the second and the third gate electrodes have a first side and a second side taken along a length direction of the second and the third gate electrodes, the lower electrodes of the second and the third gate electrodes including a lower silicide portion in which at least the first side of the lower electrodes are partially silicided.
    Type: Application
    Filed: August 20, 2012
    Publication date: August 15, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Wataru SAKAMOTO
  • Patent number: 8507986
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Peter Micah Sandvik, Zachary Matthew Stum, Peter Almren Losee, James Jay McMahon
  • Patent number: 8507343
    Abstract: In a variable resistance memory device and a method of manufacturing the variable resistance memory device, the generation of a seam, or void, is avoided in the device that, if present, may otherwise reduce the reliability of the resulting device.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Jung-in Kim
  • Patent number: 8497170
    Abstract: A semiconductor device manufacturing method includes: forming a first active region and a second active region in a semiconductor substrate; forming a first gate insulating film on the first active region and a second gate insulating film thinner than the first gate insulating film on the second active region by using material containing silicon oxide; forming first and second gate electrodes on the first and second gate insulating films respectively; forming an insulating film on the semiconductor substrate, and anisotropically etching the insulating film to leave first side wall insulating films on side walls of the first and second gate electrodes; removing the first side wall insulating film on the first gate electrode; and after removing the first side wall insulating film on the first gate electrode, thermally treating in an oxidizing atmosphere the semiconductor substrate to form a second side wall insulating film on the first gate electrode.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenzo Iizuka, Hajime Kurata
  • Patent number: 8492812
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral circuit region, and an active region defined by a device isolation film, at least one dummy gate formed over the active region to expose a center part and both ends of the active region, a bit line contact plug formed between the dummy gates so as to be coupled to the center part of the active region, and a storage node contact plug that is spaced apart from the bit line contact plug by the dummy gate and is coupled to both ends of the active region. As a result, the problem that the storage node contact hole is not open in the semiconductor device can be solved, resulting in improved semiconductor device characteristics.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: July 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Ho Hwang
  • Publication number: 20130178026
    Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.
    Type: Application
    Filed: February 27, 2013
    Publication date: July 11, 2013
    Applicant: FLASHSILICON INCORPORATION
    Inventor: FLASHSILICON INCORPORATION
  • Publication number: 20130178027
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
    Type: Application
    Filed: February 28, 2013
    Publication date: July 11, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, JR., Mehul D. Shroff
  • Publication number: 20130171785
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Patent number: 8460996
    Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
  • Patent number: 8450174
    Abstract: A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 28, 2013
    Assignee: SanDisk Technologies Inc.
    Inventor: Masaaki Higashitani
  • Publication number: 20130130452
    Abstract: Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 23, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Micron Technology, Inc.
  • Patent number: 8445350
    Abstract: According to an embodiment of a semiconductor device and a method of manufacturing the same, buried gates are formed in a semiconductor substrate including a cell region and a peripheral region, with the cell region and the peripheral region formed to have a step therebetween. Next, a spacer is formed in a region between the cell region and the peripheral region to block an oxidation path between a gate oxide layer and another insulating layer. Embodiments may reduce damage to active regions and prevent IDD failure because a gate pattern is formed on a guard region provided at a periphery of the cell region.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 21, 2013
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Dong Hee Han
  • Patent number: 8440526
    Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 14, 2013
    Assignee: Winbound Electronics Corp.
    Inventors: Hsiu-Han Liao, Lu-Ping Chiang
  • Patent number: 8435855
    Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate, the substrate including single crystalline silicon and having the first region and a second region; growing a pillar from a top surface of the substrate in the first region; forming a vertical channel transistor including a first gate structure such that first gate structure surrounds a central portion of the pillar; and forming a second transistor on the second region of the substrate such that the second transistor includes a second gate structure.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 7, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Uk Kim, Yong-Chul Oh
  • Publication number: 20130105881
    Abstract: A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.
    Type: Application
    Filed: October 5, 2012
    Publication date: May 2, 2013
    Inventors: James K. Kai, Vinod R. Purayath, George Matamis, Nima Mokhlesi, Cuong Trinh