Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/25)
  • Publication number: 20130109115
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes steps of enveloping a semiconductor chip attached to a lead frame with a resin and mounting a film-like member in a pocket provided in a base portion of a jig. The method further includes steps of making the resin in contact with the film-like member by covering the pocket with the portion of the lead frame having the semiconductor chip fixed thereto, after fixing the lead frame to a movable portion of the jig and moving the movable portion in a direction of the base portion; and curing the resin with the lead frame in a state covering the pocket.
    Type: Application
    Filed: March 12, 2012
    Publication date: May 2, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tatsuhiko Nagafuchi
  • Patent number: 8431948
    Abstract: A light emitting diode package and a fabrication method thereof are provided. The light emitting diode package comprises a lead frame, having a frame body and a conductive layer covering the frame body. A reflector has a first portion and a second portion sandwiching the lead frame, wherein the first portion has a depression to expose the lead frame, and a light emitting diode chip is disposed on the lead frame in the depression. The fabrication method comprises forming a frame body and forming a conductive layer covering the frame body to form a lead frame. A first portion and a second portion of a reflector are formed to sandwich the lead frame, wherein the first portion has a depression to expose the lead frame. A light emitting diode chip is disposed on the lead frame in the depression.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: April 30, 2013
    Assignee: Everlight Electronics Co., Ltd.
    Inventor: Yu-Huan Liu
  • Publication number: 20130102096
    Abstract: A semiconductor device and methods of manufacturing the same are disclosed. Specifically, methods and devices for manufacturing optocouplers are disclosed. Even more specifically, methods and devices that deposit one or more encapsulant materials on optocouplers are disclosed. The encapsulant material may include silicone and the devices used to deposit the silicone may be configured to simultaneously deposit the silicone on different sides of the optocoupler, thereby reducing manufacturing steps and time.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicant: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
    Inventors: Premkumar Jeromerajan, Gopinath Maasi, Tay Thiam Siew Gary
  • Patent number: 8426227
    Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: April 23, 2013
    Assignee: LuxVue Technology Corporation
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 8426845
    Abstract: An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 23, 2013
    Assignee: SVT Associates, Inc.
    Inventors: Yiqiao Chen, Peter Chow
  • Patent number: 8426938
    Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung Jun Park, Yong Woo Lee, Chang Rok Moon
  • Patent number: 8420409
    Abstract: An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuugo Goto, Teruyuki Fujii
  • Publication number: 20130087811
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third molded bodies. The first molded body covers a first light emitting element, a part of a lead electrically connected to the first light emitting element, a first light receiving element configured to detect a light emitted from the first light emitting element, and a part of a lead electrically connected to the first light receiving element with a first resin. The second molded body covers a second light emitting element, a part of a lead electrically connected to the second light emitting element, a second light receiving element configured to detect a light emitted from the second light emitting element, and a part of a lead electrically connected to the second light receiving element with the first resin. The third molded body molds the first and the second molded bodies as one body using a second resin.
    Type: Application
    Filed: March 20, 2012
    Publication date: April 11, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi TAKESHITA, Hidetomo Tanaka
  • Patent number: 8415780
    Abstract: A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: April 9, 2013
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Shih-Hao Sun
  • Patent number: 8404501
    Abstract: A semiconductor package structure includes a package substrate, at least a chip, solder balls, a light emitting/receiving device, a optical intermediary device and an optical transmission device. The package substrate has a first surface, a second surface, a circuit and solder ball pads, wherein each solder ball pad is electrically connected to the circuit. The chip is disposed on the first surface and electrically connected to the circuit. The solder balls are respectively disposed on the solder ball pads. The light emitting/receiving device is disposed on the package substrate and electrically connected to the circuit. The optical intermediary device is disposed above the light emitting/receiving device. The optical transmission device is inserted in the optical intermediary device, wherein a light emitting by the light emitting/receiving device is emitted to the optical transmission device via the optical intermediary device so that an optical signal is transmitted through the optical transmission device.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: March 26, 2013
    Assignee: Faraday Technology Corp.
    Inventors: Po-Yao Huang, Chia-Yu Jin, Yeong-Jar Chang
  • Patent number: 8389307
    Abstract: A light emitting diode package and a fabrication method thereof are provided. The light emitting diode package comprises a lead frame, having a frame body and a conductive layer covering the frame body. A reflector has a first portion and a second portion sandwiching the lead frame, wherein the first portion has a depression to expose the lead frame, and a light emitting diode chip is disposed on the lead frame in the depression. The fabrication method comprises forming a frame body and forming a conductive layer covering the frame body to form a lead frame. A first portion and a second portion of a reflector are formed to sandwich the lead frame, wherein the first portion has a depression to expose the lead frame. A light emitting diode chip is disposed on the lead frame in the depression.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: March 5, 2013
    Assignee: Everlight Electronics Co., Ltd.
    Inventor: Yu-Huan Liu
  • Publication number: 20130050677
    Abstract: A proximity sensor for use in a portable computing device is described. In particular various embodiments of a proximity sensor which fit in an extremely small portion of a cellular phone, and accurately determine the presence of a user's head in close proximity to a surface of the cellular phone.
    Type: Application
    Filed: September 22, 2011
    Publication date: February 28, 2013
    Applicant: Apple Inc.
    Inventors: Kelvin KWONG, Richard Hung Minh DINH, Benjamin John POPE
  • Patent number: 8384097
    Abstract: Substrates and packages for LED-based light devices can significantly improve thermal performance and provide separate electrical and thermal paths through the substrate. One substrate includes multiple electrically insulating base layers. On a top one of these layers are disposed top-side electrical contacts, including light device pads to accommodate a plurality of light devices. External electrical contacts are disposed on an exterior surface of the substrate. Electrical paths connect the top-side electrical contacts to the external electrical contacts. At least portions of some of the electrical paths are disposed between the electrically insulating base layers. The electrical paths can be arranged such that different subsets of the light device pads are addressable independently of each other. A heat dissipation plate can be formed on the bottom surface of a bottom one of the base layers.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: February 26, 2013
    Assignee: LedEngin, Inc.
    Inventor: Xiantao Yan
  • Patent number: 8378369
    Abstract: A light emitting unit (60) is provided with a resin container (61) in which a recessed portion (61a) is formed, an anode lead portion (62) and a cathode lead portion (63) which are provided so as to be exposed on the bottom surface of the recessed portion (61a), a semiconductor light emitting element (64) attached to the cathode lead portion (63) on the bottom surface (70) of the recessed portion (61a), and a sealing resin (65) provided so as to cover the recessed portion (61a). The resin container (61) is produced from a white resin containing titania as a coloring agent. The anode lead portion (62) and the cathode lead portion (63) are each configured by forming a silver-plated layer with the gloss level set in the range of 0.3-1.0 inclusive on a metal plate based on a copper alloy or the like. Thus, the efficiency of extraction of light outputted from the light emitting unit is improved.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: February 19, 2013
    Assignee: Showa Denko K.K.
    Inventors: Kenzo Hanawa, Takaharu Hoshina, Tomoyuki Takei
  • Patent number: 8378347
    Abstract: According to one embodiment, an LED package includes first and second lead frames spaced from each other, and an LED chip. Each of the first and second lead frames includes a base portion and a plurality of extending portions extending from the base portion. A part of a lower surface of the base portion, side surfaces of the base portion, lower surfaces of the extending portions and side surfaces of the extending portions are covered by resin. A remaining part of the lower surface of the base portion and tip surfaces of the extending portions are not covered by resin. The part of the lower surface of the base portion includes a first edge of the first lead frame and a second edge of the second lead frame. The first edge and the second edge are opposed each other.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Shimizu, Kazuhisa Iwashita, Teruo Takeguchi, Tetsuro Komatsu, Hiroaki Oshio, Tatsuo Tonedachi, Naoya Ushiyama, Kazuhiro Inoue, Gen Watari
  • Patent number: 8368108
    Abstract: A light emitting element housing package comprises a ceramic substrate on which a light emitting element is mounted, and a wiring pattern that is formed on the ceramic substrate and to which a light emitting element chip is electrically connected, wherein a white thin film layer formed from a sintered body of white inorganic particles is formed on at least an upper surface of the wiring pattern, except a connection region in the wiring pattern to be connected to the light emitting element chip.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 5, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Shota Shimonishi, Hiroyuki Tajima, Yosuke Tsuchiya
  • Patent number: 8367438
    Abstract: An optoelectronic semiconductor component includes a semiconductor body connected to a main area of a carrier body by a solder layer, wherein sidewalls of the semiconductor body are provided with a dielectric layer, and a mirror layer applied to the dielectric layer.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: February 5, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andreas Plöβl
  • Patent number: 8365385
    Abstract: There is provided a work processing apparatus including a plurality of work conveyance lines on which works are to be moved, a stopping unit to stop a work in a predetermined processing position on each of the work conveyance lines, a processing unit to make a desired process on the work stopped by the stopping unit, and a moving unit to move the processing unit between the work conveyance lines. Works are sequentially processed on the plurality of work conveyance lines. While a work is being processed in the processing position on one of the work conveyance lines, another work can be carried in to the other work conveyance line. Therefore, immediately after a work is completely processed on the one work conveyance line, processing of another work can be started. As a result, the production rate is higher and the apparatus can be designed smaller in size.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: February 5, 2013
    Assignee: Musashi Engineering, Inc.
    Inventor: Kazumasa Ikushima
  • Patent number: 8361899
    Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 29, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Hunt Hang Jiang
  • Patent number: 8354283
    Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting a first adhesive on the ledge including inserting the bump into an opening in the first adhesive, mounting a conductive layer on the first adhesive including aligning the bump with an aperture in the conductive layer, then flowing the first adhesive between the bump and the conductive layer, solidifying the first adhesive, then providing a heat spreader that includes the bump, a base and the ledge, then mounting a second adhesive on the ledge, mounting a conductive trace that includes a pad and a terminal on the second adhesive, then mounting a semiconductor device on the bump in a cavity in the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: January 15, 2013
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8354688
    Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.
    Type: Grant
    Filed: December 24, 2011
    Date of Patent: January 15, 2013
    Assignee: Bridge Semiconductor Corporation
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 8343784
    Abstract: The embodiment of the present invention provides an LED device, a manufacturing method of the LED device and a mounting structure of the LED device. In order to manufacture the LED device with low manufacturing cost through simple process capable of overcoming thermal fatigue due to heat generation, breaking of wire due to mechanical stress, the method comprises etching a wafer; forming a conductive metal layer from an upper surface to a lower surface of the wafer; bonding a light emitting diode chip to the metal layer which is disposed on the upper surface of the wafer; filling a resin into a space over the light emitting diode chip; and forming an electrode pad on the metal layer which is disposed on the lower surface of the wafer.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: January 1, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Dong Wook Park
  • Patent number: 8344397
    Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 1, 2013
    Assignee: Quarkstar LLC
    Inventors: Louis Lerman, Allan Brent York, Michael David Henry, Robert Steele, Brian D. Ogonowsky
  • Publication number: 20120326170
    Abstract: Optocoupler packages and methods of making the same. An exemplary package comprises a substrate having a first surface, a second surface opposite the first surface, and a body of electrically insulating material disposed between the first and second surfaces; a first optoelectronic device embedded in the body of electrically insulating material of the substrate and disposed between the substrate's first and second surfaces, the first optoelectronic device having a first conductive region and a second conductive region; a second optoelectronic device embedded in the body of electrically insulating material of the substrate and disposed between the substrate's first and second surfaces and optically coupled to the first optoelectronic device, the second optoelectronic device having a first conductive region and a second conductive region; and a plurality of electrical traces disposed on one or both surfaces of the substrate and electrically coupled to the conductive regions of the optoelectronic devices.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Inventors: Yong Liu, Qiuxiao Qian
  • Patent number: 8338839
    Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: December 25, 2012
    Assignee: Quarkstar LLC
    Inventors: Louis Lerman, Allan Brent York, Michael David Henry, Robert Steele, Brian D. Ogonowsky
  • Patent number: 8338840
    Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 25, 2012
    Assignee: Quarkstar LLC
    Inventors: Louis Lerman, Allan Brent York, Michael David Henry, Robert Steele, Brian D. Ogonowsky
  • Patent number: 8338841
    Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 25, 2012
    Assignee: Quarkstar LLC
    Inventors: Louis Lerman, Allan Brent York, Michael David Henry, Robert Steele, Brian D. Ogonowsky
  • Patent number: 8338842
    Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 25, 2012
    Assignee: Quarkstar LLC
    Inventors: Louis Lerman, Allan Brent York, Michael David Henry, Robert Steele, Brian D. Ogonowsky
  • Patent number: 8329493
    Abstract: A stretchable electronic circuit that includes a stretchable base substrate having a plurality of stretchable conductors formed onto a surface thereof, with both the stretchable base substrate and conductors being bendable together about two orthogonal axes. The stretchable circuit also includes a stretchable sensor layer attached to the base substrate with a cavity formed therein which has a contact point exposing one of the plurality of stretchable conductors. The stretchable electronic circuit further includes a surface mount device (SMD) package with a conductor contact protrusion installed into the cavity, and wherein a substantially constant electrical connection is established between the conductor contact protrusion and the stretchable conductor at the contact point by tensile forces interacting between the stretchable base substrate and the stretchable sensor layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: December 11, 2012
    Assignee: University of Utah Research Foundation
    Inventors: Stephen Mascaro, Debra Mascaro, Jumana Abu-Khalaf, Jungwoo Park
  • Publication number: 20120306038
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xusheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 8323999
    Abstract: The present invention relates to a gallium nitride-based compound semiconductor device and a method of manufacturing the same. According to the present invention, there is provided a gallium nitride-based III-V group compound semiconductor device comprising a gallium nitride-based semiconductor layer and an ohmic electrode layer formed on the gallium nitride-based semiconductor layer. The ohmic electrode layer comprises a contact metal layer, a reflective metal layer, and a diffusion barrier layer.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: December 4, 2012
    Assignee: Seoul Opto Device Co., Ltd.
    Inventor: Jong-Lam Lee
  • Patent number: 8324649
    Abstract: A light emitting device is provided that includes a light emitting structure (including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer), a conductive layer, an insulation layer, and a current blocking layer. The conductive layer may have a first conductive portion that passes through the second conductive type semiconductor layer and the active layer to contact the first conductive type semiconductor layer. The insulation layer may have a first insulation portion that surrounds the first conductive portion of the conductive layer. The current blocking layer may substantially surround the first insulation portion of the insulation layer, the first insulation portion provided between the current blocking layer and the first conductive portion.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 4, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sang Youl Lee, Hwan Hee Jeong, Ji Hyung Moon, Young Kyu Jeong, Kwang Ki Choi, June O Song
  • Patent number: 8319237
    Abstract: An integrated optical receiver architecture may be used to couple light between a multi-mode fiber (MMF) and silicon chip which includes integration of a silicon de-multiplexer and a high-speed Ge photo-detector. The proposed architecture may be used for both parallel and wavelength division multiplexing (WDM) based optical links with a data rate of 25 Gb/s and beyond.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventor: Ansheng Liu
  • Patent number: 8319304
    Abstract: A light detecting apparatus includes an SOI substrate. In the SOI substrate, a semiconductor layer and a silicon substrate are laminated via an insulating layer. The semiconductor layer has a light receiving unit and a circuit unit formed therein. The light detecting apparatus also includes an interlayer insulating film formed on a first main surface of the SOI substrate. The light detecting apparatus also includes a front surface circuit wiring embedded in the interlayer insulating film. The light detecting apparatus also includes a front surface pseudo-wiring having a grid unit. The grid unit has at least one opening allowing passage of a light of a predetermined wavelength range to the light receiving unit. The light detecting apparatus also includes a rear surface circuit wiring and a rear surface pseudo-wiring formed on a second main surface of the SOI substrate.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: November 27, 2012
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Noriyuki Miura
  • Patent number: 8314430
    Abstract: An optoelectronic component with a semiconductor body includes an active region suitable for generating radiation, and two electrical contacts arranged on the semiconductor body. The contacts are electrically connected to the active region. The contacts each have a connecting face that faces away from the semiconductor body. The contact faces are located on a connection side of the component and a side of the component that is different from the connection side is mirror-coated. A method for the manufacture of multiple components of this sort is also disclosed.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: November 20, 2012
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stefan Illek, Andreas Ploessl, Alexander Heindl, Patrick Rode, Dieter Eissler
  • Patent number: 8314008
    Abstract: A method mounting a MEMS integrated circuit on a substrate. The method includes the steps of: (a) providing a film frame tape supported by a wafer film frame, the film frame tape having the plurality of MEMS integrated circuits releasably attached via respective frontsides to the film frame tape; (b) treating a backside surface oxide layer of each MEMS integrated circuit with liquid ammonia; (c) positioning a substrate at the backside of one of said MEMS integrated circuits; (d) positioning a bonding tool on a zone of the film frame tape aligned with the MEMS integrated circuit; and (e) applying a bonding force from the bonding tool so as to bond the backside of the MEMS integrated circuit to the substrate.
    Type: Grant
    Filed: September 4, 2011
    Date of Patent: November 20, 2012
    Assignee: Silverbrook Research Pty Ltd
    Inventors: Roger Mervyn Lloyd Foote, Kia Silverbrook
  • Publication number: 20120290255
    Abstract: A method for optical isolation in a clear mold package is provided. The method comprises forming a substrate and mounting a first component on the substrate. The method also comprises depositing a clear layer over the first component and the substrate and fabricating a trench in the clear layer near the first component, wherein the trench extends from a top surface of the substrate to the top surface of the clear layer. Further, the method comprises depositing an opaque material within the trench.
    Type: Application
    Filed: September 20, 2011
    Publication date: November 15, 2012
    Applicant: Intersil Americas Inc.
    Inventors: Nikhil Vishwanath Kelkar, Viraj Ajit Patwardhan, Santhiran Nadarajah, Matt Preston
  • Patent number: 8309372
    Abstract: A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: November 13, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventor: Jong-joo Lee
  • Patent number: 8309972
    Abstract: Aspects include electrodes that provide specified reflectivity attributes for light generated from an active region of a Light Emitting Diode (LED). LEDs that incorporate such electrode aspects. Other aspects include methods for forming such electrodes, LEDs including such electrodes, and structures including such LEDs.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: November 13, 2012
    Assignee: Bridgelux, Inc.
    Inventors: Frank T. Shum, William W. So, Steven D. Lester
  • Patent number: 8307521
    Abstract: A method for manufacturing an acceleration sensing unit includes: providing an element support substrate in which a plurality of element supporting members is arranged so as to form a plane, each of the element supporting members being coupled to the other element supporting member through a supporting part and having a fixed part and a movable part that is supported by the fixed part through a beam, the beam having a flexibility with which the movable part is displaced along an acceleration detection axis direction when an acceleration is applied to the movable part; providing an stress sensing element substrate in which a plurality of stress sensing elements is arranged so as to form a plane, each of the stress sensing elements being coupled to the other stress sensing element through an element supporting part and having a stress sensing part and fixed ends that are formed so as to have a single body with the stress sensing part at both ends of the stress sensing part; disposing the stress sensing element
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: November 13, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Yoshikuni Saito
  • Patent number: 8293572
    Abstract: The injection molding system comprises a substrate, an inner cover, a molding tool, and a bottom plate. The substrate is used to locate at least one semiconductor device under molding and the inner cover with at least one first injection via, cavity and runner placed over the substrate. In addition, the molding tool includes at least one second injecting via aligned with the runner and the bottom plate is placed under the substrate. Furthermore, a filling material is filled into the cavity and runner of the inner cover during molding. In order to avoid overflowing the filling material, the system further comprises an O-ring placed between the molding tool and the inner cover. The inner radius of the O-ring corresponds with the inner radius of the injection via and is aligned with it.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 23, 2012
    Assignee: ADL Engineering Inc.
    Inventors: Wen-Chuan Chen, Nan-Chun Lin
  • Patent number: 8288183
    Abstract: An optically coupled device includes a light emitting element and a light receiving element which are electrically isolated from each other, and an optical waveguide allowing therethrough transmission of light from the light emitting element to the light receiving element, wherein the optical waveguide is covered with an encapsulation resin containing a light reflective inorganic particle which is typically composed of titanium oxide, the light emitting element and the light receiving element are respectively provided on a base (for example, package terminals), and the entire portion of the outer surface of the optical waveguide, brought into contact with none of the light emitting element, the light receiving element and the base, is covered with the encapsulation resin.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Mitsuhito Kanatake
  • Patent number: 8288181
    Abstract: A light emitting diode and its fabricating method are disclosed. A light emitting diode epitaxy structure is formed on a substrate, and then the light emitting diode epitaxy structure is etched to form a recess. The recess is then filled with a transparent dielectric material. An adhesive layer is utilized to adhere a conductive substrate and the light emitting diode epitaxy structure. Next, the substrate is removed.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: October 16, 2012
    Assignee: Epistar Corporation
    Inventors: Tzong-Liang Tsai, Way-Jze Wen, Chang-Han Chiang, Chih-Sung Chang
  • Patent number: 8273607
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 25, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Soo-San Park, Sang-Ho Lee, DaeSik Choi
  • Patent number: 8269226
    Abstract: A light emitting device including a light emitting structure including a second conductive type semiconductor layer, an active layer, and a first conductive type semiconductor layer, and a first protective layer disposed on a side of the light emitting structure, wherein the first protective layer overlaps with the first conductive type semiconductor layer in a vertical direction.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: September 18, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Ji Hyung Moon, Sang Youl Lee, Chung song Kim, Kwang Ki Choi, June O Song
  • Patent number: 8269330
    Abstract: A MOSFET pair with a stack capacitor is disclosed herein. It can regulate the input voltage and optimize a short EMI loop. It has a bottom lead frame and an up lead frame, which can simultaneously dissipate the heat generated by two MOSFETs to achieve excellent thermal-dissipation. It can adopt solder, Ag epoxy, or gold balls to implement the electrical bonding of two MOSFETs with the bottom lead frame and the up lead frame to achieve excellent structural flexibility. A device, such as an IGBT, a diode, an inductor, a choke, and a heat sink, can be stacked above the up lead frame to form a powerful SiP module. A corresponding method of manufacturing the MOSFET pair with a stack capacitor is also disclosed herein, which is simple, time-saving, flexible, cost-effective, and facile.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: September 18, 2012
    Assignee: Cyntec Co., Ltd.
    Inventors: Han-Hsiang Lee, Yi-Cheng Lin, Da-Jung Chen
  • Patent number: 8263421
    Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: September 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
  • Patent number: 8258016
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: September 4, 2012
    Assignee: LSI Corporation
    Inventors: Choshu Ito, William M. Loh, Rajagopalan Parthasarathy
  • Patent number: 8253229
    Abstract: In a stacked layer type semiconductor package constructed by stacking a plurality of packages with each other, the plurality of packages include a semiconductor package including: a semiconductor chip; a substrate in which a concave portion has been formed, the semiconductor chip being mounted in the concave portion; and a wiring line structure constructed in such a manner that the wiring line structure can be externally connected to the semiconductor chip at least just above and just under the semiconductor chip.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 28, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Tsuyoshi Kobayashi
  • Patent number: 8247833
    Abstract: An LED package includes a base, an LED chip, and an encapsulant. The LED chip is mounted on the base, and is enclosed by the encapsulant. The base includes a substrate and a blocking wall integrally formed with the substrate. The blocking wall divides a surface of the substrate into a first bonding area and a second bonding area. An electrically conductive layer and a solder are formed on the bonding area in sequence. The blocking wall can block the first and second solder to overflow outside the first and second bonding area at soldering respectively. A method for manufacturing the LED package is also provided.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: August 21, 2012
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Chia-Hui Shen, Tzu-chien Hung