Having Additional, Nonmemory Control Electrode Or Channel Portion (e.g., For Accessing Field Effect Transistor Structure, Etc.) Patents (Class 438/266)
  • Patent number: 10680094
    Abstract: An electronic device can include a channel layer including AlzGa(1-z)N, where 0?z?0.1; a gate dielectric layer; and a gate electrode of a high electron mobility transistor (HEMT). The gate dielectric layer can be disposed between the channel layer and the gate electrode. The gate electrode includes a gate electrode film that contacts the gate dielectric layer, wherein the gate electrode film can include a material, wherein the material has a sum of an electron affinity and a bandgap energy of at least 6 eV. In some embodiments, the material can include a p-type semiconductor material. The particular material for the gate electrode film can be selected to achieve a desired threshold voltage for an enhancement-mode HEMT. In another embodiment, a portion of the barrier layer can be left intact under the gate structure. Such a configuration can improve carrier mobility and reduce Rdson.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: June 9, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Abhishek Banerjee, Piet Vanmeerbeek, Peter Moens
  • Patent number: 10546947
    Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 28, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Mel Hymas, Bomy Chen, Greg Stom, James Walls
  • Patent number: 10438799
    Abstract: A method of fabricating semiconductor devices includes sequentially forming a gate layer and a mandrel layer on a substrate, forming a first photoresist on the mandrel layer, forming a mandrel pattern by at least partially removing the mandrel layer using the first photoresist as a mask, forming a spacer pattern that comprises a first mandrel spacer located on a side of a first mandrel included in the mandrel pattern and a second mandrel spacer located on the other side of the first mandrel, forming a sacrificial layer that covers the first and second mandrel spacers after removing the mandrel pattern, forming a second photoresist including a bridge pattern overlapping parts of the first and second mandrel spacers on the sacrificial layer; and forming a gate pattern by at least partially removing the gate layer using the first and second mandrel spacers and the second photoresist as a mask.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Jine Park, Yong Sun Ko, In Seak Hwang
  • Patent number: 10347673
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: July 9, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Otake, Toshifumi Wakano, Takuya Sano, Yusuke Tanaka, Keiji Tatani, Hideo Harifuchi, Eiichi Tauchi, Hiroki Iwashita, Akira Matsumoto
  • Patent number: 10269581
    Abstract: A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Chia-Wei Chang, Chao-Cheng Chen, Chun-Hung Lee, Dai-Lin Wu
  • Patent number: 10170540
    Abstract: Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Christopher J. Penny, Theodorus E. Standaert, Junli Wang
  • Patent number: 9941369
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 10, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Julien Delalleau, Arnaud Regnier
  • Patent number: 9741801
    Abstract: A method for producing a semiconductor device includes depositing an oxide film containing an impurity having a first conductivity type on a substrate. A nitride film is deposited and a first oxide film is deposited that contains an impurity having a second conductivity type that differs from the first conductivity type. The first oxide film, the nitride film, and the second oxide film are etched to form a contact hole. An epitaxial growth process is carried out form a first pillar-shaped silicon layer in the contact hole. The nitride film is removed and epitaxial growth process is performed to form an output terminal.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: August 22, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9721958
    Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 1, 2017
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Jeng-Wei Yang, Chun-Ming Chen, Man-Tang Wu, Feng Zhou, Xian Liu, Chien-Sheng Su, Nhan Do
  • Patent number: 9666588
    Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Yu Chiu, Hung-Che Liao
  • Patent number: 9508829
    Abstract: A semiconductor device includes a gate positioned on a substrate; a nanosheet that extends through the gate, protrudes from a sidewall of the gate, and forms a recess between the substrate and the nanosheet; a dielectric spacer disposed in the recess; a source/drain contact positioned on a source/drain disposed on the substrate adjacent to the gate; an air gap spacer positioned along the sidewall of the gate and in contact with a dielectric material disposed on the nanosheet, the air gap spacer being in contact with the source/drain contact; and an interlayer dielectric (ILD) disposed on the air gap spacer.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Michael A. Guillorn, Xin Miao
  • Patent number: 9361993
    Abstract: Read disturb is reduced in a charge-trapping memory device such as a 3D memory device by optimizing the channel boosting voltage in an unselected NAND string. A pass voltage applied to the unselected word lines can cause a large gradient in the channel which leads to electron-hole formation and a hot electron injection (HEI) type of read disturb. When the selected word line is close to the source-side of the NAND string, HEI disturb occurs on the drain-side of the selected word line. To avoid this disturb, a spike is provided in the control gate voltage of a drain-side selected gate transistor to temporarily connect the channel to the bit line, lowering the voltage of the associated channel region. A similar approach is used for a drain-side selected word line. The spike may be omitted when the selected word line is mid-range.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: June 7, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Hong-Yan Chen, Yingda Dong, Wei Zhao, Charles Kwong
  • Patent number: 9287275
    Abstract: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • Patent number: 9281198
    Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: March 8, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Patent number: 9275953
    Abstract: A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second nano-scale dielectric block. The matrix also includes third nano-scale dielectric block and a second nano-air-gap formed by a space between the second nano-scale dielectric block and the third nano-scale dielectric block. The nano-scale dielectric blocks share a first common width, and the nano-air-gaps share a second common width. An interconnect structure integrates the dielectric matrix with the conductive features.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yen Huang, Yu-Sheng Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9214234
    Abstract: According to one embodiment, a memory cell string stacked body includes first memory cell transistors above a semiconductor substrate, and second memory cell transistors below a first channel semiconductor film, and one of the first memory cell transistors and one of the second memory cell transistors share with a control gate electrode. The control gate electrodes of the first memory cell transistors cover an upper surface of a first charge storage layer and at least a part of a side surface in a second direction via a first insulating film in the one of the first memory cell transistors. The control gate electrodes of the second memory cell transistors cover only a lower surface of a second charge storage layer via a second insulating film in one of the second memory cell transistors.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Takekida
  • Patent number: 9209197
    Abstract: Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 8, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Ramsbey, Chun Chen, Unsoon Kim, Shenqing Fang
  • Patent number: 9171858
    Abstract: Integrated circuits with multi-level memory cells and methods for producing the same are provided. A method for producing an integrated circuit with a multi-level memory cell includes forming a gate insulator overlying a substrate. A select gate is formed overlying the gate insulator such that one multi-level memory cell includes one select gate. A thin film storage layer with nanocrystals is formed overlying the select gate and the substrate, and a left and right control gate are formed on opposite sides of the select gate such that the thin film storage layer is between the substrate and each of the control gates. A left implant and a right implant are formed in the substrate such that the select gate, the left control gate, and the right control gate are positioned between the left and right implants.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Fook Hong Lee
  • Patent number: 9171915
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of first providing a substrate, in which the substrate includes a SONOS region and a EEPROM region. Next, a first gate layer is formed in the SONOS region and the EEPROM region, the first gate layer is patterned by removing the first gate layer from the SONOS region and forming a floating gate pattern in the EEPROM region, an ONO layer is formed in the SONOS region and the EEPROM region, a second gate layer is formed on the ONO layer of the SONOS region and the EEPROM region, the second gate layer and the first gate layer are patterned to form a floating gate and a control gate in the EEPROM region, and the second gate layer is patterned to form a first gate in the SONOS region.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 27, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tzu-Ping Chen
  • Patent number: 9067286
    Abstract: The invention relates to a method for producing a piston ring (30, 130, 230) for a piston (10) of an internal combustion engine, comprising a ring back (31), an upper ring flank (32), a lower ring flank (33), and a running surface (42), and the method comprising the following method steps: (a) preparing a ring blank (30?) with a ring back (31?), an upper ring flank (32?), a lower ring flank (33?), and an outer lateral face (34?), (b) shaping an asymmetrical convex contour (35) along the outer lateral face (34?) and shaping a radially outward-extending protrusion (36) in the outer lateral surface (34?) in the region of the lower ring flank (33?), (c) coating the outer lateral surface (34?) with a coating material, (d) removing the protrusion (36), thereby exposing the material of the ring blank (30?) in the shape of a circumferential surface (41) which blends into the coating (39), and forming an oil scraper edge (40) between the circumferential surface (41) and the lower ring flank (33?), and (e) post and/or
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 30, 2015
    Assignee: MAHLE International GmbH
    Inventors: Daniel Lopez, Richard Alves
  • Patent number: 9064967
    Abstract: The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: June 23, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Motomu Kurata, Mayumi Mikami
  • Patent number: 9064734
    Abstract: A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jae-Hwang Sim
  • Patent number: 9040375
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: May 26, 2015
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Patent number: 9041092
    Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20150137206
    Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chyi Liu, Wei-Hang Huang, Yu-Hsing Chang, Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 9029933
    Abstract: According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Sotome, Kenta Yamada, Wataru Sakamoto
  • Patent number: 9029936
    Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Publication number: 20150123187
    Abstract: A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 7, 2015
    Inventors: Hiroyuki Ogawa, Junichi Ariyoshi
  • Patent number: 9024425
    Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least an integrated intermediate-circuit die comprising both a read/write-voltage generator (VR/VW-generator) and an address/data translator (A/D-translator). The intermediate-circuit die performs voltage, address and/or data conversion between the 3D-M core region and the host. Discrete 3D-M support multiple 3D-array dies.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 5, 2015
    Assignees: HangZhou HaiCun Information Technology Co., Ltd., Guobiao Zhang
    Inventor: Guobiao Zhang
  • Patent number: 9018690
    Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Mandana Tadayoni, Nhan Do
  • Patent number: 9012972
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisakazu Matsumori, Hideto Takekida, Akira Mino, Jun Murakami
  • Patent number: 9006073
    Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Su Jin Chae, Jin Hyock Kim, Young Seok Kwon
  • Publication number: 20150097223
    Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate spacer is over the memory gate electrode, a charge storage layer formed between the control gate structure and the memory gate structure, wherein the charge storage layer is an L-shaped structure, a first spacer along a sidewall of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8987787
    Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Kuang-Yeu Hsieh, Cheng-Yuan Wang
  • Publication number: 20150076582
    Abstract: A transistor is provided. The transistor includes a substrate, a gate electrode formed on the substrate, and multiple floating gates formed on the substrate. A fixed distance is designed between the adjacent floating gates. Wherein, the substrate, the multiple floating gates, and the gate electrode are separated by a plurality of active regions.
    Type: Application
    Filed: March 3, 2014
    Publication date: March 19, 2015
    Applicant: National Tsing Hua University
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Publication number: 20150079706
    Abstract: A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage.
    Type: Application
    Filed: July 3, 2014
    Publication date: March 19, 2015
    Inventor: Jiuun-Jer Yang
  • Patent number: 8980712
    Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Han-Soo Joo
  • Publication number: 20150056768
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 26, 2015
    Inventors: Cheng-Yuan Hsu, CHI Ren, Tzeng-Fei Wen
  • Publication number: 20150041815
    Abstract: According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.
    Type: Application
    Filed: March 3, 2014
    Publication date: February 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi SONEHARA, Takeshi MURATA, Junya FUJITA, Fumiki AISO, Saku HASHIURA
  • Publication number: 20150044833
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: September 23, 2014
    Publication date: February 12, 2015
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Igor G. Kouznetsov, Mark G. Johnson, Paul Michael Farmwald
  • Patent number: 8952446
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a channel body, a memory film, first and second insulating separation films, a first and a second inter-layer insulating films, a selection gate, a conductive layer, and resistance elements. The substrate includes a memory cell array region and a peripheral region. The stacked body includes electrode films and insulating films. The channel body extends in a stacking direction. The memory film includes a charge storage film. The first insulating separation films divide the stacked body. The first and the second inter-layer insulating films are on the stacked body and on the conductive layer, respectively. The selection gate is on the first inter-layer insulating film. The conductive layer is on the peripheral region. The resistance elements are on the second inter-layer insulating film. The second insulating separation films divide the conductive layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyasu Tanaka
  • Publication number: 20150036437
    Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: Qualcomm Incorporated
    Inventors: Xia Li, Bin Yang, Zhongze Wang
  • Patent number: 8946022
    Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
  • Patent number: 8946007
    Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Publication number: 20150021679
    Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Tsun-Kai Tsao, Ming-Huei Shen
  • Publication number: 20150004764
    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventor: Toru Tanzawa
  • Patent number: 8921991
    Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: December 30, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8916432
    Abstract: Methods of forming memory cells including non-volatile memory (NVM) and MOS transistors are described. In one embodiment the method includes: depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a NVM transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain adjacent to the gate of the NVM transistor.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 23, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar
  • Patent number: 8901632
    Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater