Having Additional, Nonmemory Control Electrode Or Channel Portion (e.g., For Accessing Field Effect Transistor Structure, Etc.) Patents (Class 438/266)
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Patent number: 8319283Abstract: A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.Type: GrantFiled: May 29, 2009Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Won Gi Min, John L. Huber, Jiang-Kai Zuo
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Patent number: 8314457Abstract: Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.Type: GrantFiled: April 27, 2011Date of Patent: November 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Kim, Sun-Il Shim, Chang-Seok Kang, Won-Cheol Jeong, Jung-Dal Choi, Jae-Kwan Park, Seung-Hyun Lim, Sun-Jung Kim
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Patent number: 8310000Abstract: A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.Type: GrantFiled: October 25, 2011Date of Patent: November 13, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Shunpei Yamazaki
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Publication number: 20120264264Abstract: A method of fabricating a non-volatile memory device is provided. A substrate including a first region and a second region is provided. Then, an uneven surface is formed on the substrate in the second region. Thereafter, a doped layer is formed in the substrate in the second region, and the doped layer is served as a control gate. Afterward, a dielectric layer is formed on the substrate in the first region and on the uneven surface of the substrate in the second region. Next, a floating gate is formed on the dielectric layer, and the floating gate is extended from the first region to the second region. Source and drain regions are formed in the substrate at opposite sides of the floating gate in the first region.Type: ApplicationFiled: June 28, 2012Publication date: October 18, 2012Applicant: MAXCHIP ELECTRONICS CORP.Inventors: Chung-Yi Chen, Li-Yeat Chen, Jung-Chun Lin
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Patent number: 8278170Abstract: Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.Type: GrantFiled: June 21, 2011Date of Patent: October 2, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Changhyun Lee, Sunil Shim, Jaehoon Jang, Sunghoi Hur, Hansoo Kim, Kihyun Kim
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Patent number: 8274108Abstract: A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line.Type: GrantFiled: February 12, 2010Date of Patent: September 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Yoshiaki Fukuzumi, Hideaki Aochi
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Patent number: 8273625Abstract: A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.Type: GrantFiled: April 9, 2010Date of Patent: September 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huei Shen, Tsun-Kai Tsao, Shih-Chang Liu, Chi-Hsin Lo, Chia-Shiung Tsai
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Publication number: 20120231594Abstract: Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.Type: ApplicationFiled: March 10, 2011Publication date: September 13, 2012Applicant: WAFERTECH, LLCInventor: Yimin Wang
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Publication number: 20120225528Abstract: A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.Type: ApplicationFiled: March 1, 2011Publication date: September 6, 2012Applicant: WAFERTECH, LLCInventors: Yimin Wang, Raymond Li
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Patent number: 8242007Abstract: Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.Type: GrantFiled: March 11, 2009Date of Patent: August 14, 2012Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Jong-ho Park, Chang-ki Jeon, Hyi-jeong Park
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Patent number: 8237213Abstract: Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.Type: GrantFiled: July 15, 2010Date of Patent: August 7, 2012Assignee: Micron Technology, Inc.Inventor: Zengtao Liu
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Patent number: 8216899Abstract: According to the present disclosure, a flash memory device includes a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers.Type: GrantFiled: October 28, 2009Date of Patent: July 10, 2012Assignee: Hynix Semiconductor Inc.Inventor: Byoung Ki Lee
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Publication number: 20120168843Abstract: A semiconductor device includes a bit line formed over a substrate, an insulation layer formed over the bit line, a gate line crossing the bit line and formed over the insulation layer, and a channel layer formed on both sidewalls of the gate line and coupled to the bit line.Type: ApplicationFiled: August 3, 2011Publication date: July 5, 2012Inventor: Dae-Young SEO
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Patent number: 8211767Abstract: A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.Type: GrantFiled: March 14, 2011Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Toshitake Yaegashi
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Patent number: 8207034Abstract: A semiconductor memory device is formed to include: a substrate; a floating gate formed on the substrate via a gate insulating film; a control gate formed on an adjacent position to the floating gate via a tunnel insulating film; a spacer insulating film formed on the floating gate; and a protection film formed between the spacer insulating film and the control gate. In such a semiconductor memory device (MC), the protection film functions as a stopper of a side surface of the spacer insulating film when a part other than the spacer insulating film is etched.Type: GrantFiled: July 26, 2010Date of Patent: June 26, 2012Assignee: Renesas Electronics CorporationInventor: Kenji Tsujita
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Patent number: 8207036Abstract: A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.Type: GrantFiled: September 30, 2008Date of Patent: June 26, 2012Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, Henry Chien, James K. Kai
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Patent number: 8198156Abstract: A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.Type: GrantFiled: January 24, 2011Date of Patent: June 12, 2012Assignee: Hynix Semiconductor Inc.Inventor: Nam-Jae Lee
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Patent number: 8193576Abstract: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.Type: GrantFiled: July 30, 2009Date of Patent: June 5, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Kwang-Young Ko
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Patent number: 8187936Abstract: A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.Type: GrantFiled: June 30, 2010Date of Patent: May 29, 2012Assignee: SanDisk Technologies, Inc.Inventors: Johann Alsmeier, Vinod Robert Purayath, Henry Chien, George Matamis, Yao-Sheng Lee, James Kai, Yuan Zhang
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Publication number: 20120119282Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
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Patent number: 8178408Abstract: Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern.Type: GrantFiled: January 4, 2010Date of Patent: May 15, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hak-Sun Lee, Kyoung-Sub Shin, Jeong-Dong Choe
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Patent number: 8178412Abstract: A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the memory cell transistor are arranged in and on a semiconductor substrate. The impurity concentration of the source/drain diffusion layer shared by the memory cell transistor and the select transistor in each of the plurality of memory cells is set lower than the impurity concentration of the other source/drain diffusion layers in each of the memory cells.Type: GrantFiled: September 24, 2008Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Isobe
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Patent number: 8173505Abstract: A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.Type: GrantFiled: October 20, 2008Date of Patent: May 8, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Matthew T. Herrick, Ko-Min Chang, Gowrishankar L. Chindalore, Sung-Taeg Kang
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Patent number: 8163608Abstract: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening.Type: GrantFiled: November 19, 2010Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Tae Park, Jeong-Hyuk Choi
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Patent number: 8163616Abstract: Nonvolatile memory devices and methods of manufacturing nonvolatile memory devices are provided. The method includes patterning a bulk substrate to form an active pillar; forming a charge storage layer on a side surface of active pillar; and forming a plurality of gates connected to the active pillar, the charge storage layer being disposed between the active pillar and the gates. Before depositing a gate, a bulk substrate is etched using a dry etching to form a vertical active pillar which is in a single body with a semiconductor substrate.Type: GrantFiled: September 21, 2011Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Pil-Kyu Kang, Daelok Bae, Jongwook Lee, Seungwoo Choi, Yong-Hoon Son, Jong-Hyuk Kang, Jung Ho Kim
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Patent number: 8158480Abstract: A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.Type: GrantFiled: June 18, 2008Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Soo Kang, Choong-Ho Lee, Suk-Kang Sung, Se-Jun Park
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Patent number: 8159020Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2 ) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3 ), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3 ?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.Type: GrantFiled: September 17, 2009Date of Patent: April 17, 2012Assignee: Infineon Technologies AGInventors: Franz Schuler, Georg Tempel
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Patent number: 8148769Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.Type: GrantFiled: August 3, 2009Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Patent number: 8143122Abstract: A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions, and a control gate electrode serving as a word line and disposed on the floating gate electrode with an interelectrode insulating film interposed therebetween. The interelectrode insulating film covers whole side portions of the floating gate electrode located in a direction different from a direction in which the word line extends, and the control gate electrode covers the side portions of the floating gate electrode located in the direction different from the direction in which the word line extends.Type: GrantFiled: May 17, 2010Date of Patent: March 27, 2012Assignee: Kabushiki Kaisha TohibaInventor: Takayuki Toba
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Patent number: 8138035Abstract: A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.Type: GrantFiled: February 28, 2011Date of Patent: March 20, 2012Assignee: Texas Instruments IncorporatedInventors: Weize Xiong, Cloves Rinn Cleavelin, Angelo Pinto, Rick L. Wise
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Patent number: 8119480Abstract: A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.Type: GrantFiled: September 29, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hoon Lee, Sungil Park, Young-Gu Jin, Jongseob Kim, Ki-Ha Hong
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Patent number: 8114730Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.Type: GrantFiled: July 20, 2010Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Abraham Yoo, Hee-Sung Kang, Heon-Jong Shin
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Patent number: 8110454Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.Type: GrantFiled: September 2, 2009Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventor: Sameer P. Pendharkar
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Patent number: 8101484Abstract: In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.Type: GrantFiled: June 23, 2010Date of Patent: January 24, 2012Assignee: Fairchild Semiconductor CorporationInventors: Izak Bencuya, Brian Sze-Ki Mo, Ashok Challa
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Patent number: 8097507Abstract: A semiconductor device and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer and the second conductive layer are patterned. A first passivation layer is formed on sidewalls of the gate electrode layer. Gate patterns are formed by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed. A second passivation layer is formed on the entire surface along a surface of the gate patterns including the first passivation layer.Type: GrantFiled: May 26, 2009Date of Patent: January 17, 2012Assignee: Hynix Semiconductor Inc.Inventor: Kwang Seok Jeon
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Patent number: 8097505Abstract: A method of forming an isolation layer in a semiconductor device is disclosed, by which breakdown voltage and PN junction leakage characteristics of the isolation layer are enhanced. Embodiments include depositing a pad nitride layer over a semiconductor substrate, reducing the thickness of the pad nitride layer by etching a portion of the pad nitride layer, forming a tetraethyl orthosilicate (TEOS) oxide layer over the remaining pad nitride layer, forming a trench by selectively removing the tetraethyl orthosilicate oxide layer and the pad nitride layer over an isolation area of the semiconductor substrate, depositing an high density plasma oxide layer over the substrate to fill the trench, and forming an isolation layer by planarizing the high density plasma oxide layer and the tetraethyl orthosilicate oxide layer.Type: GrantFiled: August 24, 2008Date of Patent: January 17, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Ji-Ho Hong
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Patent number: 8093125Abstract: Example embodiment is provided to a method for manufacturing a semiconductor device, including forming a hard mask layer on a buried bit line and forming a storage node contact hole by using the selectivity between an interlayer insulating layer and the hard mask layer, thereby forming a contact hole using a mask of a line pattern instead of a hole pattern. Accordingly, a mask for the contact hole can be easily fabricated and the contact area can be maximized, thereby reducing the contact resistance.Type: GrantFiled: December 30, 2009Date of Patent: January 10, 2012Assignee: Hynix Semiconductor, Inc.Inventor: Ji Hye Kim
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Publication number: 20120001249Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: SanDisk CorporationInventors: Johann Alsmeier, George Samachisa
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Publication number: 20110309424Abstract: A structure of a memory cell of a static random memory device and a process for fabricating the same are disclosed. The memory cell includes a substrate having an active region including an N-well and a shallow trench isolation structure; a first gate and a second gate formed over the substrate; a halo region, a LLD, and a source and drain region formed on two sides of the first gate; an interlevel dielectric layer covering the substrate, the first and second gates; and a contact penetrating the interlevel dielectric layer and extending to the source and drain region, no halo region is formed under the contact.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Inventors: Ming-Te WEI, Po-Chao Tsao, Jun-Chi Huang, Chia-Wei Huang, Chuan-Hsien Fu, Chih-Fang Tsai, Te-Hung Wu
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Patent number: 8071449Abstract: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.Type: GrantFiled: December 3, 2010Date of Patent: December 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Aoyama, Hisataka Meguro, Satoshi Nagashima
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Patent number: 8072023Abstract: A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.Type: GrantFiled: October 31, 2008Date of Patent: December 6, 2011Assignee: Marvell International Ltd.Inventor: Chih-Hsin Wang
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Patent number: 8067809Abstract: A semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by favorable nitrogen concentration profile of a gate insulating film, and a method for manufacturing the semiconductor device. The semiconductor device fabricating method operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, including introducing an oxynitriding species previously diluted by plasma excitation gas into a plasma processing apparatus, generating an oxynitriding species by a plasma, and forming an oxynitride film on the semiconductor substrate as the gate insulating film. The oxynitriding species contains NO gas at a ratio of 0.00001 to 0.01% to the total volume of gas introduced into the plasma processing apparatus.Type: GrantFiled: September 30, 2005Date of Patent: November 29, 2011Assignees: Tokyo Electron Limited, Tohoku UniversityInventors: Junichi Kitagawa, Shigenori Ozaki, Akinobu Teramoto, Tadahiro Ohmi
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Patent number: 8063431Abstract: An electrically erasable programmable read only memory (EEPROM) is disclosed. The EEPROM includes a tunneling region in a semiconductor substrate, a control gate region in the semiconductor substrate and separated from the tunneling region by a device isolating layer, a tunnel oxide layer in a trench in the semiconductor substrate between the tunneling region and the control gate region, and a polysilicon layer on the tunnel oxide layer.Type: GrantFiled: September 21, 2009Date of Patent: November 22, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Kwang Young Ko
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Patent number: 8048739Abstract: According to yet another embodiment, a method for forming a non-volatile memory device includes etching a substrate to form first and second trenches. The first and second trenches are filled with an insulating material to form first and second isolation structures. A conductive layer is formed over the first and second isolation structures and between the first and second isolation structures to form a floating gate. The conductive layer and the first isolation structure are etched to form a third trench having an upper portion and a lower portion, the upper portion having vertical sidewalls and the lower portion having sloping sidewalls. The third trench is filled with a conductive material to form a control gate.Type: GrantFiled: June 30, 2006Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Patent number: 8049266Abstract: A nonvolatile semiconductor memory device is provided in such a manner that a semiconductor layer is formed over a substrate, a charge accumulating layer is formed over the semiconductor layer with a first insulating layer interposed therebetween, and a gate electrode is provided over the charge accumulating layer with a second insulating layer interposed therebetween. The semiconductor layer includes a channel formation region provided in a region overlapping with the gate electrode, a first impurity region for forming a source region or drain region, which is provided to be adjacent to the channel formation region, and a second impurity region provided to be adjacent to the channel formation region and the first impurity region. A conductivity type of the first impurity region is different from that of the second impurity region.Type: GrantFiled: December 23, 2010Date of Patent: November 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Shunpei Yamazaki
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Publication number: 20110263087Abstract: A semiconductor device which is formed in a self-aligned manner without causing a problem of misalignment in forming a control gate electrode and in which a leak between the control gate electrode and a floating gate electrode is not generated, and a manufacturing method of the semiconductor device are provided. A semiconductor device includes a semiconductor film, a first gate insulating film over the semiconductor film, a floating gate electrode over the first gate insulating film, a second gate insulating film which covers the floating gate electrode, and a control gate electrode over the second gate insulating film. The control gate electrode is formed so as to cover the floating gate electrode with the second gate insulating film interposed therebetween, the control gate electrode is provided with a sidewall, and the sidewall is formed on a stepped portion of the control gate electrode, generated due to the floating gate electrode.Type: ApplicationFiled: June 20, 2011Publication date: October 27, 2011Inventor: Yoshinobu Asami
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Patent number: 8043914Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.Type: GrantFiled: December 3, 2009Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-wan Choi, Yong-soon Choi, Bo-young Lee, Eunkee Hong, Eun-kyung Baek, Ju-seon Goo
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Patent number: 8022462Abstract: Methods of forming buried bit lines in a non-volatile memory device can include forming impurity regions in a substrate of a non-volatile memory device to provide immediately neighboring buried bit lines for the device and then forming a shallow trench isolation region in the substrate between the immediately neighboring buried bit lines to substantially equalize lengths of the immediately neighboring buried bit lines.Type: GrantFiled: April 25, 2008Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Wook Hyun Kwon
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Patent number: 8017991Abstract: Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.Type: GrantFiled: March 15, 2007Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, Suk-pil Kim, Yoon-dong Park, June-mo Koo
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Patent number: 8017477Abstract: A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.Type: GrantFiled: February 9, 2007Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-joo Kim, Suk-pil Kim, Yoon-dong Park