Abstract: A CMOS circuit for and method of forming a FinFET device is disclosed. The method includes providing a substrate comprising a semiconductor layer, forming on the semiconductor layer active areas insulated from each other by field areas, forming at least one dummy gate on at least one of said active areas and forming source and drain regions on the at least one of the active areas. The method also includes covering the substrate with an insulating layer leaving said dummy gate exposed and forming an open cavity by patterning the dummy gate to form a dummy fin and a semiconductor fin aligned to said dummy fin, both fins extending from the source to the drain regions.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A selfaligned FinFET is fabricated by defining a set of fins in a semiconductor wafer, depositing gate material over the fins, defining a gate hardmask having a thickness sufficient to withstand later etching steps, etching the gates material outside the hardmask to form the gate, depositing a conformal layer of insulator over the gate and the fins, etching the insulator anistotropically until the insulator over the fins is removed down to the substrate, the hardmask having a thickness such that a portion of the hardmask remains over the gate and sidewalls remain on the gate, and forming source and drain areas in the exposed fins while the gate is protected by the hardmask material.

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.

Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.

Abstract: A double gate electrode for a field effect transistor is fabricated by forming in a substrate, a trench and a tunnel that extends from a sidewall of the trench parallel to the substrate. An insulating coating is formed inside the tunnel. A bottom gate electrode is formed within the insulating coating inside the tunnel. An insulating layer is formed on the substrate and a top gate electrode is formed on the insulating layer opposite the bottom gate electrode.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is located on one side of the fin. A portion of the first gate includes conductive material doped with an n-type dopant. The second gate is formed on the insulating layer and is located on the opposite side of the fin as the first gate. A portion of the second gate includes conductive material doped with a p-type dopant.

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract: A semiconductor device (1) has a fin (2) and a multiple gate electrode (3) over the fin (2), the multiple gate electrode (3) being a layer of gate electrode material with a substantially planar surface (13b) to support a patterned mask (14a), the mask (14a) having a uniform thickness and a planar surface controlling the patterning dimensions of the patterned mask (14a).

Abstract: Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region.

Abstract: In cellular MOSFET transistor arrays using a geometric gate construction, deleterious inherent capacitance induced by the construction is substantially reduced by the use of plugs in between adjacent source regions of transistor source rows and adjacent drain regions of transistor drain rows of the array. Embodiments using field oxide, thicker step gate oxide, dielectric materials in a floating gate construction, and shallow trench isolation region plugs are described.

Abstract: An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

Abstract: The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.

Abstract: A method for fabricating a multiple-gate device including the steps of providing a substrate of a semi-conducting layer on an insulator stack which includes an insulator layer overlying an etch-stop layer; patterning a semi-conducting layer forming a semiconductor fin; etching the insulator layer at the base of the fin forming an undercut; depositing a gate dielectric layer overlying the fin; depositing an electrically conductive layer over the gate dielectric layer; etching the electrically conductive layer forming a gate straddling across the two sidewall surfaces and the top surface of the fin; and forming a source region and a drain region in the fin.

Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Abstract: The present invention relates to a gas insulated gate field effect transistor and a fabricating method thereof which provides an improved insulator between the gate and the source-drain channel of a field effect transistor. The insulator is a vacuum or a gas filled trench. As compared to a conventional MOSFET, the gas insulated gate device provides reduced capacitance between the gate and the source/drain region, improved device reliability and durability, and improved isolation from interference caused by nearby electric fields. The present invention includes the steps of forming a doped source region and drain region on a substrate, forming a gate, forming a gaseous gate insulating trench and forming terminals upon the gate, the source region and the drain region. A plurality of the devices on a single substrate may be combined to form an integrated circuit.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

Abstract: An aspect the present invention is to provide a semiconductor device including at least one MISFET structure having an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region, an element region formed on the surface region of the semiconductor substrate to surround the element isolation region, a gate insulating film formed to cover at least the surface of the element region, a contact region formed on the element isolation region, and at least four gate electrodes connected to the contact region and formed on the surface of the element region via the gate insulating film to extend to at least outside the element region.

Abstract: The present invention relates to a method for fabrication of semiconductor devices, in particular but not limited to the fabrication of double gate transistors of the type Gate-All-Around or “semiconductor-on-nothing” transistors and devices. A method according to the present invention comprises the steps of: (a) forming a trench in a least a first substrate, (b) transferring semiconductor material over the trench to form a semiconductor bridge across the trench, the semiconductor bridge defining an active area. The bridge may be free to oscillate above the trench without using removing a sacrificial layer. The method may also include the steps of: (c) forming a gate insulator on the semiconductor bridge, and (d) applying gate material on the gate insulator, thus forming a gate.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

Abstract: The method comprising sequentially forming a first oxide film, a first nitride film, a second oxide film and a second nitride film on a semiconductor substrate; forming a first mask on the second nitride film; etching the second nitride film and the second oxide film forming a first spacer; sequentially forming a gate insulation film and a gate conductor; wet etching the remaining second nitride film, second oxide film, first nitride film and first spacer; performing LDD implantation on the substrate to form an LDD region; forming a second spacer; performing source/drain implantation to form source/drain regions; removing the remaining first oxide film; and forming a salicide region in the gate conductor and the source/drain regions.

Abstract: The present invention discloses a vertical transistor wherein source/drain regions are formed by using a self-alignment method without using a latest photolithography, channels are formed via a selective epitaxial growth (hereinafter, referred to as ‘SEG’) method and gate oxide films are formed at the both ends of channels to be more efficient than devices having the same channel length, and a method of manufacturing thereof, the vertical transistor comprising: a source region formed on a semiconductor substrate; a drain region formed substantially above the source region; a vertical channel, one end of the channel being contact to the source region and the other end being contact to the drain region; and a gate electrode, formed on the substrate, surrounding the sides of the channel and the drain region, said gate electrode electrically isolated with the source region by a nitride pattern disposed therebetween, isolated with the drain region by a nitride spacer formed on the sidewalls of the drai

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. The trench is etched using an etchant gas that also serves as a dopant source for the formation of the doped column. For example, if a p-type dopant such as boron is desired, BCl3 may be used as the etchant gas. Alternatively, if an n-type dopant such as phosphorus is required, PH3 may be used as the etchant gas. The dopant present in the gas is incorporated into the silicon defining the surfaces of the trench. This dopant is subsequently diffused to form the doped column surrounding the trench.

Abstract: A semiconductor device suppressing the lateral diffusion of impurities doped in a PMOS and NMOS and shortening the distance between the PMOS and NMOS to reduce the size of the semiconductor device, including PMOS and NMOS formation regions isolated by an element isolation region; a p-type gate electrode arranged on the PMOS formation region; an n-type gate electrode arranged on the NMOS formation region; and first and second impurity storage regions arranged in a direction different from that of the arrangement of the p-type and n-type gate electrodes. An end of the first impurity storage region is connected to the p-type gate electrode, an end of the second impurity storage region is connected to the n-type gate electrode, and the other ends of the first and second impurity storage regions are electrically connected.

Abstract: Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Abstract: A switching power supply including a power factor correction circuit comprises a rectifier, an inductor coupled in series with the rectifier, a semiconductor switch formed by a compensation device coupled in parallel with the rectifier and the inductor. The output circuit comprises a diode coupled in series with a capacitor both coupled in parallel with the semiconductor switch. An input current sensor, and a control unit for controlling the compensation device are provided.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method patterns a stopper layer and a first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on an element separating region in the logic circuit area. The method forms an ONO membrane over the whole surface of the memory area and the logic circuit area, and further forms a second conductive layer above the ONO membrane. The method carries out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area.

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination zone provided at the surface of the transistor includes the steps of producing the horizontal polysilicon gate first and then introducing the recombination zone. The process allows producing a transistor without encountering problems caused by the insufficient high-temperature compatibility of metals.

Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

Abstract: A power MOSFET semiconductor device high in breakdown voltage and low in resistance can be manufactured at a low cost and in a short turnaround time. In a planar-type power MOSFET, a manufacture method comprises forming a trench in a drift region, and forming a body diffusion layer on a trench side wall and bottom portion (forming the trench and subsequently performing diffusion) to obtain a structure. Deep body diffusion formation is effective for obtaining the high breakdown voltage and low resistance, but to attain the structure, usually epitaxial growth and selective formation of a deep body region have to be performed a plurality of times, and with an increase of manufacture steps, souring of manufacture cost and lengthening of manufacture period are caused. However, the present structure can further simply bring about the similar effect. It is possible to supply the power MOSFET semiconductor device at the low cost and in the short manufacture turnaround time.

Abstract: In one implementation, a non-volatile resistance variable device includes a body formed of a voltage or current controlled resistance setable material, and at least two spaced electrodes on the body. The body includes a surface extending from one of the electrodes to the other of the electrodes. The surface has at least one surface striation extending from proximate the one electrode to proximate the other electrode at least when the body of said material is in a highest of selected resistance setable states. In one implementation, a method includes structurally changing a non-volatile device having a body formed of a voltage or current controlled resistance setable material and at least two spaced electrodes on the body. The body has a surface extending from one of the electrodes to the other of the electrodes, and the surface is formed to comprise at least one surface striation extending from proximate the one electrode to proximate the other electrode.

Abstract: A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In a process for forming a contact plug, a pad polycrystalline silicon layer pattern is formed at the presumed contact region, and a contact plug is formed according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed. Accordingly, a higher contact plug is formed by improving a growth rate of the SEG process, and thus a succeeding process can be easily performed. In the SEG process, a contact property is improved by compensating for a semiconductor substrate damaged in a process for forming an insulating film spacer at the sidewalls of a gate electrode. As a result, the property and yield of the semiconductor device are remarkably improved.

Abstract: For fabricating a test field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A dummy structure is formed on the gate electrode material, and the dummy structure is disposed over a shaped area of the gate electrode material and of the semiconductor substrate. The dummy structure has at least one sidewall around a perimeter of the shaped area. A spacer structure is formed to surround the at least one sidewall of the dummy structure outside of the perimeter of the shaped area. The dummy structure is etched away such that the shaped area of the gate electrode material is exposed and such that the spacer structure remains outside of the perimeter of the shaped area. Any exposed regions of the gate electrode material and of the gate dielectric material not under the spacer structure are etched away.

Abstract: A complementary metal oxide semiconductor integrated circuit containing a notched gate in the support device region as well as a method of forming the same are provided.

Abstract: The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts.

Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched to expose the substrate and a portion of the STI region. The surface is etched and the mask oxide layer is eroded away while creating a gate recess in the unmasked area. A thin pad oxide layer is then grown overlying the surface followed by a deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown causing the pad oxide layer to further thicken.

Abstract: A semiconductor device comprising, on a semiconductor substrate, an element-isolating region, an active region, and a gate electrode with a bent portion having a bent-angle &thgr; on the active region. The boundary between the element-isolating region and the active region intersects the gate electrode so that the line segments of the boundary at which said intersection takes place, are approximately parallel to the bisector of the bent-angle &thgr; of the bent portion of the gate electrode. In this semiconductor device, the variation in width of gate electrode is small and accordingly the variation in properties is small, even when the relative position of gate electrode and active region of MOSFET has shifted slightly.

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.