Abstract: A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surface of the silicon substrate is formed by anisotropically etching the first surface of the silicon substrate to remove a portion of the material from the substrate. Both the first and second halo regions are formed by low-energy ion implantation. For the fabrication of an n-channel device, boron is implanted at an energy of no more than about 1 keV. Upon implantation and a subsequent annealing process, the first and second halo regions form a continuous halo region within the semiconductor substrate.

Abstract: Floating body effects are substantially reduced by strategically forming source-side stacking faults to create a leakage path from the body to the source of an SOI structure. Embodiments include ion implanting a heavy ion, such as Xe, to form a buried amorphous layer in the source-side of the silicon layer after source/drain implants followed by silicidation, during which the buried amorphous region recrystallizes creating source-side stacking faults.

Abstract: A field effect transistor having a doped region in the substrate immediately underneath the gate of the transistor and interposed between the source and drain of the transistor is provided. The doped region has a retrograde dopant profile such that the doping concentration immediately adjacent the gate is selected to allow for the formation of a channel when a threshold voltage is applied to the gate thereby eliminating the need for an enhancement doping step during formation of the transistor. The retrograde doping profile increases with the depth into the substrate which inhibits stray currents from traveling between the source and drain of the transistor in the absence of the formation of a channel as a result of voltage being applied to the gate of the transistor.

Abstract: There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion.

Abstract: A novel silicon RF LDMOSFET structure based on the use of a stacked LDD, is disclosed. The LDD has been modified from a single layer of N type material to a stack of three layers. These are upper and lower N type layers with a P type layer between them. The upper N type layer is heavily doped to reduce the on-resistance of the device, while the lower N type layer is lightly doped to reduce the output capacitance, thereby improving the high frequency performance. The middle P layer is heavily doped which allows it to bring about pinch-off of the two N layers, thereby raising the device's breakdown voltage. A process for manufacturing the device, as well as experimental data concerning its performance are also given.

Abstract: A MOS transistor and a method for fabricating the MOS transistor which includes the forming a gate electrode containing an HLD film; etching the HLD film; etching a pad oxide film formed at a lower portion of the HLD film at a predetermined thickness; removing the nitride side wall spacer of an opening in the gate electrode; forming a LDD region by implanting impurity ions into the semiconductor substrate at both sides of the gate electrode; forming a side wall spacer at both sides of the gate electrode; and forming a source/drain by implanting impurity ions into the semiconductor substrate.

Abstract: There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion.

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract: A method of fabricating a MOS transistor. First, a substrate having a gate electrode and spacers on the gate electrode sidewalls is provided. A source/drain region is formed in the substrate outside the outer edge of the spacer sidewalls. A self-aligned silicide layer is formed over the exposed surface of the gate electrode and the source/drain regions. A portion of the spacers is removed by etching to form a sharp-angled triangular spacer on the sidewalls of the gate electrode. A pocket implantation of the substrate is carried out to form a pocket region inside the substrate under the side edges of the gate electrode. By controlling the setting of the energy level and the implant angle in the pocket implantation, a precise distribution of the dopants at desired locations within the substrate is reproduced. Finally, the sharp-angled spacers are removed and then a light implantation is conducted to form source/drain extension regions in the substrate on each side of the gate electrode.

Abstract: A method of fabricating a flash memory is disclosed. The method begins a stacked gate on the substrate. A shallow junction doping is performed on a substrate having a stacked gate already formed thereon, with the stacked gate serving as a mask, so as to form a shallow junction doped region in the substrate adjacent to both sides of the stacked gate. A mask layer is formed on the substrate to cover a top surface and sidewalls of the stacked gate, while exposing portions of the shallow junction doped region. With the mask layer serving as a mask, a deep junction doping is performed on the substrate to form a deep junction doped region in the substrate adjacent to both sides of the mask layer. After the mask layer is removed, a thermal process is performed to form a source/drain region having both the shallow junction doped region and deep junction doped region.

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N− LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

Abstract: A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a source/drain region in the substrate beside the spacer. A self-aligned silicide layer is further formed on the gate and the source/drain region. A portion of the spacer is removed to form a triangular spacer with a sharp corner, followed by performing a tilt angle implantation on the substrate to form a source/drain extension region in the substrate under the side of the gate and the spacer with the sharp corner. A thermal cycle is further conducted to adjust the junction depth and the dopant profile of the source/drain extension region.

Abstract: A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of Gn+2Sn are formed on n-channel transistor gate structures and an N+ implant is performed to form N+ implant is performed to form N+ regions in the n-channel substrate region. Resist spacers having a dimension of Gs +2Sp are formed on p-channel transistor gate structures and a P+ implant is performed to form P+ regions in the p-channel substrate region.

Abstract: The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A layer formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls the first conductive layer. Doped dielectric sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the doped dieletric sidewall spacers.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A method for forming of a self-aligned polysilicon gate MOSFET with silicon oxide shallow trench isolation is described wherein a hardmask is used to etch the polysilicon gate electrode. The hardmask is formed of a material which has a significantly high etch rate in dilute HF than the trench isolation so that the residual hardmask may be later removed with minimal attack of the shallow trench oxide which is also exposed to the aqueous etch. The preferred hardmask material is a borophosphosilicate glass (BPSG), although a phosphosilicate glass PSG may be used as well. The BPSG erodes at about the same rate as a silicon oxide hardmask during the polysilicon etch but offers the advantage of a higher aqueous HF etch rate during hardmask removal. The BPSG hardmask is left in place during LDD sidewall spacer formation and is removed just prior to the source/drain ion implantation.

Abstract: The present invention provides a semiconductor device having: at least a first diffusion layer having a first impurity concentration; at least a second diffusion layer having a first impurity concentration which is lower than the first impurity concentration, and the first and second diffusion layers being of the same conductivity type, wherein a silicide layer is formed over the first diffusion layer, while no silicide layer is formed over the second diffusion layer.

Abstract: A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by ion implantation. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, second amorphous regions and second inactive dopant regions are created in the substrate by ion implantation. Dopants in the first and second inactive dopant regions are then activated using a low temperature annealing process to create source/drain regions and source/drain extension regions. The aforementioned process simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.

Abstract: A semiconductor device which is applied to access transistors of an SRAM cell to improve its operation performance and a method for fabricating the same are disclosed. The semiconductor device includes a gate insulating layer formed on a semiconductor substrate, a gate electrode formed on the gate insulating layer, lightly doped impurity regions having different lengths beneath surface of the semiconductor substrate at first and second sides of the gate electrode, and heavily doped impurity regions formed beneath the surface of the semiconductor substrate, extending from the lightly doped impurity regions.

Abstract: A method of making a semiconductor device includes performing a doping implant through a layer of dielectric material. The implanting through dielectric material enables use of high-energy implants to form shallow doped regions. Other implanting steps may also be combined with the implanting through the dielectric material.

Abstract: A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light second conductive type ions are implanted into the substrate with the polysilicon layer as a mask. An insulation layer is formed to cover a side wall of the polysilicon layer. A first step heavy of ion implantation with second conductive type ions is perform to the substrate using the polysilicon layer and the spacer as mask, so that a heavily doped region is formed. A second step of heavy ion implantation with the second conductive type ions is performed to the substrate using the polysilicon layer and the spacer as masks, so that the heavily doped region is broadened and deepened with a smooth ion distribution profile.

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract: A process for fabricating an EEPROM device having pocket substrate regions includes forming a pattern composite layer overlying a principal surface of a semiconductor substrate. The pattern composite layer includes a dielectric layer and a resist layer overlying the dielectric layer. Processing is carried out to reduce the lateral dimension of the resist layer relative to the dielectric layer thereby exposing an upper surface of the dielectric layer. A doping process is carried out in which dopants penetrate the exposed upper surface of the dielectric layer and enter the semiconductor substrate immediately below the exposed upper surface of the dielectric layer. Upon conforming the pocket regions, an oxidation process is carried out to form bit-line oxide regions in the semiconductor substrate.

Abstract: For fabricating a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate, a hardmask dielectric material covers a top surface of the gate structure. A drain silicide is formed with a drain contact junction that is exposed, and a source silicide is formed with a source contact junction that is exposed. The drain silicide and the source silicide have a first thickness and are comprised of a first silicide material. The hardmask dielectric material that covers the top surface of the gate structure prevents formation of silicide with the gate structure during formation of the drain silicide and the source silicide. An encapsulating dielectric material is then deposited to cover the drain silicide and the source silicide using a low temperature of less than about 400° Celsius. The hardmask dielectric material is etched away from the top surface of the gate structure to expose the top surface of the gate structure.

Abstract: A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.

Abstract: A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.

Abstract: An ESD protected structure and method of its fabrication are disclosed. A heavily doped polycrystalline silicon region of a first conductivity type is disposed on a substrate surface and is connected to a power supply voltage. A lightly doped region, of the first conductivity type, is disposed below the substrate surface and below the polycrystalline silicon region. A first heavily doped region, of the first conductivity type, of a first MOS device is disposed below the substrate surface, and contained entirely within the lightly doped region. A second heavily doped region, of the first conductivity type, of a second MOS device, is disposed below the substrate surface, and separated from the first region by a portion of the lightly doped region and a second conductivity type doped portion of the substrate.

Abstract: The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a semiconducting substrate, forming a recess in said substrate proximate said gate stack, and performing an implantation process to implant dopant atoms into the bottom surface of the recess. The method further comprises forming a layer of epitaxial silicon in the recess, performing a second ion implantation process to form a doped region in at least the epitaxial silicon in the recess, and performing an anneal process to activate the implanted dopant atoms.

Abstract: The present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source. The third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.

Abstract: A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively implants the polysilicon layer that forms the gates of the analog transistors so that the doping concentration of the analog gates is greater than the doping concentration of the digital gates.

Abstract: A method of fabricating an integrated circuit (10, 51, 61, 71, 81, 91) includes forming on the upper surface (13) of a substrate (12) a part (18) which has thereon a side surface (19). A plurality of sidewalls (22, 27 and 83-84) are then formed in succession, outwardly from the side surface. A plurality of successive implants (21, 26, 31, 73-74, 87-88, 93-94) are introduced into the substrate, where a respective different subset of the sidewalls is present when each implant is created. The formation of sidewalls and implants may be carried out in an alternating manner, followed by removal of the sidewalls. Alternatively, removal of the sidewalls and formation of the implants may be carried out in an alternating manner. The width of each sidewall may be sublithographic, and the cumulative width of all sidewalls may be sublithographic.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-15 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: The present invention provide a method for reducing the sheet resistance of the buried layer serving as the bit line or an interconnect of a semiconductor device. The method includes steps of providing the silicon substrate, doping the silicon substrate for forming an extrinsic silicon region, and forming a silicide layer on the extrinsic silicon region for obtaining a low-resistance buried layer.

Abstract: A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is formed on the substrate and on sidewalls of the first conductive layer. Sidewall spacers are formed on sidewalls of the gate structure. The thermal oxide layer uncovered by the sidewall spacers is removed. The substrate is isotropically etched to form recessed regions on the substrate in regions uncovered by the gate structure and the sidewall spacers. A first metal layer is formed on the substrate after the first dielectric layer is removed. A source/drain/gate implantation is performed to the substrate, thereby forming source/drain regions under the recessed regions.

Abstract: A method of manufacturing a semiconductor device comprises providing on a semiconductor substrate a mask pattern having a fully opened region and a partially opened region. Impurities are selectively introduced into an impurity introduction region of the semiconductor substrate through the fully opened region and the partially opened region of the mask pattern to form areas having high and low impurity densities in the impurity introduction region.

Abstract: A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, the first silicon layer, and the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the first dielectric layer is removed. A second silicon layer is formed on the semiconductor substrate and on the first silicon layer. Another doping step is performed to dope the second silicon layer. A series of process is then performed to form a metal silicide layer on the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A method for fabricating a semiconductor substrate includes forming a silicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.

Abstract: A method of manufacturing a semiconductor device having shallow p-n junctions and silicide regions, capable of meeting both requirements of a high annealing temperature and a low annealing temperature. A lamination of two films made of materials having different etching characteristics is formed on the surface of a silicon substrate, covering an insulated gate electrode structure. The upper film is anisotropically etched to form side wall spacers. Impurity ions are implanted into a surface layer of the silicon substrate and sufficiently activated to a first level. The lower film is removed by using as a mask the side wall spacers, and a metal film capable of being silicided is deposited to perform a first silicidation reaction. The insulated gate electrode is exposed and impurity ions are implanted shallowly in the surface layer of the silicon substrate.

Abstract: A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

Abstract: The present invention provides a method for making a HVMOS transistor on a SOI substrate. The method according to the present invention involves forming a plurality of shallow trench isolations (STI) and at least one active area isolated by each shallow trench isolation on the SOI substrate. Then, two unneighboring field oxide layers and a gate are formed on the surface of the active area, with a portion of the gate covering the two field oxide layers. Thereafter, two double diffuse drains(DDD) are formed on the surface of the active area not covered by the gate and the two field oxide layers. Finally, a drift region of the HVMOS transistor is formed at the bottom of the two field oxide layers.

Abstract: An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced.

Abstract: A high-voltage lateral double-diffused metal oxide semiconductor has a field metal plate or an electrical field shield conductive layer, which is electrically coupled with a gate or a gate conductive layer that lies over a field oxide layer. A wire bridges over the field oxide layer and thus decreases the strength of the electrical field. The field oxide layer under the crossing wire has no drift region below. Therefore, the electrical field crowding effect does not occur at the junction between the drift region and the channel. In addition, there is no wire over the field oxide layer having the drift region below. Thus, the components can work normally. In this way, the strength of electrical field between the drift region and the channel decreaes and the breakdown voltage of high-voltage lateral double-diffused metal oxide semiconductor increases.

Abstract: A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region.

Abstract: The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.