Radiation Or Energy Treatment Modifying Properties Of Semiconductor Regions Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) Patents (Class 438/308)
  • Patent number: 6767804
    Abstract: A pan/tilt camera system includes a sensor spaced from a rotational shaft of a pan/tilt camera, a detected piece rotated with the rotational shaft so as to correspond to the sensor, an origin setting unit rotating the rotational shaft in a first direction upon turn-on of a power and thereafter in a second direction opposite to the first direction so that the sensor detects a rear end of the detected piece for setting an origin, a pulse counter applying a predetermined number of pulses to the motor after set of the origin so that the rotational shaft is continuously rotated in the second direction and counting pulses applied to the motor until a front end of the detected piece with respect to the rotation direction of the detected piece is detected, and a backlash calculating unit comparing a count of the pulse counter with the predetermined number of pulses applied to the motor thereby to calculate an amount of backlash of the drive mechanism.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: July 27, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Mark Albert Crowder
  • Patent number: 6767847
    Abstract: A method of forming a silicon nitride-silicon dioxide composite insulator layer for use as a gate insulator stack for an MOSFET device, has been developed. The method features formation of the silicon dioxide component of the gate insulator stack, after formation of the overlying silicon nitride component, allowing the gate insulator stack to be comprised with a nitrogen profile presenting enhanced barrier characteristic and less interface charge than counterpart silicon nitride-silicon dioxide composites formed wherein the silicon nitride component was deposited on an already grown underlying silicon dioxide layer. Oxygen ions, or oxygen radicals obtained via ultra-violet procedures, penetrate the silicon nitride component and locate in a top portion of the semiconductor substrate. Subsequent annealing allows reaction of the oxygen ions or radicals with a top portion of the semiconductor substrate resulting in the desired silicon dioxide component underlying silicon nitride.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: July 27, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chien-Ming Hu, Chien-Hao Chen, Mo-Chiun Yu, Shih-Chang Chen, Mong-Song Liang
  • Publication number: 20040137760
    Abstract: In a thin film processing method and system, a film thickness is regulated by using electron beams irradiated from a plurality of electron beam tubes onto a film of varying thickness formed on an object to be processed, wherein the output powers or beam irradiation times of the electron beam tubes are individually controlled according to a distribution of the thickness. In the method and system, electric charges charged in a film of an object to be processed can be removed also.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 15, 2004
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tadashi Onishi, Manabu Hama, Minoru Honda, Kazuyuki Mitsuoka, Mitsuaki Iwashita
  • Publication number: 20040121543
    Abstract: First, an first insulating film is formed along surfaces of a plurality of combinations of an gate electrode and an gate insulating films, and a semiconductor substrate, respectively. Then, on the first insulating film, an second insulating film different from the first insulating film is formed. The steps of forming the first insulating film and forming the second insulating film are alternately repeated until a concave formed by the surface of an later insulating film, which is a film formed later out of the first insulating film and the second insulating film, is positioned above the upper surface of the gate electrode. Thereafter, an third insulating film is formed on the later insulating film. Thus, a semiconductor device with high reliability can be obtained by improving a state of the insulating film formed between the gate electrodes.
    Type: Application
    Filed: December 12, 2003
    Publication date: June 24, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Yoshihiro Miyagawa
  • Publication number: 20040121529
    Abstract: A method of forming a buffer dielectric film in a semiconductor device and a method of manufacturing a thin film transistor using the same are disclosed.
    Type: Application
    Filed: October 2, 2003
    Publication date: June 24, 2004
    Inventors: Choong Yong Sohn, Yong Hae Kim, Jin Ho Lee, Young Wook Ko, Choong Heui Chung
  • Publication number: 20040115871
    Abstract: The method for fabricating a semiconductor device comprises the step of: forming a gate electrode on a semiconductor substrate with a gate insulation film formed therebetween; the step of implanting a dopant in the semiconductor substrate with the gate electrode as a mask to form a dope region in the semiconductor substrate; the step of forming a chemical oxide film on the doped region, which prevents the dopant implanted in the doped region from diffusing outside the semiconductor substrate; and the step of performing thermal processing for activating the dopant implanted in the doped region.
    Type: Application
    Filed: September 30, 2003
    Publication date: June 17, 2004
    Inventor: Tomokazu Kawamoto
  • Publication number: 20040115869
    Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes.
    Type: Application
    Filed: November 26, 2003
    Publication date: June 17, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Hidekazu Miyairi
  • Publication number: 20040115889
    Abstract: The invention describes a method for forming ultra shallow junction formation. Dopant species are implanted into a semiconductor. Solid phase epitaxy anneals and subsequent ultra high temperature anneals are performed following the implantation processes.
    Type: Application
    Filed: November 25, 2003
    Publication date: June 17, 2004
    Inventors: Amitabh Jain, Lance S. Robertson
  • Patent number: 6750101
    Abstract: A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines. Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process. The memory cells comprise structures including a selection device, a heating/barrier plate layer and a phase change memory element, vertically arranged at the intersections of the bit lines and word lines.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: June 15, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 6746912
    Abstract: A downsized, high-capacity MIM capacitor provided on a compound semiconductor includes a lower electrode comprising a plurality of metal layers including a top layer, an upper electrode, and a dielectric layer positioned between the lower electrode and the upper electrode. The entire surface of the top metal layer is oxidized to form an insulating metal oxide layer.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: June 8, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hidefumi Nakata
  • Patent number: 6743680
    Abstract: A method of manufacturing an integrated circuit includes providing an amorphous semiconductor material including germanium, annealing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: June 1, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Yu
  • Patent number: 6734081
    Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. A trench is etched in the integrated circuit substrate. A light barrier layer is then formed in the trench such that the light barrier layer at least partially fills the trench to create an isolation structure, the light barrier layer being adapted for absorbing laser light applied during laser thermal processing, thereby preventing damage to the integrated circuit substrate. For instance, the light barrier layer may be a conductive layer such as polysilicon. A dielectric layer is then formed over the isolation structure. The dielectric layer may be adapted for transferring heat generated by the laser thermal processing to the light barrier layer. For instance, the dielectric layer may be formed through oxidation of a top surface of the light barrier layer.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: May 11, 2004
    Assignee: LSI Logic Corporation
    Inventors: Helmut Puchner, Venkatesh P. Gopinath
  • Publication number: 20040087069
    Abstract: In crystallizing an amorphous silicon film by illuminating it with linear pulse laser beams having a normal-distribution type beam profile or a similar beam profile, the linear pulse laser beams are applied in an overlapped manner. There can be obtained effects similar to those as obtained by a method in which the laser illumination power is gradually increased and then decreased in a step-like manner in plural scans.
    Type: Application
    Filed: June 25, 2003
    Publication date: May 6, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japan Corporation
    Inventors: Naoto Kusumoto, Koichiro Tanaka
  • Patent number: 6730566
    Abstract: A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Rajesh Khamankar, Husam N. Alshareef
  • Publication number: 20040082201
    Abstract: A method of treating an electrically non-conductive tunnel barrier layer through an overlayer of a tunnel junction device with ultra-violet light is disclosed. The method includes irradiating a tunnel barrier layer with ultra-violet light through at least one overlayer that covers the tunnel barrier layer to activate oxygen or nitrogen atoms disposed in the barrier layer so that those atoms will react with a target material of the tunnel barrier layer to form a uniformly oxidized or nitridized tunnel barrier layer having minimal or no defects therein and/or a desired breakdown voltage. The ultra violet light can irradiate the tunnel barrier layer during or after the formation of the overlayer. Heat can be applied before, during, or after the irradiation step to increase the activation rate and to further reduce defects. The method is applicable to any tunnel junction device including a magnetic field sensitive memory device such as a MRAM.
    Type: Application
    Filed: October 29, 2002
    Publication date: April 29, 2004
    Inventors: Manish Sharma, Trueman H. Denny
  • Publication number: 20040077149
    Abstract: A method and system can compensate for anneal non-uniformities by implanting dopant in a pattern to provide higher dopant concentrations where the anneal non-uniformities result in lower active dopant concentrations. A pattern for the anneal non-uniformities may be determined by annealing a wafer having a uniform dopant distribution and measuring properties of the wafer after annealing, e.g., by obtaining a sheet resistance map of the wafer. In one embodiment, the non-uniformities may be measured by measuring temperature variations during annealing.
    Type: Application
    Filed: October 16, 2002
    Publication date: April 22, 2004
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Anthony Renau
  • Patent number: 6723666
    Abstract: Gate oxide surface irregularities, such as surface roughness, are reduced by treatment with an oxygen-containing plasma. Embodiments include forming a gate oxide layer and then treating the formed gate oxide layer with an oxygen plasma to repair weak spots and fill in pin holes and surface irregularities, thereby reducing gate/gate oxide interface roughness.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Philip A. Fisher
  • Publication number: 20040063290
    Abstract: A method including introducing a species into a substrate including semiconductor material; and translating linearly focused electromagnetic radiation across a surface of the substrate, the electromagnetic radiation being sufficient to thermally influence the species. An apparatus including an electromagnetic radiation source; a stage having dimensions suitable for accommodating a semiconductor substrate within a chamber; an optical element disposed between the electromagnetic radiation source and the stage to focus radiation from the electromagnetic radiation source into a line having a length determined by the diameter of a substrate to be placed on the stage; and a controller coupled to the electromagnetic radiation source including machine readable program instructions that allow the controller to control the depth into which a substrate is exposed to the radiation.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Dean C. Jennings, Amir Al-Bayati
  • Publication number: 20040058501
    Abstract: A method for adiabatically heating semiconductor device surfaces, including using capping layers to prevent deformation of surfaces. Using the method, semiconductor surfaces having varying topographies or topologies may be heated adiabatically. In an embodiment of the method, one or more capping layers may be formed over a semiconductor surface, to further prevent deformation of semiconductor surfaces.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 25, 2004
    Inventors: Jose A. Maiz, Sarangapani Sista, Mark Liu
  • Patent number: 6709960
    Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode oxide over a substrate; depositing a first layer of polysilicon over the gate oxide; implanting dopants in the first layer; depositing a second layer of polysilicon over the first layer; etching both layers to form a gate electrode; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate; and laser thermal annealing to activate the source/drain regions and to melt the first layer. The first layer can have a depth of about 200 to 500 angstroms, and the second layer can have a depth of about 300 to 4500 angstroms. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The laser thermal annealing can also melt amorphitized portions of the second layer.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: March 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Qi Xiang
  • Patent number: 6706568
    Abstract: A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the surface of the semiconductor layer and a gate insulating film, in order to achieve a TFT having a good characteristic. In an atmosphere of one kind or a plural kinds of gas selected from hydrogen or inert gas (nitrogen, argon, helium, neon, krypton and xenon), radiation with a laser beam in the first, second and third conditions is carried out in order, wherein the first condition laser beam is radiated for crystallizing a semiconductor film or improving a crystal characteristic; the second condition laser beam is radiated for eliminating an oxide film; and the third condition laser beam is radiated for leveling a surface of the crystallized semiconductor film.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: March 16, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Setsuo Nakajima
  • Publication number: 20040043575
    Abstract: A substrate to be processed in a high temperature processing chamber is preheated to avoid the problems associated with thermal shock when the substrate is dropped onto a heated susceptor. Preheating is effected by holding the substrate over a susceptor maintained at or near the processing temperature until the temperature of the substrate approaches the processing temperature. Thus, wafer warping and breakage are greatly reduced, and wafer throughput is improved because of time saved in maintaining the susceptor at constant temperature without cool down and reheat periods.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 4, 2004
    Inventors: Paul Jacobson, Ivo Raaijmakers, Ravinder Aggarwal, Robert C. Haro
  • Publication number: 20040029049
    Abstract: A method for fabricating a Mask ROM with self-aligned coding is described. A plurality of buried bit lines are formed in a substrate, and then a plurality of word lines are formed on the substrate crossing over the buried bit lines with first blocking strips thereon. A plurality of second blocking strips are formed between the word lines and between the first blocking strips, and then the first blocking strips are patterned into an array of blocking bumps, which define a plurality of pre-coding windows with the second blocking strips. A coding mask layer is formed on the substrate with a plurality of coding windows therein exposing selected pre-coding windows, and then a coding implantation is performed to form implanted coding regions in the substrate under the selected pre-coding regions exposed by the coding windows. The coding mask layer is then removed.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 12, 2004
    Inventors: Chun-Yi Yang, Ta-Hung Yang
  • Patent number: 6680242
    Abstract: A method of forming a crystalline semiconductor thin film on a base material which can be prepared at a low temperature by simple step and device, the method including a processing step of applying UV-rays to an amorphous semiconductor thin film provided on a base material while keeping a temperature at not less than 25° C. and not more than 300° C. in a vacuum or a reducing gas atmosphere, as well as a substrate having the semiconductor thin film provided on the base material, a substrate for forming a color filter and a color filter using the substrate.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: January 20, 2004
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigemi Ohtsu, Keishi Shimizu, Kazutoshi Yatsuda, Eiichi Akutsu
  • Patent number: 6677213
    Abstract: A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: January 13, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventors: Krishnaswamy Ramkumar, Frederick B. Jenne
  • Patent number: 6660575
    Abstract: A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type to diffuse said impurity into a region of said semiconductor.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: December 9, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 6660543
    Abstract: The present invention is directed to several inventive methods for characterizing implant profiles. In one embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating at least one profile trace corresponding,to an anticipated profile of the implant region, wherein, in creating the profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to at least one created profile trace.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: December 9, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Broc Stirton, Kevin R. Lensing, Homi E. Nariman, Steven P. Reeves
  • Patent number: 6660606
    Abstract: The number of defects (HF defects) in the SOI layer of an SOI substrate is reduced. In an annealing method of annealing an SOI substrate in a reducing atmosphere at a temperature equal to or less than the melting point of a semiconductor, annealing is executed in a state wherein a flow of a reducing atmospheric gas parallel to the surface of the SOI substrate is generated near this surface.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: December 9, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroshi Miyabayashi, Nobuhiko Sato, Masataka Ito
  • Publication number: 20030219936
    Abstract: A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.
    Type: Application
    Filed: April 22, 2003
    Publication date: November 27, 2003
    Inventor: Sang-Hyun Kim
  • Publication number: 20030219950
    Abstract: Semiconductor device annealing process with deuterium at superatmospheric pressures to improve reduction of the effects of hot carrier stress during device operation, and devices produced thereby.
    Type: Application
    Filed: July 24, 2002
    Publication date: November 27, 2003
    Inventors: Joseph W. Lyding, Karl Hess, Jinju Lee
  • Patent number: 6649537
    Abstract: The present invention provides a method of forming a dielectric on a semiconductor substrate. A dielectric is grown at a substrate interface in a plurality of increments. Stress is relieved at the dielectric substrate interface between each increment. In another aspect, stress relief is performed by annealing the substrate. The annealing is performed by placing the substrate in an inert environment and by raising the temperature surrounding the substrate.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: November 18, 2003
    Assignee: LSI Logic Corporation
    Inventors: Steven E. Reder, Hemanshu D. Bhatt
  • Patent number: 6645834
    Abstract: Provided is a manufacturing process for an annealed wafer capable of elucidating a relationship between a tilt angle from a (100) plane of a wafer to be annealed and haze to set optimal tilt angles for suppression of haze and to improve a characteristic of a device from the annealed wafer as a result of the suppression of haze. A silicon mirror wafer having a surface orientation with a tilt angle in the range of 0.1 degree<&thgr;<0.2 degree from a (100) plane or a plane equivalent thereto is heat treated in an atmosphere of hydrogen gas, an inert gas, nitrogen gas or a mixed gas thereof.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: November 11, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: 6642118
    Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of the polysilicon residue. An oxygen anneal step is subsequently performed to completely convert the rich oxygen containing polysilicon residue into silicon dioxide that can eliminate the conductivity of the polysilicon residue and prevent oxygen encroachment occurring.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: November 4, 2003
    Assignee: Mactronix International Co., Ltd.
    Inventors: Chun-Lien Su, Chun-Chi Wang, Ming-Shang Chen
  • Publication number: 20030203549
    Abstract: There are disposed two homogenizers for controlling an irradiation energy density in the longitudinal direction of a laser light transformed into a linear one which is inputtted into the surface to be irradiated. Also, there is disposed one homogenizer for controlling an irradiation energy density in a width direction of the linear laser light. According to this, the uniformity of laser annealing can be improved by the minimum number of homogenizers.
    Type: Application
    Filed: May 15, 2003
    Publication date: October 30, 2003
    Applicant: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka, Satoshi Teramoto
  • Publication number: 20030203517
    Abstract: Disclosed is a technique capable of preventing the breakage of a semiconductor wafer with a diameter of 300 mm in an RTP equipment. When the RTP process composed of a heating process, a main process for maintaining the predetermined final temperature for a predetermined time, and a cooling process is performed to a semiconductor wafer with a diameter of 300 mm, the temperature of the semiconductor wafer is measured by the use of pyrometers, an open-loop control in which the difference in the in-plane temperature of a semiconductor wafer is controlled within 90° C. is performed in the heating process at a temperature lower than 500° C., and a closed-loop control is performed in the heating process at a temperature of 500° C. or higher and in the main process. In this manner, it is possible to reduce the warp of the semiconductor wafer and to prevent the breakage thereof.
    Type: Application
    Filed: February 6, 2003
    Publication date: October 30, 2003
    Inventors: Tadashi Suzuki, Tadami Ishida, Mikio Shimizu
  • Patent number: 6639228
    Abstract: A method for estimating molecular nitrogen implantation dosage. The semiconductor wafers are first implanted with various concentration of molecular nitrogen. After implantation, the implanted wafers and a non-implanted wafer are subjected to thermal process to grow oxide layer. The thickness of oxide layer on the wafers with various implantation dosage is measured. Because implanted nitrogen on the wafers suppresses the growth of oxide layer, a suppression ratio is computed from the difference in thickness of the oxide layer between the implanted and non-implanted semiconductor wafers to stand for the thickness variation. Then, a relation between the suppression ratio and the dosages of molecular nitrogen is built. A molecular nitrogen dosage needed to grow a predetermined thickness of oxide layer on a process wafer is computed by inputting the predetermined thickness into the relation.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: October 28, 2003
    Assignee: Promos Technologies Inc.
    Inventor: Chun-Yao Yen
  • Patent number: 6638800
    Abstract: A laser processing process which comprises laser annealing a silicon film 2 &mgr;m or less in thickness by irradiating at laser beam 400 nm or less in wavelength and being operated in pulsed mode with a pulse width of 50 nsec or more, and preferably, 100 nsec or more. A laser processing apparatus which comprises a laser generation device and a stage for mounting thereon a sample provided separately from said devices to thereby prevent transfer of vibration attributed to the movement of the stage to the laser generation device and the optical system. A stable laser beam can be obtained to thereby improve productivity.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: October 28, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroaki Ishihara, Kazuhisa Nakashita, Hideto Ohnuma, Nobuhiro Tanaka, Hiroki Adachi
  • Patent number: 6635541
    Abstract: A method of the invention comprises forming a partial absorber layer (PAL) over at least one integrated transistor device formed on a semiconductor substrate, and exposing the PAL to radiant energy. A first portion of the radiant energy passes through the PAL and is absorbed in the source and drain regions adjacent a gate region of the integrated transistor device and in the semiconductor substrate underneath the field isolation regions of the integrated device. A second portion of the radiant energy is absorbed by the PAL and is thermally conducted from the PAL to the source and drain regions. The first and second portions of the radiant energy are sufficient to melt the source and drain regions to anneal the junctions of the integrated device.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: October 21, 2003
    Assignee: Ultratech Stepper, Inc.
    Inventors: Somit Talwar, Yun Wang, Carol Gelatos
  • Patent number: 6635587
    Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: October 21, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Joseph C. Holzer
  • Patent number: 6636280
    Abstract: A liquid crystal display device is provided with a pixel area on a substrate having plural gate lines, plural drain lines, plural thin film transistors and plural pixel electrodes corresponding to the plural thin film transistors, and a drive circuit area disposed at a periphery of the substrate and having a drive circuit for driving the plural thin film transistors. The thin film transistor has a polycrystalline silicon semiconductor layer formed on the substrate, a gate electrode formed on the polycrystalline silicon semiconductor layer with a gate insulating film interposed therebetween, an insulating film to cover the polycrystalline silicon semiconductor layer, the gate insulating film and the gate electrode, a drain electrode formed on the insulating film and electrically connected to the polycrystalline silicon semiconductor layer, and a source electrode formed on the insulating film, spaced from the drain electrode and electrically connected to the polycrystalline silicon semiconductor layer.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Miyazawa, Akio Mimura
  • Publication number: 20030190797
    Abstract: There is provided an optical system for reducing faint interference observed when laser annealing is performed to a semiconductor film. The faint interference conventionally observed can be reduced by irradiating the semiconductor film with a laser beam by the use of an optical system using a mirror of the present invention. The optical system for transforming the shape of the laser beam on an irradiation surface into a linear or rectangular shape is used. The optical system may include an optical system serving to convert the laser beam into a parallel light with respect to a traveling direction of the laser beam. When the laser beam having passed through the optical system is irradiated to the semiconductor film through the mirror of the present invention, the conventionally observed faint interference can be reduced. Besides, the optical system which has been difficult to adjust can be simplified.
    Type: Application
    Filed: April 4, 2003
    Publication date: October 9, 2003
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Tomoko Nakaya
  • Patent number: 6627489
    Abstract: A method for making CMOQ transistors and associated devices. The method is used to make transistors of a first type and a second type in CMOS technology in an active layer. The method etches regions of the active layer or making them inactive so as to define active islands designed to form sources, channels of determined width, and drains of the transistors of the first type and second type respectively, covers at least two active islands with an insulating layer and covers the insulating layer with a conductive layer, and sequentially etches all the gates of the transistors of the first type and then all the gates of the transistors of the second type. The associated devices includes CMOS transistor devices obtained by the method. Such a method may particularly find application to devices for the addressing and control of active matrix liquid crystal displays.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: September 30, 2003
    Assignee: Thomson-CSF
    Inventors: François Plais, Carlo Reita, Odile Huet
  • Patent number: 6624037
    Abstract: A SOI substrate is preamorphized by ion implanting Xe prior to forming source/drain extensions and source/drain regions, thereby virtually eliminating or significantly reducing floating body effects. Other aspects comprise ion implanting a Xe2+ into a bulk silicon or SOI substrate to effect preeamorphization prior to forming source/drain extensions and regions having shallow junctions with reduced vertical and lateral straggle.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: September 23, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew Stephen Buynoski, Che-Hoo Ng
  • Patent number: 6613619
    Abstract: In producing a semiconductor device by annealing with laser light irradiation, while a linear laser light is scanned in a direction perpendicular to a line, the annealing is performed for a semiconductor material. In this state, since an anneal effect in a beam lateral direction corresponding to a line direction is 2 times or more different than that in the scanning direction, a plurality of semiconductor elements are formed along a line direction in which the linear laser light is irradiated. Also, a line direction connecting the source and drain region of a thin film transistor is aligned to the line direction of the linear laser light.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: September 2, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoto Kusumoto, Koichiro Tanaka
  • Patent number: 6613638
    Abstract: The HF defect density in an SOI is reduced. After annealing step (S2) of annealing an SOI at a temperature between the melting point (e.g., 993° C.) of a semiconductor metal compound (e.g., nickel silicide) formed from a metal and the semiconductor material of the crystal semiconductor of the SOI (inclusive) and the melting point of the semiconductor material (inclusive), the temperature is reduced such that the cooling rate within the temperature range from the melting point of the semiconductor metal compound and the production temperature (e.g., 775° C.) of the semiconductor metal compound becomes 0.12° C./sec or more.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: September 2, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masataka Ito
  • Patent number: 6602742
    Abstract: An electric double layer capacitor including at least one pair of polarizable electrodes connected to current collectors, a separator made of ion-permeable but electron-insulating material interposed between the electrodes in each pair of electrodes, and a liquid electrolyte. According to the invention the electrodes include a layer of carbon particles having a narrow distribution of nanopores therein, the pore sizes of the nanopores being adapted to fit the ion sizes of the electrolyte. The invention also relates to a method of manufacturing such a supercapacitor.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: August 5, 2003
    Assignee: FOC Frankenburg Oil Company Est.
    Inventors: Yurii Maletin, Natalie Strizhakova, Sergey Kozachkov, Antonina Mironova, Sergey Podmogilny, Valerii Danilin, Julia Kolotilova, Volodymyz Izotov, Jan Cederström, Sergey Gordeev Konstantinovich, Julia Kukushkina Aleksandrovna, Vasilii Sokolov Vasilevitj, Alexander Kravehik Efimovitj, Anti Perkson, Mati Arulepp, Jaan Leis, Clarence L. Wallace, Jie Zheng
  • Patent number: 6599790
    Abstract: A laser-irradiation method which comprises a process for fabricating a semiconductor device, comprising: a first step of forming a thin film amorphous semiconductor on a substrate having an insulating surface; a second step of modifying the thin film amorphous semiconductor into a crystalline thin film semiconductor by irradiating a pulse-type linear light and/or by applying a heat treatment; a third step of implanting an impurity element which imparts a one conductive type to the crystalline thin film semiconductor; and a fourth step of activating the impurity element by irradiating a pulse-type linear light and/or by applying a heat treatment; wherein the peak value, the peak width at half height, and the threshold width of the laser energy in the second and the fourth steps above are each distributed within a range of approximately ±3% of the standard value. Also claimed is a laser irradiation device which realizes the method above.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: July 29, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Naoto Kusumoto, Takeshi Fukunaga, Setsuo Nakajima, Tadayoshi Miyamoto, Atsushi Yoshinouchi
  • Patent number: 6599820
    Abstract: A method of producing a semiconductor device having a polymetal wiring structure fabricated by a polycrystalline silicon film, a reaction preventing film, and a tungsten film comprising steps of forming a polycrystalline silicon film 4 and a tungsten nitride film 13 on a silicon substrate 1; forming a tungsten film 14 using a target of tungsten containing fluorine of 10 ppm or less by a sputtering method; and forming a gate electrode 15 by patterning a polycrystalline silicon film 4, the tungsten nitride film 13, and the tungsten film 14, whereby a content of fluorine can be reduced, a film separation is prevented, and a preferable transistor property is obtainable.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: July 29, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhiro Kanda, Mitsuo Kimoto, Kazuyoshi Maekawa, Noboru Sekiguchi
  • Patent number: 6593180
    Abstract: A method of manufacturing semiconductor device comprises the step of forming the transistor in the semiconductor substrate, the step of forming the capacitor conducting to the transistor, and the step of forming the insulating film to cover the transistor and the capacitor; and the step of sintering the semiconductor substrate in an atmosphere including the mixture of hydrogen, nitrogen and oxygen gases.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: July 15, 2003
    Assignees: Fujitsu Limited, Kabushiki Kaisha Toshiba
    Inventors: Jun Lin, Yoshiaki Fukuzumi
  • Patent number: 6582998
    Abstract: Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, after the first passivation film is removed, a second passivation film of silicon dioxide is deposited over the substrate as well as over a stacked cell electrode by a CVD process performed at a relatively low temperature. Thereafter, the substrate is annealed in a nitrogen ambient at such a temperature as activating the dopant introduced. In this manner, the dopant in source region and first drain region is activated.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: June 24, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toshinari Nitta