Ordered Or Disordered Patents (Class 438/36)
  • Patent number: 7842529
    Abstract: In a method for manufacturing a III-V nitride compound semiconductor light emitting element, light emitting element regions (21) are formed in a low dislocation region on the III-V nitride compound semiconductor substrate wherein high density dislocation sections (22) and low dislocation regions are alternately arranged repeatedly, so that stripe-shaped light emitting regions are in parallel to the direction wherein the high density dislocation sections (22) extend, and then the substrate is broken, after making two scribe lines (23) to have the high density dislocation section (22) in between, on a plane (25) on the opposite side to a plane (24) whereupon the element regions (21) are formed. Thus, chips are separated and the high density dislocation sections (22) can be removed. The pitch of the two scribe lines is preferably 100 ?m or more.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: November 30, 2010
    Assignees: Tottori Sanyo Electric Co., Ltd., Sanyo Electric Co., Ltd.
    Inventor: Katsunori Kontani
  • Patent number: 7821807
    Abstract: A photosensitive diode has an active region defining a majority carrier of a first conductivity type and a minority carrier of a second conductivity type. An extraction region is disposed on a first side of the active region and extracts minority carriers from the active region. It also has majority carriers within the extraction region flowing toward the active region in a condition of reverse bias. An exclusion region is disposed on a second side of the active region and has minority carriers within the exclusion region flowing toward the active region. It receives majority carriers from the active region. At least one of the extraction and exclusion region provides a barrier for substantially reducing flow of one of the majority carriers or the minority carriers, whichever is flowing toward the active region, while permitting flow of the other minority carriers or majority carriers flowing out of the active region.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: October 26, 2010
    Assignee: EPIR Technologies, Inc.
    Inventors: Silviu Velicu, Christoph H. Grein, Sivalingam Sivananthan
  • Patent number: 7794798
    Abstract: A method for depositing material on a substrate is described. The method comprises maintaining a reduced-pressure environment around a substrate holder for holding a substrate having a surface, and holding the substrate securely within the reduced-pressure environment. Additionally, the method comprises providing to the reduced-pressure environment a gas cluster ion beam (GCIB) from a pressurized gas mixture, accelerating the GCIB, and irradiating the accelerated GCIB onto at least a portion of the surface of the substrate to form a thin film. In one embodiment, the pressurized gas mixture comprises a silicon-containing specie and at least one of a nitrogen-containing specie or a carbon-containing specie for forming a thin film containing silicon and at least one of nitrogen or carbon. In another embodiment, the gas mixture comprises a metal-containing specie for forming a thin metal-containing film.
    Type: Grant
    Filed: September 29, 2007
    Date of Patent: September 14, 2010
    Assignee: TEL Epion Inc.
    Inventor: John J. Hautala
  • Patent number: 7776636
    Abstract: A method for reducing dislocation density between an AlGaN layer and a sapphire substrate involving the step of forming a self-organizing porous AlN layer of non-coalescing column-like islands with flat tops on the substrate.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: August 17, 2010
    Assignee: CAO Group, Inc.
    Inventor: Tao Wang
  • Patent number: 7767481
    Abstract: Disclosed are an image sensor and a method for manufacturing the same, capable of increasing a light absorbing coefficient by forming a rough surface on a photodiode. The image sensor includes a semiconductor substrate with a plurality of photodiodes thereon having rough upper surfaces, a dielectric layer on the semiconductor substrate, a color filter layer on the dielectric layer, a planarization layer on an entire surface of the semiconductor substrate including the color filter layer, and a plurality of micro-lenses formed on the planarization layer to correspond to the color filter layer.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: August 3, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Sang Chul Kim, Jae Won Han
  • Patent number: 7754504
    Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: July 13, 2010
    Assignee: Sony Corporation
    Inventors: Akira Ohmae, Shigetaka Tomiya, Yuki Maeda, Michinori Shiomi, Takaaki Ami, Takao Miyajima, Katsunori Yanashima, Takashi Tange, Atsushi Yasuda
  • Publication number: 20100155709
    Abstract: The present invention relates to an encapsulation for an electronic thin film device, comprising a first barrier layer (108), a second barrier layer (112), and a first planarization layer (110?) for reducing the formation of pinholes in a subsequent barrier layer, said first planarization layer (110?) arranged between the first barrier layer (108) and the second barrier layer (112), wherein the first planarization layer (110?) is composed of a first plurality of planarization segment (114) having areas formed between each other, and the encapsulation further comprises a second planarization layer (116) arranged between the second barrier layer (112) and a third barrier layer (120), wherein the second planarization layer (116) is composed of a second plurality of planarization segments (118) arranged to extend over the areas between the first plurality of planarization segments (114), thereby further reducing the number of pinholes providing passageways through the encapsulation.
    Type: Application
    Filed: May 21, 2008
    Publication date: June 24, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Martinus Jacobus Johannes Hack, Thomas Nicolaas Maria Bernards, Peter Van De Weijer
  • Patent number: 7723139
    Abstract: Embodiments of a method of quantum well intermixing (QWI) comprise providing a wafer comprising upper and lower epitaxial layers, which each include barrier layers, and a quantum well layer disposed between the upper and lower epitaxial layers, applying at least one sacrificial layer over the upper epitaxial layer, and forming a QWI enhanced region and a QWI suppressed region by applying a QWI enhancing layer over a portion of the sacrificial layer, wherein the portion under the QWI enhancing layer is the QWI enhanced region, and the other portion is the QWI suppressed region. The method further comprises the steps of applying a QWI suppressing layer over the QWI enhanced region and the QWI suppressed region, and annealing at a temperature sufficient to cause interdiffusion of atoms between the quantum well layer and the barrier layers of the upper epitaxial layer and the lower epitaxial layer.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: May 25, 2010
    Assignee: Corning Incorporated
    Inventors: Yabo Li, Kechang Song, Chung-En Zah
  • Publication number: 20100105158
    Abstract: A method of fabricating a semiconductor device having high output power and excellent long-term reliability by preventing thermal adverse influence exerted at the time of window structure formation is provided. The method comprises a 1st step of forming predetermined semiconductor layers 2 to 9 containing at least an active layer 4b consisting of a quantum well active layer on a semiconductor substrate 1; a 2nd step of forming a first dielectric film 10 on a first portion of the surface of the semiconductor layers 2 to 9; a 3rd step of forming a second dielectric film 12 made of the same material as that of the first dielectric film 10 and having a density lower than that of the first dielectric film 10 on a second portion of the surface of the semiconductor layers 2 to 9; and a 4th step of heat-treating a multilayer body containing the semiconductor layers 2 to 9, the first dielectric film 10, and the second dielectric film 12 to disorder the quantum well layer below the second dielectric film 12.
    Type: Application
    Filed: January 6, 2010
    Publication date: April 29, 2010
    Applicant: The Furukawa Electric Co., Ltd.
    Inventor: Yumi Yamada
  • Patent number: 7691728
    Abstract: A semiconductor device manufacturing method can produce semiconductor light emitting/detecting devices that have high connective strength and high luminous energy by increasing contact areas of electrodes thereof and decreasing enclosed areas of electrodes thereof. A wafer is provided with a semiconductor substrate and a semiconductor epitaxial layer. A plurality of substrate concave portions and epitaxial layer concave portions are formed on the semiconductor substrate and the semiconductor epitaxial layer, respectively. Substrate electrodes and epitaxial layer electrodes are formed in the substrate concave portions and the epitaxial layer concave portions. A substrate surface electrode and an epitaxial layer surface electrode can be formed on the semiconductor substrate and the substrate electrodes and the semiconductor epitaxial layer and the epitaxial layer electrodes, respectively.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yasuhiro Tada, Akihiko Hanya
  • Patent number: 7678597
    Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: March 16, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Ohtsuka, Yoichiro Tarui, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
  • Patent number: 7632695
    Abstract: A technique is provided which enables formation of nitride semiconductor layers with excellent flatness and excellent crystallinity on a gallium nitride substrate (GaN substrate), while improving the producibility of the semiconductor device using the GaN substrate. A gallium nitride substrate is prepared which has an upper surface having an off-angle of not less than 0.1° nor more than 1.0° in a <1-100> direction, with respect to a (0001) plane. Then, a plurality of nitride semiconductor layers including an n-type semiconductor layer are stacked on the upper surface of the gallium nitride substrate to form a semiconductor device such as a semiconductor laser.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 15, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihito Ohno, Masayoshi Takemi, Nobuyuki Tomita
  • Publication number: 20090230397
    Abstract: A display device includes a TFT substrate in which a plurality of first TFT elements each having an active layer of an amorphous semiconductor and a plurality of second TFT elements each having an active layer of a polycrystalline semiconductor are disposed on a surface of an insulating substrate, wherein the first TFT element and the second TFT element each have a structure with a gate electrode, a gate insulating film, and the active layer stacked in this order on the surface of the insulating substrate and a source electrode and a drain electrode both connected to the active layer via a contact layer above the active layer, and the active layer of the second TFT element has a thickness of more than 60 nm in a position where the contact layer is stacked.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 17, 2009
    Inventors: Takeshi Noda, Takuo Kaitoh, Hidekazu Miyake, Takahiro Kamo
  • Patent number: 7579627
    Abstract: A nitride semiconductor laser device has a nitride semiconductor substrate that includes a dislocation-concentrated region 102 and a wide low-dislocation region and that has the top surface thereof slanted at an angle in the range of 0.3° to 0.7° relative to the C plane and a nitride semiconductor layer laid on top thereof. The nitride semiconductor layer has a depression immediately above the dislocation-concentrated region, and has, in a region thereof other than the depression, a high-quality quantum well active layer with good flatness and without cracks, a layer that, as is grown, readily exhibits p-type conductivity, and a stripe-shaped laser light waveguide region. The laser light waveguide region is formed above the low-dislocation region. This helps realize a nitride semiconductor laser device that offers a longer life.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: August 25, 2009
    Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.
    Inventors: Yoshihiro Ueta, Teruyoshi Takakura, Takeshi Kamikawa, Yuhzoh Tsuda, Shigetoshi Ito, Takayuki Yuasa, Mototaka Taneya, Kensaku Motoki
  • Patent number: 7575947
    Abstract: A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: August 18, 2009
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Michael Iza, Troy J. Baker, Benjamin A. Haskell, Steven P. DenBaars, Shuji Nakamura
  • Publication number: 20090140267
    Abstract: Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer.
    Type: Application
    Filed: November 24, 2008
    Publication date: June 4, 2009
    Inventor: Kyong Jun KIM
  • Publication number: 20090080483
    Abstract: A semiconductor laser device includes a first semiconductor laser element and a second semiconductor laser element. The first semiconductor laser element has a first end face window structure that is a region including first impurities formed near an end face, and the second semiconductor laser element has a second end face window structure that is a region including second impurities formed near an end face. The distance from a lower end of a first active layer to a lower end of the first end face window structure is shorter than the distance from a lower end of a second active layer to a lower end of the second end face window structure.
    Type: Application
    Filed: July 2, 2008
    Publication date: March 26, 2009
    Inventors: Takayuki Kashima, Kouji Makita, Kenji Yoshikawa
  • Publication number: 20090001349
    Abstract: A method of making an inorganic light emitting layer includes combining a solvent for semiconductor nanoparticle growth, a solution of core/shell quantum dots, and semiconductor nanoparticle precursor(s); growing semiconductor nanoparticles to form a crude solution of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; forming a single colloidal dispersion of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; depositing the colloidal dispersion to form a film; and annealing the film to form the inorganic light emitting layer.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventor: Keith B. Kahen
  • Patent number: 7410856
    Abstract: A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source/drain elevationally above the first source/drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Kris K. Brown
  • Publication number: 20080176351
    Abstract: The present invention provides a manufacturing method of a display device which can prevent the reduction of a size of a pseudo single-crystalline region having strip-like crystals in forming such a pseudo single-crystalline silicon region on a substrate. A step for forming pseudo single crystals having strip-like crystals on a preset region of a semiconductor film formed on a substrate includes a step for forming the pseudo single crystal by radiating an energy beam to a first region of the semiconductor film while moving a radiation position of the energy beam in a first direction, and a step for forming the pseudo single crystal by radiating the energy beam to a second region of the semiconductor film while moving a radiation position of the energy beam in a second direction opposite to the first direction.
    Type: Application
    Filed: August 23, 2007
    Publication date: July 24, 2008
    Inventors: Hideaki Shimmoto, Takahiro Kamo, Takeshi Noda, Takuo Kaitoh, Eiji Oue
  • Patent number: 7399657
    Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Chad A. Cobbley
  • Publication number: 20080128678
    Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 5, 2008
    Inventor: Suk Hun Lee
  • Publication number: 20080112451
    Abstract: The invention relates to high power broad-area semiconductor lasers incorporating a structure that provides both gain guiding and index guiding. The lateral width of the index guiding region is greater than the lateral width of the gain guiding region by at least 20 micron. This results in a high power broad-area semiconductor laser which has reduced lateral divergence of the output beam.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 15, 2008
    Applicant: JDS Uniphase Corporation, State of Incorporation: Delaware
    Inventors: Victor Rossin, Matthew Glenn Peters, Erik Paul Zucker
  • Patent number: 7344905
    Abstract: Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: March 18, 2008
    Assignee: Ahura Corporation
    Inventors: Peidong Wang, Chih-Cheng Lu, Daryoosh Vakhshoori
  • Publication number: 20080061302
    Abstract: A light emitting diode comprises an N-type semiconductor layer comprising a horizontal lattice defect layer, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 13, 2008
    Inventor: Dae Sung Kang
  • Publication number: 20070238209
    Abstract: The present invention is directed to methods and systems of modulating step function phenomena by varying nanoparticle size—particularly wherein a plurality of such nanoparticles are employed, and wherein said nanoparticles comprise a size distribution favorable for collectively smoothing the step function. Such methods and systems are particularly favorable for hydrogen sensors.
    Type: Application
    Filed: April 4, 2007
    Publication date: October 11, 2007
    Applicant: NANO-PROPRIETARY, INC.
    Inventors: Zvi Yaniv, Donald R. Schropp
  • Patent number: 7211458
    Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: May 1, 2007
    Assignee: North Carolina State University
    Inventors: Mehmet Ozturk, Veena Misra, Saurabh Chopra
  • Patent number: 7151004
    Abstract: In fabricating a semiconductor laser producing light with a wavelength of 770 to 810 nm, impurities are introduced into an MQW active layer near a light emitting facet of the laser to form a disordered region constituting a window layer. Pump light is applied to the window layer to generate photoluminescence whose wavelength ? dpl (nm) is measured. A blue shift amount ? bl (nm) is defined as the difference between the wavelength ? apl (nm) 0f photoluminescence generated by application of pump light to the active layer on the one hand, and the wavelength ? dpl (nm) of photoluminescence from the window layer under pump light irradiation on the other hand. The blue shift amount ? bl is referenced during the fabrication process in order to predict catastrophic optical damage levels of semiconductor lasers.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: December 19, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihisa Tashiro, Zempei Kawazu, Harumi Nishiguchi, Tetsuya Yagi, Akihiro Shima
  • Patent number: 7067846
    Abstract: A semiconductor light-emitting device has a semiconductor layer containing Al between a substrate and an active layer containing nitrogen, wherein Al and oxygen are removed from a growth chamber before growing said active layer and a concentration of oxygen incorporated into said active layer together with Al is set to a level such that said semiconductor light-emitting device can perform a continuous laser oscillation at room temperature.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 27, 2006
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Takahashi, Morimasa Kaminishi, Shunichi Sato, Akihiro Itoh, Naoto Jikutani
  • Patent number: 7049157
    Abstract: A critical dimension control wafer for calibrating process control scanning electron microscopes is described. The test wafer provides one or more test structures each consisting of an array of parallel trenches precision micro-machined in a metal plate. The trenches are formed, preferably in an aluminum/copper alloy plate, using focused ion beam milling. The micro-machined trenches have lower width roughness and lower edge roughness compared to similar patterns form in polysilicon by conventional photo lithographic methods. In addition, electron charging in the scanning electron microscope, which produces distorted images, is essentially eliminated. The dimensions of the trenches and the metal lines between them have dimensions comparable to those of polysilicon lines used in sub-tenth micron integrated circuit process technology control wafer. The control wafers are calibrated using a calibrated laboratory grade scanning electron microscope.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: May 23, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hui Lu, Tien-Chi Wu
  • Patent number: 7037743
    Abstract: A semiconductor laser device is provided that includes a first conductivity type semiconductor substrate, a first conductivity type cladding layer provided on the semiconductor substrate and an active layer provided on the cladding layer. The active layer has a super-lattice structure including a disordered region in a vicinity of a cavity end face. A first cladding layer of a second conductivity type is provided on the active layer, an etching stop layer of the second conductivity type is provided on the first cladding layer and a second cladding layer of the second conductivity type is provided on the etching stop layer. The second cladding layer forms a ridge structure that extends along a cavity length direction. An impurity concentration in the etching stop layer in the vicinity of the cavity end face is equal to or smaller than about 2×1018 cm?3.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: May 2, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshikazu Onishi, Hideto Adachi, Masaya Mannou, Akira Takamori
  • Patent number: 7005681
    Abstract: A radiation-emitting semiconductor component having a semiconductor body (1), which has a radiation-generating active layer (9) and a p-conducting contact layer (2), which contains InGaN or AlInGaN and to which a contact metalization (3) is applied.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: February 28, 2006
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Stefan Bader, Viorel Dumitru, Volker Härle, Bertram Kuhn, Alfred Lell, Jürgen Off, Ferdinand Scholz, Heinz Schweizer
  • Patent number: 6989286
    Abstract: There is disclosed a method of manufacturing of optical devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and the like. There is further disclosed Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices. According to the present invention there is provided a method of manufacturing an optical device (40), a device body portion (15) from which the device (40) is to be made including a Quantum Well Intermixing (QWI) structure (30), the method including the step of plasma etching at least part of a surface of the device body portion (5) prior to depositing a dielectric layer (51) thereon so as to introduce structural defects at least into a portion (53) of the device body portion (5) adjacent the dielectric layer (51). The structural defects substanially comprise “point” defects.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: January 24, 2006
    Assignee: The University Court of the University of Glasgow
    Inventors: Craig James Hamilton, Olek Peter Kowalski, John Haig Marsh, Stewart Duncan McDougall
  • Patent number: 6984538
    Abstract: A process for shifting the bandgap energy of a quantum well layer (e.g., a III-V semiconductor quantum well layer) without inducing complex crystal defects or generating significant free carriers. The process includes introducing ions into a quantum well structure at an elevated temperature, for example, in the range of from about 200° C. to about 700° C. The quantum well structure that has had ions introduced therein includes upper and lower barrier layers with quantum well layers therebetween. The quantum well structure is then pre-annealed at a temperature and time that does not induce quantum well intermixing, but does diffuse the point defects closer to the quantum well layer. Finally, the structure is thermally annealed at a higher temperature to induce quantum well intermixing (QWI) in the quantum well structure, which shifts the bandgap energy of the quantum well layer.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: January 10, 2006
    Assignee: Phosistor Technologies, Inc.
    Inventors: Boon-Siew Ooi, Ruiyu Wang
  • Patent number: 6962828
    Abstract: A novel light-emitting device includes a saphire substrate with a light-emitting layer comprising InXGa1?XN, where the critical value of the indium mole fraction X is determined by a newly derived relationship between the indium mole fraction X and the wavelength ? of emitted light.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: November 8, 2005
    Assignees: Toyoda Gosei Co., Ltd.
    Inventors: Norikatsu Koide, Masayoshi Koike, Shiro Yamasaki, Isamu Akasaki, Hiroshi Amano
  • Patent number: 6947311
    Abstract: This invention relates to the controlled two-dimensional structural transition of a dipole monolayer at a metal, semi-conducting or insulating interface. The dipole monolayer consists of objects/molecules with a permanent electric dipole moment. A transition between the structures of the molecular layer can be performed locally and reversibly by applying an electrical field and the structures/patterns can be reversibly switched many times between two different structures/states. Both of the two structures, the ordered and the disordered structures, are intrinsically stable without the presence of the switching electrical field. This controlled switch of the local layer structure can be used to change layer properties (i.e., mechanical, electrical, optical properties). The controlled reversible modifications of the dipole monolayer structures are usable as bit assignments in data storage applications for example.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: September 20, 2005
    Assignee: University of Basel
    Inventors: Simon Berner, Silvia Schintke, Luca Ramoino, Michael de Wild, Thomas A. Jung
  • Patent number: 6936488
    Abstract: A light emitting device comprised of a light emitting semiconductor active region disposed on a substrate comprised of GaN having a dislocation density less than 105 per cm2 is provided.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: August 30, 2005
    Assignee: General Electric Company
    Inventors: Mark P. D'Evelyn, Nicole A. Evers
  • Patent number: 6920167
    Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: July 19, 2005
    Assignee: Sony Corporation
    Inventors: Nozomu Hoshi, Hiroki Nagasaki
  • Patent number: 6881601
    Abstract: A nitride compound semiconductor light-emitting device having a stack of layers including an active layer for a light emitting device and a method of manufacturing the device is disclosed. The method includes the steps of growing a first layer on a substrate at a first temperature to obtain an incomplete crystalline structure including both indium and aluminum and having the composition expressed as InXAlYGa1-X-YN(0?X?1, 0?Y?1). The method grows a cap layer on the first layer to cover the first layer, with growth of the cap layer proceeding at a second temperature substantially equal to or below the first temperature. The first layer is heat treated at a third temperature above the first temperature to cause the incomplete crystalline structure to crystallize and to create areas of differing compositions, thus changing the first layer to an active layer. The material of the cap layer is selected to be heat stable during the heat-treating step.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: April 19, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideto Sugawara
  • Patent number: 6878562
    Abstract: A process for shifting the bandgap energy of a quantum well layer (e.g., a III-V semiconductor quantum well layer) without inducing complex crystal defects or generating significant free carriers. The process includes introducing ions (e.g., deep-level ion species) into a quantum well structure at an elevated temperature, for example, in the range of from about 200° C. to about 700° C. The quantum well structure that has had ions introduced therein includes an upper barrier layer, a lower barrier layer and a quantum well layer. The quantum well layer is disposed between the upper barrier layer and the lower barrier layer. The quantum well structure is then thermally annealed, thereby inducing quantum well intermixing (QWI) in the quantum well structure and shifting the bandgap energy of the quantum well layer. Also, a photonic device assembly that includes a plurality of operably coupled photonic devices monolithically integrated on a single substrate using the process described above.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 12, 2005
    Assignee: Phosistor Technologies, Incorporated
    Inventors: Boon-Siew Ooi, Seng-Tiong Ho
  • Patent number: 6806114
    Abstract: A process for creating a broadly tunable Distributed Bragg Reflector (DBR) with a reduced recombination rate. According to the current invention, this may be achieved by creating electron confinement regions and hole confinement regions in the waveguide of the DBR. Preferably, this is achieved by engineering the band gaps of the DBR waveguide and cladding materials. Preferably, the materials selected for use in the DBR may be lattice matched. Alternately, two or more thin electron confinement regions and two or more thin hole confinement regions may be created to take advantage of strain compensation in thinner layers thereby broadening the choices of materials appropriate for use in creating a broadly tunable DBR. Alternately, graded materials and/or graded interfaces may be created according to alternate processes according to the current invention to provide effective electron and/or hole confinement regions in various DBR designs.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: October 19, 2004
    Assignee: Nova Crystals, Inc.
    Inventor: Yu-Hwa Lo
  • Patent number: 6750158
    Abstract: A first semiconductor layer is formed on a mother substrate, and the mother substrate is irradiated with irradiation light from a surface opposite to the first semiconductor layer, so that a thermally decomposed layer formed by thermally decomposing the first semiconductor layer between the first semiconductor layer and the mother substrate. Then, a second semiconductor layer including an active layer is formed on the first semiconductor layer in which the thermally decomposed layer is formed.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: June 15, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Ogawa, Daisuke Ueda, Masahiro Ishida, Masaaki Yuri, Hirokazu Shimizu
  • Patent number: 6727109
    Abstract: The present invention relates to a method of fabricating vertical-cavity surface emitting lasers being watched as a light source for long wavelength communication. The present invention includes forming a layer having a high resistance near the surface by implanting heavy ions such as silicon (Si), so that the minimum current injection diameter is made very smaller unlike implantation of a proton. Further, the present invention includes regrowing crystal so that current can flow the epi surface in parallel to significantly reduce the resistance up to the current injection part formed by silicon (Si) ions. Therefore, the present invention can not only effectively reduce the current injection diameter but also significantly reduce the resistance of a device to reduce generation of a heat. Further, the present invention can further improve dispersion of a heat using InP upon regrowth and thus improve the entire performance of the device.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: April 27, 2004
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Gu Ju, Won Seok Han, O Kyun Kwon, Jae Heon Shin, Byueng Su Yoo, Jung Rae Ro
  • Patent number: 6720196
    Abstract: A thin nitride-based semiconductor layer having a low dislocation density is formed by laterally growing a nitride-based semiconductor layer on the upper surface of an underlayer and forming quantum dots on the laterally grown nitride-based semiconductor layer. The number of dislocations is reduced by a single lateral growth and is further reduced due to a dislocation loop effect by the quantum dots, without repeating lateral growth.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: April 13, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tatsuya Kunisato, Yasuhiko Nomura, Takashi Kano, Hiroki Ohbo, Masayuki Hata
  • Patent number: 6716654
    Abstract: The present invention discloses a light-emitting diode with enhanced brightness and a method for fabricating the same. The light-emitting diode comprises: an epitaxial LED structure having at least one lighting-emitting active layer with a plurality of spacers inside the lighting-emitting active layer; at least one conductive contact, formed on the bottom surface where no spacer is formed inside the lighting-emitting active layer; a transparent material layer formed in the spacers; an adhesion layer formed between the transparent material layer and a permanent substrate; a bottom electrode formed on the bottom surface of the permanent substrate; and an opposed electrode formed on the top surface of the epitaxial LED structure.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: April 6, 2004
    Assignee: Opto Tech Corporation
    Inventors: Jung-Kuei Hsu, Hsueh-Chih Yu, Chia-Liang Hsu, Hung-Yuan Lu, Yen-Hu Chu, Chui-Chuan Chang, Kwang-Ru Wang, Chang-Da Tsai, San Bao Lin, Yung-Chiang Hwang, Ming-Der Lin
  • Patent number: 6716655
    Abstract: An object of the invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having no cracks and a low dislocation density and which have excellent characteristics. Specifically, a mask formed from SiO2 film is provided on the Si(111) plane of an n-type silicon substrate, and a window portion (crystal growth region) in the shape of an equilateral triangle having a side of approximately 300 &mgr;m is formed through the mask. The three sides of the equilateral triangle are composed of three edges; each edge defined by the (111) plane and another crystal plane that is cleavable. Subsequently, a multi-layer structure of semiconductor crystals in an LED is formed through crystal growth of a Group III nitride compound semiconductor. Thus, limiting the area of one crystal growth region to a considerably small area weakens a stress applied to a semiconductor layer, thereby readily producing semiconductor elements having excellent crystallinity.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: April 6, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
  • Patent number: 6689626
    Abstract: The invention relates to a substrate comprising a glass sheet (1) having a thickness which is smaller than or equal to 0.1 mm, the glass sheet (1) being provided with a layer of a synthetic resin material (2) having a thickness which is smaller than or equal to that of the glass sheet (1). This substrate proves to be flexible. In addition, the substrate cracks less easily, so that it can be processed more readily. The substrate may be used, for example, in light-emitting devices, such as a poly-LED or PALC.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: February 10, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Marcellinus P. C. M. Krijn, Marinus J. J. Dona, Johannes M. M. Swinkels, Jeroen J. M. Vleggaar
  • Patent number: 6653158
    Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: November 25, 2003
    Assignee: The Regents of the University of California
    Inventors: Eric M. Hall, Shigeru M. Nakagawa, Larry A. Coldren
  • Patent number: 6653248
    Abstract: A semiconductor layer is co-doped with two dopants. The first dopant is to generate charge carriers in the semiconductor material, and the second dopant is to promote atomic disorder within the material. When the semiconductor material is annealed, the second dopant becomes mobile and moves through the lattice so as to promote atomic disorder. This eliminates unwanted effects such as, for example, a reduction in the forbidden bandgap that can otherwise arise as a result of atomic ordering. The amount of diffusion of the second dopant during the annealing can be increased by making the initial concentration of the second dopant non-uniform over the volume of the semiconductor material.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 25, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Alistair Henderson Kean, Haruhisa Takiguchi
  • Patent number: 6617188
    Abstract: The present invention provides a novel technique based on gray scale mask patterning (110), which requires only a single lithography and etching step (110, 120) to produce different thickness of SiO2 implantation mask (13) in selected regions followed by a one step IID (130) to achieve selective area intermixing. This novel, low cost, and simple technique can be applied for the fabrication of PICs in general, and WDM sources in particular. By applying a gray scale mask technique in IID in accordance with the present invention, the bandgap energy of a QW material can be tuned to different degrees across a wafer (14). This enables not only the integration of monolithic multiple-wavelength lasers but further extends to integrate with modulators and couplers on a single chip. This technique can also be applied to ease the fabrication and design process of superluminescent diodes (SLDs) by expanding the gain spectrum to a maximum after epitaxial growth.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: September 9, 2003
    Assignee: NTU Ventures PTE Ltd
    Inventors: Boon Siew Ooi, Yee Loy Lam, Yuen Chuen Chan, Yan Zhou, Siu Chung Tam