Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.

Abstract: Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.

Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.

Abstract: A method for forming self aligned magnetic memory element pillars for Magnetic Random Access Memory. The method allows the magnetic memory element pillars to be arranged in staggered rows of memory elements at a pitch that is smaller than what is possible using photolithography alone. The method involves forming a spacer mask in the form of an array of connected rings arranged in a square pattern of non-staggered rows. A sacrificial mask material is deposited over the spacer mask and the spacer mask is then removed, leaving sacrificial mask material in the holes at the center of the rings and also in the spaces between the rings. A reactive ion processes is then performed to transfer the pattern of the sacrificial mask onto underlying hard mask layers. A material removal process can then be performed to define a plurality of memory element pillars.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

Abstract: A magnetic tunnel junction element includes, in a following stack order, an underlayer formed of a metal material, a fixed layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, or alternatively, the magnetic tunnel junction element includes, in a following stack order, a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, an underlayer formed of a metal material, and a fixed layer formed of a ferromagnetic body, wherein the fixed layer is formed and stacked after performing plasma treatment to a surface of the underlayer having been formed.

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).

Abstract: A magnetic tunnel junction (MTJ) containing device and methods of constructing the MTJ containing device are described. In an example, the MTJ containing device may be a memory element including a bottom electrode structure, a MTJ pillar, and a top electrode structure located on the MTJ pillar. The MTJ pillar has a non-circular lateral cross section, where the MTJ pillar has a bottommost portion forming an interface with an uppermost portion of the bottom electrode structure. The MTJ pillar has a lateral perimeter-to-area ratio that defines a breakdown voltage of the MTJ pillar.

Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

Abstract: A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.

Abstract: To improve the Q value of a piezoelectric thin-film element in a state in which unnecessary vibration is suppressed, an acoustic reflection film (104) is affixed to a first electrode (102), a piezoelectric single-crystal substrate (101) is thinned by polishing from the other surface (101b) of the piezoelectric single-crystal substrate (101), such that the first electrode (102) and piezoelectric thin film (105) are piled on the piezoelectric single-crystal substrate (101). In this polishing, a pressure (polishing pressure) to the surface (101b) during polishing in an electrode formation region where the first electrode (102) is formed differs from that in a non-electrode formation region around the electrode formation region. Consequently, the electrode formation region of the piezoelectric thin film (105), where the first electrode (102) is formed, is made thinner than the non-electrode formation region around the electrode formation region.

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

Abstract: Some embodiments include an integrated assembly having a ferroelectric transistor body region between a first comparative digit line and a second comparative digit line. A carrier-reservoir structure is coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line. Some embodiments include an integrated assembly having a conductive structure over a carrier-reservoir structure. A bottom of the conductive structure is spaced from the carrier-reservoir structure by an insulative region. A ferroelectric transistor is over the conductive structure. The ferroelectric transistor has a bottom source/drain region over the conductive structure, has a body region over the bottom source/drain region, and has a top source/drain region over the body region. An extension extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region.

Abstract: A magnetic sensor includes a first bridge circuit including a plurality of magnetic field sensor elements, each configured to generate a sensor signal in response to the magnetic field impinging thereon. The first bridge circuit is configured to generate a first differential signal based on sensor signals generated by the plurality of magnetic field sensor elements. The plurality of magnetic field sensor elements include a first, second, and third pair of sensor elements. The first pair are arranged at center region of the magnetic sensor, the second pair are arranged at a first side region of the magnetic sensor and are displaced a first distance from the first pair, and the third pair are arranged at a second side region of the magnetic sensor, opposite to the first side region, and are displaced a second distance from the first pair that is substantially equal to the first distance.

Abstract: In order to provide a memory element configured to generate and detect monopole current, in an embodiment provided in the present disclosure is a monopole current generation detection device comprising a ferromagnetic quantum spin-ice layer, a buffer layer made of a material capable of exhibiting a quantum spin-liquid state, and a pair of electrodes disposed in contact with the buffer layer. In this device it is possible to apply a voltage between the pair of electrodes by providing a voltage application means. It is possible to generate a monopole current Jm upon application of the voltage, where the monopole currents through the ferromagnetic quantum spin-ice layer and through another ferromagnetic quantum spin-ice layer that is in contact with the buffer layer on the other side of the ferromagnetic quantum spin-ice layer. Also, the monopole current can be electrically detected by providing a detection circuit to the device.

Abstract: A semiconductor device comprises a first conductive material, a contact, an a magnetic tunneling junction positioned between the first conductive material and the contact. The semiconductor device further comprises a spacer that is positioned between the first conductive material and the contact and surrounds at least a portion of the magnetic tunneling junction. The spacer comprises spacer material that has at least some etch selectivity compared to a dielectric material that surrounds at least a portion of the first conductive material.

Abstract: A polycrystalline dielectric thin film and a capacitor element have a large relative dielectric constant. The polycrystalline dielectric thin film has a perovskite oxynitride as a principal component. The perovskite oxynitride is represented by compositional formula Aa1Bb1OoNn (a1+b1+o+n=5), and the a-axis length of the crystal lattice of the perovskite oxynitride is larger than a theoretical value.

Abstract: Methods of forming an inductor using dry processes are described. A cavity is laser drilled in an insulator. A first magnetic material layer is printed in the cavity. An Ag conductive ink is printed on the first magnetic material layer and a second magnetic material layer printed on the ink. The ink has a trace sandwiched between the first and second magnetic material layers that provides a majority of the inductance of the inductor. A protective insulating layer protects the second magnetic material layer from a wet chemistry solution when contacts are formed to the ink. The second magnetic material layer and ink are deposited in or on the cavity.

Abstract: A memory cell includes: a first electrode contact formed as a cylinder shape that extends along a first direction; a resistive material layer comprising a first portion that extends along the first direction and surrounds the first electrode contact; and a second electrode contact coupled to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.

Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

Abstract: A composition for forming a Ce-doped PZT-based piezoelectric film contains: PZT-based precursors containing metal atoms configuring the composite metal oxides; a diol; and polyvinylpyrrolidone. The PZT-based precursors are contained so that a metal atom ratio (Pb:Ce:Zr:Ti) in the composition satisfies (1.00 to 1.28):(0.005 to 0.05):(0.40 to 0.55):(0.60 to 0.45) and the total of Zr and Ti in a metal atom ratio is 1. A concentration of the PZT-based precursor in 100 mass % of the composition is from 17 mass % to 35 mass % in terms of an oxide concentration, a rate of diol in 100 mass % of the composition is from 16 mass % to 56 mass %, and a molar ratio of polyvinylpyrrolidone to 1 mole of the PZT-based precursor is 0.01 moles to 0.25 moles in terms of monomers.

Abstract: A spin flow magnetization reversal element includes a first ferromagnetic metal layer capable of changing a direction of magnetization; and a spin orbit torque wiring layer joined to the first ferromagnetic metal layer and extending in a direction intersecting a direction perpendicular to a plane of the first ferromagnetic metal layer. The spin orbit torque wiring layer includes at least one light element L among B, C, Si and P and at least one noble gas element among Ar, Kr and Xe.

Abstract: A method is presented for establishing a top contact to a magnetic tunnel junction (MTJ) device, the method including selectively etching, via a first etching process, an oxide layer to expose a top surface of a nitride layer of a dummy fill shape and selectively etching, via a second etching process, a top portion of the nitride layer of the dummy fill shape to expose a top surface thereof. The method further includes selectively etching, via the second etching process, the oxide layer to expose a top surface of a nitride layer of the MTJ device, and selectively etching, via the first etching process, a top portion of the nitride layer of the MTJ device to expose a top surface thereof such that a height of the MTJ device is approximately equal to a height of the dummy fill shape.

Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

Abstract: A method for testing individual memory elements or sets of memory elements of an array of magnetic memory elements. The method involves forming a mask such as photoresist mask over an array memory elements. The mask is configured with an opening over each of the selected memory elements to be tested. The mask can be formed of photoresist which can be patterned by focused electron beam exposure to form opening at features sizes smaller than those available using standard photolithographic processes. An electrically conductive material is deposited over the mask and into the openings in the mask to make electrical contact with the selected memory element or memory elements to be tested. Then, electrical connection can be made with the electrically conductive material to test the selected one or more magnetic memory elements.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a first magnetic layer; a second magnetic layer; and a spacer layer interposed between the first magnetic layer and the second magnetic layer, wherein the spacer layer includes a first layer, a second layer and an intermediate layer interposed between the first layer and the second layer, and wherein each of the first layer and the second layer includes an oxide, or a nitride, or a combination of an oxide and a nitride, the intermediate layer includes a multilayer structure including [Ru/x]n or [x/Ru]n, x includes a metal, an oxide, or a nitride, or a combination of a metal, an oxide and a nitride, and n represents an integer of 1 or greater.

Abstract: A magnetic tunnel junction (MTJ) structure having faceted sidewalls is formed on a conductive landing pad that is present on a surface of an electrically conductive structure embedded in a dielectric material layer. No metal ions are re-sputtered onto the sidewalls of the MTJ structure during the patterning of the MTJ material stack that provides the MTJ structure. The absence of re-sputtered metal on the MTJ structure sidewalls reduces the risk of shorts.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset of the one or more memory elements by reading or writing the data a predetermined number of times to fix the data to a non-volatile stable state.

Abstract: A magnetoresistive random access memory (MRAM) structure and a method of forming the same are provided. The MRAM structure includes a conductive pillar over a substrate, a first MTJ spacer and a first conductive layer. The first MTJ spacer surrounds the conductive pillar. The first conductive layer surrounds the first MTJ spacer. The first magnetic tunnel junction (MTJ) spacer includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) layer. The first electrode is in contact with the conductive pillar and the substrate. The second electrode is positioned over the first electrode and in contact with the first conductive layer. The magnetic tunnel junction (MTJ) layer is positioned between the first electrode and the second electrode.

Abstract: A method of manufacturing an embedded magnetoresistive random access memory including the following steps is provided. A memory cell stack structure is formed on a substrate structure. The memory cell stack structure includes a first electrode, a second electrode, and a magnetic tunnel junction structure. A first dielectric layer covering the memory cell stack structure is formed. A metal nitride layer is formed on the first dielectric layer. A second dielectric layer is formed on the metal nitride layer. A first CMP process is performed on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer. An etch back process is performed to completely remove the metal nitride layer and expose the first dielectric layer. A second CMP process is performed to expose the second electrode. The manufacturing method can have a better planarization effect.

Abstract: Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.

Abstract: A method of fabricating a ferroelectric memory device is provided. The method includes preparing a substrate, forming an interfacial insulation layer on the substrate, forming a ferroelectric layer on the interfacial insulation layer, applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer, forming a gate electrode layer on the ferroelectric layer, and annealing the ferroelectric layer to crystallize the ferroelectric layer.

Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

Abstract: A method for manufacturing a magnetic memory element array. A plurality of magnetic memory elements are formed on a substrate, and a dielectric fill layer such as SiO2 or SiNx is deposited over the magnetic memory element pillars. An ion milling is then performed at a high angle (at least 70 degrees) relative normal to remove topographic dielectric features from areas over the magnetic memory elements. Optionally, additional ion milling processes can be performed at increasing angles relative to normal until the dielectric material has been removed from the areas over the magnetic memory elements.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.

Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a variable resistance element exhibiting two different states for storing data; and an upper layer disposed over the variable resistance element, and wherein the upper layer may have a stepped or sloped profile and be located to serve as a part of a hard mask to pattern the variable resistance element.

Abstract: A spintronics element including a ferromagnetic layer containing boron, and a diffusion stopper film covering a side face of the ferromagnetic layer partially or entirely, the side face in direct contact with diffusion stopper film, so as to prevent out-diffusion of the boron contained in the ferromagnetic layer. The diffusion stopper film contains boron at a concentration higher than a concentration of the boron in a portion of the ferromagnetic layer where the ferromagnetic layer contacts the diffusion stopper film.

Abstract: A method for improving photo resist adhesion to an underlying hard mask layer. The method includes a cleaning step that includes applying tetramethylammonium hydroxide (TMAH) to coat a hard mask layer of a wafer. The method further includes puddle developing the wafer for a first desired amount of time, and rinsing the wafer in running water for a second desired amount of time. The method further includes spin drying the wafer, and baking the wafer for a third desired amount of time. The method concludes with the proceeding of subsequent photolithographic processes on the wafer.

Abstract: A method of manufacturing a spintronics element from laminated layers. The method includes (a) forming a plurality of laminated layers in manufacturing equipment, (b) forming a wafer in the manufacturing equipment, including applying a protection layer directly on a non-magnetic uppermost layer of the laminated layers so that the protection layer prevents alteration of characteristics of the uppermost layer, and (c) exposing the wafer, outside of the manufacturing equipment, to an atmosphere that includes H2O having a partial pressure in the atmosphere equal to or larger than 10?4 Pa.

Abstract: According to the present invention, it is possible to provide a cleaning solution which removes a dry etching residue and photoresist on a surface of a semiconductor element having a low dielectric constant film (a low-k film) and at least one material selected from between a material that contains 10 atom % or more of titanium and a material that contains 10 atom % or more of tungsten, wherein the cleaning solution contains: 0.002-50 mass % of at least one type of oxidizing agent selected from among a peroxide, perchloric acid, and a perchlorate salt; 0.000001-5 mass % of an alkaline earth metal compound; and water.

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.