Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 8492224
    Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 23, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien
  • Patent number: 8470685
    Abstract: The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: June 25, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 8470631
    Abstract: A simple and economical method for manufacturing very thin capped MEMS components. In the method, a large number of MEMS units are produced on a component wafer. A capping wafer is then mounted on the component wafer, so that each MEMS unit is provided with a capping structure. Finally, the MEMS units capped in this way are separated to form MEMS components. A diaphragm layer is formed in a surface of the capping wafer by using a surface micromechanical method to produce at least one cavern underneath the diaphragm layer, support points being formed that connect the diaphragm layer to the substrate underneath the cavern. The capping wafer structured in this way is mounted on the component wafer in flip chip technology, so that the MEMS units of the component wafer are capped by the diaphragm layer. The support points are then cut through in order to remove the substrate.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: June 25, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Torsten Kramer, Kathrin Knese, Hubert Benzel, Karl-Heinz Kraft, Simon Armbruster
  • Publication number: 20130157435
    Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.
    Type: Application
    Filed: February 14, 2013
    Publication date: June 20, 2013
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventor: Air Products And Chemicals, Inc.
  • Patent number: 8466033
    Abstract: A light emitting diode comprises a substrate, a buffer layer, a semiconductor layer and a semiconductor light emitting layer. The buffer layer is disposed on the substrate. The semiconductor layer is disposed on the buffer layer. The semiconductor light emitting layer is disposed on the semiconductor layer. A plurality of voids is defined within the semiconductor layer. Each void encloses air therein. A method for manufacturing the light emitting diode is also provided. Light generated by the semiconductor light emitting layer toward the substrate is reflected by the voids to emit out of the light emitting diode.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: June 18, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang, Shun-Kuei Yang, Chia-Hung Huang
  • Publication number: 20130146958
    Abstract: A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.
    Type: Application
    Filed: April 13, 2012
    Publication date: June 13, 2013
    Inventors: You-Song Kim, Jin-Ki Jung
  • Patent number: 8461015
    Abstract: A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Han-Pin Chung, Shiang-Bau Wang
  • Patent number: 8456009
    Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8426289
    Abstract: In one embodiment, a method of forming an insulating spacer includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 23, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Andrew B. Graham, Gary Yama, Gary O'Brien
  • Patent number: 8421166
    Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Hwa Chi, Wen-Chuan Chiang, Mu-Chi Chiang, Cheng-Ku Chen
  • Patent number: 8415257
    Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: April 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hartmut Ruelke, Volker Jaschke
  • Patent number: 8399349
    Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removale of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: March 19, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Raymond Nicholas Vrtis, Dingjun Wu, Mark Leonard O'Neill, Mark Daniel Bitner, Jean Louise Vincent, Eugene Joseph Karwacki, Jr., Aaron Scott Lukas
  • Patent number: 8399335
    Abstract: In sophisticated semiconductor devices, densely packed metal line layers may be formed on the basis of an ultra low-k dielectric material, wherein corresponding modified portions of increased dielectric constant may be removed in the presence of the metal lines, for instance, by means of a selective wet chemical etch process. Consequently, the metal lines may be provided with desired critical dimensions without having to take into consideration a change of the critical dimensions upon removing the modified material portion, as is the case in conventional strategies.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: March 19, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Torsten Huisinga, Michael Grillberger, Frank Feustel
  • Patent number: 8389376
    Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure including depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: March 5, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Alexandros T. Demos, Li-Qun Xia, Bok Hoen Kim, Derek R. Witty, Hichem M'Saad
  • Patent number: 8377793
    Abstract: A method of manufacturing a non-volatile memory device, including providing at least one control gate layer on a substrate. A passage may be created between the at least one control gate layer and the substrate. In the passage at least one filling layer may be provided. A floating gate structure including the filling layer may be formed, as well as a control gate structure including the at least one control gate layer, the control gate structure being in a stacked configuration with the floating gate structure.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: February 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Marius Orlowski
  • Patent number: 8357989
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: 8338911
    Abstract: In one embodiment, a semiconductor device including a substrate provided with a semiconductor element, and first and second interconnects provided above the substrate, each of the first and second interconnects having a line shape in a plan view, and the first and second interconnects being substantially parallel to each other. The device further includes a first via plug provided above the substrate, electrically connected to a lower surface of the first interconnect on a second interconnect side, and including a first recess part at an upper end of the first via plug under a first region between interconnects, the first region between interconnects being a region between the first interconnect and the second interconnect.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Miki, Makoto Wada, Yumi Hayashi
  • Patent number: 8338903
    Abstract: The surrounding length of a junction separation portion can be shortened to improve an insulating resistance in order to provide a solar cell with highly efficiency. In a photoelectric transducer of the type where a light-receiving surface electrode is wired to another electrode on a back surface via a through electrode passing through a semiconductor substrate of a first conductive type, the photoelectric transducer comprises: a junction separation portion made around the through electrode on a back surface of the semiconductor substrate; a dielectric layer formed for covering the junction separation portion, the through electrode penetrating the dielectric layer; and a back electrode provided on the dielectric layer and coupled to the through electrode which is connected to the light-receiving surface electrode.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: December 25, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tsutomu Yamazaki, Satoshi Okamoto, Jumpei Imoto
  • Publication number: 20120306046
    Abstract: A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 6, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Gerhard Schmidt
  • Patent number: 8304316
    Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: November 6, 2012
    Assignee: Cambridge Semiconductor Limited
    Inventors: Florin Udrea, Gehan Anil Joseph Amaratunga, Tanya Trajkovic, Vasantha Pathirana
  • Publication number: 20120276711
    Abstract: A semiconductor device having a spacer with an air gap is manufactured by forming a first conductive pattern over a semiconductor substrate; forming a spacer on sidewalls of the first conductive pattern; forming a sacrifice layer on sidewall of the spacer, the sacrifice layer having a different etching selectivity with the spacer; forming a second conductive pattern to fill a space between the first conductive pattern and the first conductive pattern; and forming an air gap between the first and second conductive patterns by selectively removing the sacrifice layer.
    Type: Application
    Filed: September 25, 2011
    Publication date: November 1, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hyo Geun YOON, Ji Yong PARK, Sun Jin LEE
  • Publication number: 20120273919
    Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.
    Type: Application
    Filed: August 16, 2011
    Publication date: November 1, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Song Hyeuk IM
  • Patent number: 8298910
    Abstract: Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Don Nam, Sang-Hoon Ahn, Eunkee Hong
  • Patent number: 8298911
    Abstract: In a method of forming a wiring structure, a first insulation layer is formed on a substrate, the first insulation layer comprising a group of hydrocarbon (C?H?) wherein ? and ? are integers. A second insulation layer is formed on the first insulation layer, the second insulation layer being avoid of the group of hydrocarbon. A first opening is formed through the first and the second insulation layers by etching the first and the second insulation layers. A damaged pattern and a first insulation layer pattern are formed by performing a surface treatment on a portion of the first insulation layer corresponding to an inner sidewall of the first opening. A sacrificial spacer is formed in the first opening on the damaged pattern and on the second insulation layer. A conductive pattern is formed in the first opening.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoung-Woo Lee
  • Patent number: 8294194
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Noda, Hidenobu Nagashima
  • Patent number: 8293617
    Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Arthur J. McGinnis, Sachin Joshi, Chan Lim
  • Publication number: 20120261791
    Abstract: A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventors: Xiaobin Wang, Anup Bhalla, Yeeherg Lee
  • Publication number: 20120241910
    Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.
    Type: Application
    Filed: September 16, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun OGI, Takeshi Kamigaichi, Tatsuo Izumi
  • Publication number: 20120241838
    Abstract: According to one embodiment, a semiconductor storage device includes: a plurality of word lines that are formed at predetermined intervals in a first direction on the element region; a select gate transistor that is arranged in each of both sides of the word lines and has a width in the first direction wider than the word line; a first air gap that is positioned between the word lines; and a second air gap that is formed on a side wall portion opposite to a side of the word line of the select gate transistor. Further, according to one embodiment, the semiconductor storage device is provided in which an oxide film is formed on a surface of a substrate between the select gate transistors that are adjacent to each other, and a cross-sectional surface in a direction perpendicular to the first direction under the oxide film has a convex shape.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hidenobu NAGASHIMA, Akira YOTSUMOTO
  • Patent number: 8269306
    Abstract: A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is removed substantially concurrently from the first and second trenches to expose substantially all of the dielectric liner within the second trench and to form a plug of the material in the one or more first trenches. A second layer of dielectric material is formed substantially concurrently on the plug in the first trench and on the exposed portion of the dielectric liner in the second trench. The second layer of dielectric material substantially fills a portion of the first trench above the plug and the second trench.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: September 18, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Sukesh Sandhu
  • Patent number: 8268698
    Abstract: The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: William K. Henson, Dureseti Chidambarrao, Kern Rim, Hsingjen Wann, Hung Y. Ng
  • Publication number: 20120213006
    Abstract: A semiconductor storage device according to an embodiment comprises a memory cell string in which a plurality of memory cells each having a gate are serially connected to each other. A selective transistor is connected to an end memory cell at an end of the memory cell string. A sidewall film covers a side surface of a gate of the end memory cell and a side surface of a gate of the selective transistor between the end memory cell and the selective transistor.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke ISOMURA, Wataru SAKAMOTO, Hiroyuki NITTA
  • Patent number: 8247902
    Abstract: In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: August 21, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Junji Noguchi, Takashi Matsumoto, Takayuki Oshima, Toshihiko Onozuka
  • Patent number: 8241992
    Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
  • Patent number: 8241989
    Abstract: An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 14, 2012
    Assignee: Qimonda AG
    Inventor: Franz Hofmann
  • Patent number: 8241991
    Abstract: A method for forming an interconnect structure with airgaps, includes: providing a structure having a trench formed on a substrate; depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers by plasma enhanced atomic layer deposition; filling the trench having the sidewall spacers with copper; removing the sidewall spacers to form an airgap structure; and encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: August 14, 2012
    Assignee: ASM Japan K.K.
    Inventors: Julian J. Hsieh, Nobuyoshi Kobayashi, Akira Shimizu, Kiyohiro Matsushita, Atsuki Fukazawa
  • Patent number: 8241990
    Abstract: An air gap fabricating method is provided. A patterned sacrificial layer is formed over a substrate, and the material of the patterned sacrificial layer includes a germanium-antimony-tellurium alloy. A dielectric layer is formed on the patterned sacrificial layer. A reactant is provided to react with the patterned sacrificial layer and the patterned sacrificial layer is removed to form a structure with an air gap disposed at the original position of the patterned sacrificial layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 14, 2012
    Assignee: Industrial Technology Research Institute
    Inventor: Wei-Su Chen
  • Publication number: 20120199938
    Abstract: A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.
    Type: Application
    Filed: May 16, 2011
    Publication date: August 9, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Min Hwang, Hyeon Soo Kim
  • Patent number: 8232653
    Abstract: A wiring structure includes a conductive pattern on a substrate, a first insulation layer pattern between adjacent conductive patterns and a second insulation layer pattern on the first insulation layer pattern. The first insulation layer pattern is separated from the conductive pattern by a first distance to provide a first air gap. The second insulation layer pattern is spaced apart from the conductive pattern by a second distance substantially smaller than the first distance to provide a second air gap. The wiring structure may have a reduced parasitic capacitance while simplifying processes for forming the wiring structure.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoung-Woo Lee
  • Publication number: 20120178235
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 12, 2012
    Inventors: Jayavel Pachamuthu, Vinod R. Purayath, George Matamis
  • Patent number: 8211777
    Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuaki Yonemochi, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
  • Publication number: 20120156855
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.
    Type: Application
    Filed: November 22, 2011
    Publication date: June 21, 2012
    Inventor: Jae-Hwang SIM
  • Patent number: 8202783
    Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: June 19, 2012
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Deborah A. Neumayer
  • Publication number: 20120129316
    Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 24, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Young-Kyun JUNG
  • Publication number: 20120091555
    Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 19, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Toshio NAKASAKI
  • Patent number: 8148235
    Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Markus Naujok, Hermann Wendt, Alois Gutmann, Muhammed Shafi Pallachalil
  • Patent number: 8129252
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: March 6, 2012
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 8129264
    Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: March 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Gyun Kim, Bon-young Koo, Ki-hyun Hwang
  • Patent number: 8097949
    Abstract: The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (216, 218) between a lower etch-barrier layer (236) and an upper etch-barrier layer (211) on top of an upper-intermediate interconnect level (224). Lateral inhomogeneities of the dielectric constant on the upper-intermediate interconnect level are removed in comparison with prior-art devices. For in the finished interconnect stack local variations in the dielectric permittivity can only occur at the (former) etch vias, which are either visible by the presence of air cavities or hardly visible due to a later filling with the dielectric material of the next interlevel dielectric layer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 17, 2012
    Assignees: NXP B.V., Commissariat a l'Energie Atomique
    Inventors: Laurent Gosset, Jean Raymond Jacques Marie Pontcharra, Frederic Gaillard
  • Publication number: 20120003809
    Abstract: The present invention discloses an isolation process in a semiconductor device. In the present invention, when a SPT process is used for isolation, ISO cut patterns for cutting spacers for SPT in the unit of a specific length are first formed, and ISO partition patterns defining partition regions for forming the spacers are then formed over the ISO cut patterns. Accordingly, there are advantages in that the SPT process can be simplified and costs can be reduced according to the simplified process because the isolation process is simplified.
    Type: Application
    Filed: July 5, 2011
    Publication date: January 5, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Young Deuk KIM