Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 8084794
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction which crosses the first direction and being disposed with a space interposed between the first wiring and the second wiring, and including a tantalum layer, a tantalum nitride layer formed over the tantalum layer, and a metal layer formed over the tantalum nitride layer.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: December 27, 2011
    Assignee: Fujitsu Limited
    Inventors: Yoichi Kamada, Naoya Okamoto
  • Publication number: 20110309426
    Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien
  • Publication number: 20110309430
    Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Inventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
  • Publication number: 20110309425
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Inventors: Vinod Robert Purayath, George Matamis, Eli Harari, Hiroyuki Kinoshita, Tuan Pham
  • Publication number: 20110303967
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.
    Type: Application
    Filed: June 9, 2011
    Publication date: December 15, 2011
    Inventors: Eli Harari, Tuan Pham, Yupin Fong, Vinod Robert Purayath
  • Patent number: 8067291
    Abstract: To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons or holes are drastically improved, thereby realizing high-speed operation and low power consumption. A stressor 2 composed of silicon germanium is formed in a portion in an active region that is separated by an insulating film formed on a silicon substrate, a silicon channel layer 1 composed of silicon is formed above the stressor, and a tensile stress layer 10 is formed so as to surround a gate electrode and a sidewall formed on the gate electrode.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Publication number: 20110281415
    Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 17, 2011
    Inventors: Dae-Hyuk KANG, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
  • Patent number: 8058138
    Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: November 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Arthur J. McGinnis, Sachin Joshi, Chan Lim
  • Patent number: 8058136
    Abstract: A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 15, 2011
    Assignee: Inotera Memories, Inc.
    Inventors: Chien-Hsun Chen, Tzung Han Lee, Chung-Lin Huang
  • Patent number: 8053335
    Abstract: A method includes forming a first layer containing silicon oxide on a first substrate, partially removing the first layer to form an exposure portion on the first substrate, depositing amorphous gallium nitride system compound semiconductor on the first substrate with the exposure portion, evaporating the semiconductor on the first layer to form cores of the semiconductor on the exposure portion of the first substrate, forming an epitaxial layer of the semiconductor on the first substrate, and removing the epitaxial layer of the semiconductor on the exposure portion on the first substrate to form a separating groove.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 8, 2011
    Inventor: Takao Yonehara
  • Publication number: 20110269293
    Abstract: A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies.
    Type: Application
    Filed: April 4, 2011
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Matthias Kessler, Thomas Feudel
  • Patent number: 8048760
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 1, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventors: Bishnu Prasanna Gogoi, Michael Albert Tischler
  • Patent number: 8043931
    Abstract: The embodiments of the present invention are directed to the formation of multi-layer silicon structures by forming and attaching a plurality of individual layers or structures where each of the layers or the structures comprises at least silicon forming a desired pattern. In some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures comprises a plurality of discrete silicon features that are combined together with at least one sacrificial material. In some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures comprises a plurality of discrete silicon features that are supported by a temporary substrate. Still in some embodiments or some applications of some embodiments, at least one of the plurality of individual layers or the structures needs to be machined after it is attached to a receiver such as a substrate or an another layer or structure.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: October 25, 2011
    Inventor: Gang Zhang
  • Patent number: 8022489
    Abstract: An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: September 20, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20110223739
    Abstract: A substrate having buried address lines and a first dielectric layer is provided. A conductive electrode is formed in the first conductive layer. A top portion of the conductive electrode is exposed. A second dielectric layer is deposited on surface of the exposed top portion. The second dielectric layer defines a recess around the top portion. A third dielectric layer is deposited over the second dielectric layer. A portion of the third dielectric layer and a portion of the second dielectric layer are removed, thereby exposing a top surface of the top portion of the conductive electrode. The top portion of the conductive electrode is salicidized to form a heating stem. The remaining third dielectric layer is selectively removed from the recess. A phase-change material layer covers the heating stem and the second dielectric layer. The phase-change material layer is etched, thereby forming a phase-change storage cap.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 15, 2011
    Inventor: Li-Shu Tu
  • Publication number: 20110189833
    Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 4, 2011
    Applicant: TOKYO OHKA KOGYO CO., LTD.
    Inventor: Yoshihiro SAWADA
  • Patent number: 7985977
    Abstract: Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 26, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventors: Bishnu Prasanna Gogoi, David William Wolfert, Jr.
  • Publication number: 20110175205
    Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 21, 2011
    Inventors: Katsumi MORII, Yoshitaka OTSU, Kazuma ONISHI, Tetsuya NITTA, Tatsuya SHIROMOTO, Shigeo TOKUMITSU
  • Patent number: 7982558
    Abstract: Method of manufacturing a MEMS device integrated in a silicon substrate. In parallel to the manufacturing of the MEMS device passive components as trench capacitors with a high capacitance density can be processed. The method is especially suited for MEMS resonators with resonance frequencies in the range of 10 MHz.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 19, 2011
    Assignee: NXP B.V.
    Inventors: Marc Sworowski, David D. R. Chevrie, Pascal Philippe
  • Publication number: 20110159649
    Abstract: Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Inventor: Masaaki Higashitani
  • Publication number: 20110159663
    Abstract: A method for fabricating a semiconductor device using optical proximity correction to form high integrated cell patterns that are less prone to bridge defects. The method includes: obtaining a target layout of cell patterns, which form rows in a cell region, and peripheral patterns of a peripheral region; forming oblique patterns, which are alternately overlapped in the rows of the cell patterns, and a reverse pattern of the peripheral patterns; attaching spacers to sidewalls of the oblique patterns and the reverse pattern; forming first burying patterns between the oblique patterns and a second burying pattern around the reverse pattern by filling gaps between the spacers; and forming the cell patterns by cutting and dividing the middle portions of the oblique patterns and the first burying patterns, and setting the peripheral pattern with the second burying pattern by removing the reverse pattern.
    Type: Application
    Filed: June 23, 2010
    Publication date: June 30, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Chun Soo KANG
  • Publication number: 20110156201
    Abstract: An air gap fabricating method is provided. A patterned sacrificial layer is formed over a substrate, and the material of the patterned sacrificial layer includes a germanium-antimony-tellurium alloy. A dielectric layer is formed on the patterned sacrificial layer. A reactant is provided to react with the patterned sacrificial layer and the patterned sacrificial layer is removed to form a structure with an air gap disposed at the original position of the patterned sacrificial layer.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Wei-Su Chen
  • Publication number: 20110140216
    Abstract: The present disclosure relates to a method of fabricating a micromachined CMOS-MEMS integrated device as well as the devices/apparatus resulting from the method. In the disclosed method, the anisotropic etching (e.g., DRIE) for isolation trench formation on a MEMS element is performed on the back side of a silicon wafer, thereby avoiding the trench sidewall contamination and the screen effect of the isolation beams in a plasma etching process. In an embodiment, a layered wafer including a substrate and a composite thin film thereon is subjected to at least one (optionally at least two) back side anisotropic etching step to form an isolation trench (and optionally a substrate membrane). The method overcomes drawbacks of other microfabrication processes, including isolation trench sidewall contamination.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 16, 2011
    Applicant: Oakland University
    Inventor: Hongwei Qu
  • Patent number: 7960290
    Abstract: A method for fabricating a semiconductor device. A preferred embodiment comprises forming a via in a semiconductor substrate, filling the via with a disposable material such as amorphous carbon, forming a dielectric layer on the substrate covering the via, performing a back side etch to expose the disposable material in the via. A back side dielectric layer is then depositing, covering the exposed via. A small opening is then formed, and the disposable material is removed, for example by an isotropic etch process. The via may now be filled with a metal and used as a conductor or a dielectric material. The via may also be left unfilled to be used as an air gap.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: June 14, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 7947566
    Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: May 24, 2011
    Assignee: International Business Machines Corporation
    Inventors: Howard Hao Chen, Louis Lu-Chen Hsu, Jack Allan Mandelman
  • Patent number: 7944018
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: May 17, 2011
    Assignee: Icemos Technology Ltd.
    Inventors: Samuel Anderson, Koon Chong So
  • Patent number: 7943488
    Abstract: A method includes placing a first bonding layer on at least one of a first functional region bonded on a release layer with a light releasable adhesive layer on a first substrate, and a transfer region on a second substrate; bonding the first functional region to the second substrate by the first bonding layer; irradiating the release layer with light with a light blocking member being provided to separate the first substrate from the first functional region at the release layer; placing a second bonding layer on at least one of a second functional region on the first substrate, and a transfer region on the release layer or a transfer region on a third substrate; bonding the second functional region to the second substrate or the third substrate by the second bonding layer; and separating the first substrate from the second functional region at the release layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 17, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 7943480
    Abstract: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Nicholas C. M. Fuller, David V. Horak, Elbert E. Huang, Wai-Kin Li, Anthony D. Lisi, Satyanarayana V. Nitta, Shom Ponoth
  • Publication number: 20110104866
    Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.
    Type: Application
    Filed: October 6, 2010
    Publication date: May 5, 2011
    Inventors: Hartmut Ruelke, Volker Jaschke
  • Publication number: 20110092046
    Abstract: An apparatus and method for holding a semiconductor device in a wafer. A bar is connected to the wafer. A first sidewall comprises a first end and a second, and is connected to the bar at its first end. A first tab comprises a first end and a second end, and is connected to the second end of the first sidewall at its first end and connected to the first side of the semiconductor device at its second end. The thickness of the first tab is less than the thickness of the bar and the thickness of the first sidewall.
    Type: Application
    Filed: December 28, 2010
    Publication date: April 21, 2011
    Applicant: APPLIED NANOSTRUCTURES, INC.
    Inventor: Ami Chand
  • Publication number: 20110076831
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Publication number: 20110062547
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Inventors: Kazuma ONISHI, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: 7892901
    Abstract: A silicon-on-insulator semiconductor device which includes a substrate; an insulator layer overlying the substrate; a plurality of strained silicon islands overlying the insulator layer, the strained silicon islands are isolated from each other by mesa isolation; and a plurality of transistors formed on the strained silicon islands. A method for fabricating the silicon-on-insulator semiconductor device is further disclosed.
    Type: Grant
    Filed: November 25, 2006
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yee-Chia Yeo, Chenming Hu
  • Patent number: 7892940
    Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
  • Patent number: 7879727
    Abstract: A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventors: Sergei Postnikov, Thomas Schulz, Hans-Joachim Barth, Klaus von Arnim
  • Patent number: 7867870
    Abstract: A device isolation film in a semiconductor device and a method for forming the same are provided. The method includes etching a middle portion of a device isolation film having a deposition structure including a Spin-On-Dielectric (SOD) oxide film and a High Density Plasma (HDP) oxide film to form a hole and filling an upper portion of the hole with an oxide film having poor step coverage characteristics to form a second hole extending along the middle portion of the device isolation film. The second hole serves as a buffer for stress generated at the interface between an oxide film, which can be a device isolation film, and a silicon layer, which can be a semiconductor substrate, thereby increasing the operating current of a transistor and improving the electrical characteristics of the resulting device.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Bong Jang
  • Patent number: 7868352
    Abstract: A Break Over Diode (“BOD”) device is a gate-less two terminal high power semiconductor switch in which transitions from a blocking state to a conducting state are triggered by a dV/dt pulse to the anode. The BOD device can be thought of as two cross-coupled PNP and NPN transistors, and includes both anode and cathode shorts which reduce the gain of the NPN and PNP transistors by shunting some current away from their bases directly to their emitters, thereby improving blocking. Moreover, the anode and cathode shorts in conjunction with the device blocking junction form PN diodes which are distributed throughout the bulk of the material and function as anti-parallel diodes to the base-emitter junctions of the PNP and NPN transistors, which enables the BOD device to handle a larger current reversal for a longer period of time. The P base layer may be made thin to decrease the voltage fall time from full blocking to full conduction, and the cathode and anode shorts may be provided in a honeycomb pattern.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: January 11, 2011
    Assignee: OptiSwitch Technology Corporation
    Inventors: David M. Giorgi, Tajchai Navapanich
  • Patent number: 7863072
    Abstract: A method for producing a micromechanical diaphragm sensor, and a micromechanical diaphragm sensor produced with the method. The micromechanical diaphragm sensor has at least one first diaphragm as well as a second diaphragm, which is disposed essentially on top of the first diaphragm. Furthermore, the micromechanical diaphragm sensor has a first cavity and a second cavity, which is essentially disposed above the first cavity.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: January 4, 2011
    Assignee: Robert Bosch GmbH
    Inventors: Matthias Illing, Heribert Weber, Christoph Schelling, Heiko Stahl, Stefan Weiss
  • Patent number: 7863150
    Abstract: A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew Earl Colburn, Daniel C. Edelstein, Satya Venkata Nitta, Sampath Purushothaman, Shom Ponth
  • Patent number: 7858480
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films; two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes; a source/drain region formed in a region of the semiconductor substrate sandwiching the two channel regions; a first stress film formed so as to cover the semiconductor substrate and the two gate electrodes; and a second stress film formed in at least a portion of a void, the void being formed in a region between the two gate electrodes.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Yamasaki
  • Publication number: 20100320436
    Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Jun Liu
  • Patent number: 7855139
    Abstract: Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: December 21, 2010
    Assignee: Sematech, Inc.
    Inventor: Gregory C. Smith
  • Publication number: 20100308444
    Abstract: In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.
    Type: Application
    Filed: March 19, 2010
    Publication date: December 9, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bin-Yuan Hung, Sung-Hui Huang, Wen Ting Tsai, Dian-Hau Chen, Ching Wei Hsieh
  • Patent number: 7842613
    Abstract: Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: November 30, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Kuolung Lei
  • Patent number: 7838373
    Abstract: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: November 23, 2010
    Assignee: Intel Corporation
    Inventors: Martin Giles, Titash Rakshit, Lucian Shifren, Jack Kavalieros, Willy Rachmady
  • Patent number: 7838390
    Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
  • Patent number: 7833890
    Abstract: Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Kim, June-mo Koo, Seung-hwan Song, Suk-pil Kim, Yoon-dong Park, Jong-jin Lee
  • Patent number: 7816253
    Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: October 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Qinghuang Lin, Kelly Malone, Sanjay Mehta, Terry A. Spooner, Chih-Chao Yang
  • Patent number: 7811924
    Abstract: Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 12, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Mehul Naik, Christopher D. Bencher, Kenneth MacWilliams
  • Patent number: 7811935
    Abstract: A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is removed substantially concurrently from the first and second trenches to expose substantially all of the dielectric liner within the second trench and to form a plug of the material in the one or more first trenches. A second layer of dielectric material is formed substantially concurrently on the plug in the first trench and on the exposed portion of the dielectric liner in the second trench. The second layer of dielectric material substantially fills a portion of the first trench above the plug and the second trench.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: October 12, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Sukesh Sandhu