Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 6846736
    Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. At least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening. A conductive material then substantially fills the at least one opening and at least one elongated passageway to form at least one electrical interconnect guided by the at least one elongated passageway and extended through the layer of dielectric material along the length to electrically connect at least two of the components of the integrated circuit.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: January 25, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Patent number: 6844238
    Abstract: A method for fabricating a multiple-gate device including the steps of providing a substrate of a semi-conducting layer on an insulator stack which includes an insulator layer overlying an etch-stop layer; patterning a semi-conducting layer forming a semiconductor fin; etching the insulator layer at the base of the fin forming an undercut; depositing a gate dielectric layer overlying the fin; depositing an electrically conductive layer over the gate dielectric layer; etching the electrically conductive layer forming a gate straddling across the two sidewall surfaces and the top surface of the fin; and forming a source region and a drain region in the fin.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: January 18, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu
  • Patent number: 6838355
    Abstract: A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wiring structure which contains a dielectric material having relatively high dielectric constant (i.e., 4.0 or higher). The damascene structure comprises the higher dielectric constant material immediately adjacent to the metal interconnects, thus benefiting from the mechanical characteristics of these materials, while incorporating the lower dielectric constant material in other areas of the interconnect level.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: January 4, 2005
    Assignee: International Business Machines Corporation
    Inventors: Anthony K. Stamper, Edward C. Cooney, III, Jeffrey P. Gambino, Timothy J. Dalton, John A. Fitzsimmons, Lee M. Nicholson
  • Patent number: 6835631
    Abstract: A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd
    Inventors: Zheng Jia Zhen, Sanford Chu, Ng Chit Hwei, Lap Chan, Purakh Raj Verma
  • Patent number: 6830987
    Abstract: An SOI semiconductor and method for making the same includes a substrate and dielectric support structures that support a silicon body above the substrate. This creates a void underneath the silicon body and thereby reduces the capacitance between the source/drain regions on body and the substrate.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario P. Pelella, Srinath Krishnan, William G. En, Witold P. Maszara
  • Publication number: 20040235262
    Abstract: A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 25, 2004
    Applicant: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Sheng Teng Hsu
  • Publication number: 20040229442
    Abstract: The present invention relates to a method for forming a high resistive region in a semiconductor device. A pattern having the bottom wider in width than the top such as a trench is formed in a region where an inductor will be formed by means of a two-step or multi-step etch processes. While forming an air gap at the corner of the bottom of the trench using a coverage characteristic of an insulating material, the trench is buried with the insulating material to easily form a high resistive region. Therefore, the present invention can minimize reduction in the quality factor (Q reduction) by preventing, by maximum, the eddy current from being generated in the substrate due to the inductor.
    Type: Application
    Filed: December 8, 2003
    Publication date: November 18, 2004
    Inventor: Kyeong Keun Choi
  • Patent number: 6818525
    Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: November 16, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: James A. Durham, Keith Kamekona, Brian Schoonover
  • Patent number: 6815310
    Abstract: A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: November 9, 2004
    Assignee: Intel Corporation
    Inventors: Brian Roberds, Brian S. Doyle
  • Patent number: 6812113
    Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics SA
    Inventors: Jerome Alieu, Christophe Lair, Michel Haond
  • Patent number: 6812544
    Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: November 2, 2004
    Assignee: Broadcom Corp.
    Inventors: Harry Contopanagos, Christos Komninakis
  • Patent number: 6791155
    Abstract: A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: September 14, 2004
    Assignee: Integrated Device Technology, Inc.
    Inventors: Guo-Qiang (Patrick) Lo, Brian Schorr, Gary Foley, Shih-Ked Lee
  • Patent number: 6780721
    Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6780755
    Abstract: A method of forming a multilevel conductor structure for ULSI circuits is provided. The structure includes a substrate having a plurality of dielectric supports extending from the substrate to support conductor layers. A removable material is deposited progressively on the substrate. An insulating ‘dome’ is formed over the conductor envelope and the material. Openings are provided through the dome for removing the material. The evacuated ‘dome envelope’ is filled with a near-unity dielectric constant gas or liquid at or above atmospheric pressure to enhance heat removal. The openings are sealed to provide a dielectric medium around the conductors within the envelope. Metal conductors within the envelope electrically connect active devices to other active regions as well as to the external environment.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: August 24, 2004
    Assignee: University of South Florida
    Inventor: Thomas E. Wade
  • Patent number: 6770537
    Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 3, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6764919
    Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: July 20, 2004
    Assignee: Motorola, Inc.
    Inventors: Kathleen C. Yu, Edward O. Travis, Bradley P. Smith
  • Patent number: 6756653
    Abstract: Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 29, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6750520
    Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: June 15, 2004
    Assignee: Fujitsu Limited
    Inventors: Hideo Kurihara, Mitsuteru Iijima, Kiyoshi Itano, Tetsuya Chida
  • Publication number: 20040108558
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an epitaxial source/drain junction layer having an insulating film thereunder. The method comprises the step of forming a under-cut under an epitaxial source/drain junction layer so that an insulating film filling the under-cut can be formed.
    Type: Application
    Filed: June 30, 2003
    Publication date: June 10, 2004
    Inventors: Byung Il Kwak, Kyung Jun Ahn
  • Patent number: 6746880
    Abstract: A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed of a semiconductor material is disposed between the semiconductor substrate and the substrate holder.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: June 8, 2004
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Martin Franosch, Matthias Goldbach, Volker Lehmann, Jörn Lützen
  • Patent number: 6737723
    Abstract: Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 18, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6734094
    Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: May 11, 2004
    Assignee: Intel Corporation
    Inventors: Grant M. Kloster, Jihperng Leu, Hyun-Mog Park
  • Patent number: 6730571
    Abstract: In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: May 4, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Cher Liang Cha, Kheng Chok Tee
  • Patent number: 6727157
    Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: April 27, 2004
    Assignee: Anam Semiconductor, Inc.
    Inventor: Young Hun Seo
  • Patent number: 6724027
    Abstract: A magnetic random access memory module includes a magnetic memory array. A permeable metal layer extends over a first side of the magnetic memory array. An electrically insulating layer is disposed between the permeable metal layer and the magnetic memory array.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: April 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Manoj K. Bhattacharyya, Darrel Bloomquist, Anthony Peter Holden, Sarah Morris Brandenberger
  • Patent number: 6696315
    Abstract: Cavities of submicron dimension are in a cavity layer of a semiconductor device. For that purpose, processing material is deposited on ridges of a working layer that is structured from ridges and trenches. The processing material is polymerized and the polymerizing processing material expands over the trenches. Upon covering the trenches, the submicron cavities are formed.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: February 24, 2004
    Assignee: Infineon Technologies AG
    Inventors: Rainer Leuschner, Egon Mergenthaler
  • Patent number: 6690081
    Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: February 10, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Hollie Reed, Paul Kohl, Chirag S. Patel, Kevin P. Martin, James Meindl
  • Patent number: 6677209
    Abstract: Techniques of shallow trench isolation and devices produced therefrom are shown. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device. The shallow trench isolation structures are used on a variety of substrates including silicon-on-insulator (SOI) substrates and silicon-on-nothing (SON) substrates.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 13, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. Farrar
  • Patent number: 6661068
    Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: December 9, 2003
    Assignee: Semiconductor Components Industries LLC
    Inventors: James A. Durham, Keith Kamekona, Brian Schoonover
  • Patent number: 6656782
    Abstract: The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: December 2, 2003
    Assignee: STMicroelectronics SA
    Inventors: Thomas Skotnicki, Stéphane Monfray, Alexandre Villaret
  • Patent number: 6632723
    Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Watanabe, Takashi Ohsawa, Kazumasa Sunouchi, Yoichi Takegawa, Takeshi Kajiyama
  • Patent number: 6627529
    Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: September 30, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Philip J. Ireland
  • Patent number: 6624031
    Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna, Jed H. Rankin, Edward W. Sengle, William R. Tonti
  • Patent number: 6596606
    Abstract: A method of forming a semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: July 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra Mouli
  • Patent number: 6589861
    Abstract: A method for fabricating a semiconductor device includes sequentially forming a stopping layer, an intermetal dielectric, and a capping layer on an interlayer dielectric, selectively removing the capping layer, the intermetal dielectric, and the stopping layer to partially expose a surface of the interlayer dielectric to form a hole, selectively removing a side of the intermetal dielectric within the hole, depositing a metal film on an entire surface including the hole to form an air gap in a portion where the side of the intermetal dielectric is removed, and planarizing an entire surface of the metal film to expose a surface of the capping layer to form a plurality of metal lines.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: July 8, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Heon Park, Yun Seok Cho
  • Publication number: 20030119246
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6570217
    Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: May 27, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Ichiro Mizushima, Yoshitaka Tsunashima, Toshihiko Iinuma, Kiyotaka Miyano
  • Patent number: 6566241
    Abstract: A method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region is provided. In the method, a contact pad is formed in the active metal contact region and the bit line contact region using a conductive plug. An etch stopper is formed on the upper sides of the conductive plug. A portion of a lower interlayer dielectric layer is etched so that the etch stopper protrudes above the lower interlayer dielectric layer. A bit line stack is formed in the bit line contact region. An etch stopper is formed in the active metal contact region. An upper interlayer dielectric layer is etched to expose the surfaces of the etch stopper and bit line capping layer pattern of the bit line stack. The exposed surfaces of the etch stopper and bit line capping layer pattern are etched to form a contact hole which exposes the conductive plug and a bit line conductive layer of the bit line stack. The contact hole is filled with a conductive layer.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: May 20, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yoon-soo Chun
  • Patent number: 6558989
    Abstract: A method for crystallizing an amorphous silicon film which includes the steps of: preparing a substrate having the amorphous silicon film, the amorphous silicon film being formed on an intermediate layer in which an inner space exists; applying an energy to the amorphous silicon film in order to crystallize the amorphous silicon film, wherein the step of preparing the substrate includes the steps of: forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, forming the amorphous silicon film on the intermediate layer,selectively removing the amorphous silicon film and the intermediate layer to expose a part of the material layer for forming space, and removing the material layer for forming space; or forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, selectively removing the intermediate layer to expose a part of the material layer, removing the mater
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: May 6, 2003
    Assignee: LG. Phillips LCD Co., Ltd.
    Inventor: Dae-Gyu Moon
  • Patent number: 6558983
    Abstract: A semiconductor apparatus is provided which includes a lateral high-voltage semiconductor device which comprises a silicon substrate, a pair of main electrodes formed on the silicon substrate, and a silicon oxide film formed on the silicon substrate, such that at least a part of the silicon oxide film is located between the main electrodes. The semiconductor device further includes a voltage withstanding structure formed on the silicon oxide film, which structure includes a first silicon nitride film having a refractive index of not lower than 2.8, and a second silicon nitride film formed on the first silicon nitride film and having a refractive index of not higher than 2.2.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: May 6, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaru Saitou, Gen Tada, Akio Kitamura
  • Patent number: 6544858
    Abstract: A silicon-containing polymer is deposited in a recess on the surface of the substrate. The substrate is then heated to a given temperature. The surface of the substrate, heated to the given temperature and having the silicon-containing polymer deposited thereon, is subjected to gas or vapor activated by a plasma or other electromagnetic radiation which is distinct from a source of heat used to heat the substrate to the given temperature.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: April 8, 2003
    Assignee: Trikon Equipments Limited
    Inventors: Knut Beekman, Jashu Patel
  • Publication number: 20030059344
    Abstract: A pin plate used to print a high density array printing of materials such as biological inks and a method for manufacturing the pin plate are described herein. The pin plate can be manufactured by coating a top surface of a silica wafer with a substantially thick layer of photoresist material. Next, a photolithography process is used to remove selected areas of the photoresist material from the silica wafer. Thereafter, a reactive ion etching process is used to form the pins in the silica wafer by etching away a predetermined amount of the top surface from the silica wafer that is not covered by the photoresist material. Afterwards, the remaining photoresist material is removed from the silica wafer which now resembles the pin plate.
    Type: Application
    Filed: September 24, 2001
    Publication date: March 27, 2003
    Inventors: Michael D. Brady, Martha B. Custer, Celine C. Guermeur, Richard C. Peterson, Christine M. Share
  • Publication number: 20030049914
    Abstract: A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a swelling agent is deposited on ridges of a working layer that is constructed of ridges and trenches. The processing material expands over the trenches during swelling; and covered cavities thus emerge from the trenches.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 13, 2003
    Inventors: Rainer Leuschner, Egon Mergenthaler
  • Patent number: 6524944
    Abstract: One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: February 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Ramkumar Subramanian, Michael K. Templeton
  • Publication number: 20030034532
    Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 20, 2003
    Inventors: John P. Snyder, John M. Larson
  • Patent number: 6500731
    Abstract: A process for producing a semiconductor device module comprises the steps of forming a first substrate having a separation layer having thereon a plurality of independent semiconductor layers and semiconductor devices individually formed on the plurality of semiconductor layers, electrically connecting the semiconductor devices one another on the first substrate, and separating the plurality of semiconductor layers from the first substrate at the separation layer to transfer the semiconductor layers to a second substrate.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: December 31, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsumi Nakagawa, Shoji Nishida
  • Patent number: 6498070
    Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes forming a sacrificial polymer film over a substrate having metal lines thereon. A portion of the sacrificial polymer film is subsequently removed to form first spacers. A micro-porous structure layer is formed over the substrate and the metal lines and between the first spacers. A portion of the micro-porous structure layer is removed to form second spacers. The first spacers are removed by thermal dissociation to form air gaps. A dielectric layer is formed over the substrate and the metal lines and between the second spacers.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: December 24, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Ting-Chang Chang, Yi-Shien Mor, Po-Tsun Liu
  • Patent number: 6492245
    Abstract: A process for forming air gap isolation regions between a bit line contact structure and adjacent capacitor structures, to reduce the capacitance of the space between these structures, has been developed. The process features the formation of insulator spacers on the sides of capacitor openings. After formation of capacitor structures, in the capacitor openings, top portions of the insulator spacers are exposed via a first selective etch procedure, allowing a second, selective, isotropic etch procedure to completely remove the insulator spacers creating the air gap isolation regions now located between the capacitor structure and an adjacent insulator layer. Subsequent deposition of an overlying insulator layer, comprised with poor conformality properties, allows coverage of the capacitor structures, however without filling the air gap isolation regions.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: December 10, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yuan-Hung Liu, Yeur-Luen Tu
  • Patent number: 6489215
    Abstract: Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate, and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: December 3, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Chandra V. Mouli, Fernando Gonzalez
  • Patent number: 6482657
    Abstract: A TMR element includes: a free layer formed on a lower gap layer; a tunnel barrier layer formed on the free layer; and a pinned layer formed on the tunnel barrier layer. In the step of forming the tunnel barrier layer on the free layer, an Al layer used for making the tunnel barrier layer is formed through sputtering, for example, on the free layer while the substrate is cooled. The Al layer is oxidized to form the tunnel barrier layer.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: November 19, 2002
    Assignee: TDK Corporation
    Inventor: Koji Shimazawa