Recessed Oxide Laterally Extending From Groove Patents (Class 438/426)
  • Publication number: 20080211037
    Abstract: A method of forming an isolation layer of a semiconductor device includes the steps of forming a gate insulating layer and a conductive layer on an active area of a semiconductor substrate; forming a spacer layer on side walls of the conductive layer; forming a trench on the semiconductor substrate between the spacer layer-covered side walls; removing the spacer layer to form a step on an upper edge of the trench; and forming a liner insulating layer on the trench. The method makes it possible to solve problems caused by impurities present in material with which the trench is gap-filled or present in etchants used in an etch-back process.
    Type: Application
    Filed: December 21, 2007
    Publication date: September 4, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Chan Sun Hyun
  • Patent number: 7416956
    Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: August 26, 2008
    Assignee: SanDisk Corporation
    Inventor: Jack H. Yuan
  • Patent number: 7410891
    Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: August 12, 2008
    Assignee: Third Dimension (3D) Semicondcutor, Inc.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7402498
    Abstract: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. A trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench. The trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material. The at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, H. Montgomery Manning
  • Patent number: 7396729
    Abstract: A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench such that the oxide layer is thicker on the beveled surfaces of the trench than on other surfaces of the trench.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Jeong, Wook-Hyoung Lee
  • Patent number: 7396738
    Abstract: A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed over the gate dielectric layer. An isolation trench is formed in the peripheral region, the isolation trench defining first and second trenches having different opening widths. A first gap-fill layer is provided over the isolation trench and on the step. The first gap-fill layer has a first portion on a sidewall of the insulating layer, a second portion on a sidewall of the gate dielectric layer, and a third portion at least partly filling the second trench of the isolation trench, the second portion being thicker than the first portion. A wet etch is performed to remove at least part of the first gap-fill layer. A second gap-fill layer is provided over the first gap-fill layer in the isolation trench to form an isolation structure.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: July 8, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Jung Lee
  • Patent number: 7396732
    Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: July 8, 2008
    Assignee: Interuniversitair Microelektronica Centrum vzw (IMEC)
    Inventor: Eddy Kunnen
  • Publication number: 20080160719
    Abstract: Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area; forming a third oxide layer along an inside of the trench; forming a fourth oxide layer to fill up the trench; forming a sacrificial oxide layer on the fourth oxide layer; and removing the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer so as to form the shallow trench isolation. Thus, it is possible to minimize the damage of a narrow active area when forming an element isolation area through an STI process.
    Type: Application
    Filed: March 6, 2008
    Publication date: July 3, 2008
    Inventor: Jae Suk Lee
  • Publication number: 20080138958
    Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.
    Type: Application
    Filed: February 15, 2008
    Publication date: June 12, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sang Don LEE
  • Publication number: 20080124893
    Abstract: In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.
    Type: Application
    Filed: July 2, 2007
    Publication date: May 29, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Hwan Kim, Chang-Woo Oh, Yong-Lack Choi, Na-Young Kim
  • Patent number: 7303951
    Abstract: A method of manufacturing a semiconductor device for preventing dielectric breakdown of gate electrodes attributable to needle-like protrusions caused inside a trench in the step of forming element isolation trench in which includes forming a silicon oxide film over a silicon nitride film as an etching mask for forming element isolation trenches, then cleaning the surface of a substrate with a hydrofluoric acid etching solution to lift off obstacles deposited over the surface of the silicon oxide film, before the step of patterning the silicon nitride film by using as a mask a photoresist film provided with an anti-reflection film therebelow.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: December 4, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Kanamitsu, Takashi Moriyama, Naohiro Hosoda
  • Patent number: 7291540
    Abstract: The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit light, allowing a photodetector to respond to transmitted light to stimulate a retina, for example. Discrete electronic components may be placed in the three-dimensional street area of the integrated circuit package, yielding a completely integrated hermetic package that is implantable in living tissue.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: November 6, 2007
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Brian V. Mech, Robert J. Greenberg, Gregory J. DelMain
  • Patent number: 7265022
    Abstract: A method of fabricating a semiconductor device, includes depositing, on a semiconductor substrate, a gate insulating film, a polycrystalline or amorphous silicon film, a silicon nitride film and a silicon oxide film sequentially, patterning a resist for forming a plurality of trenches on an upper surface of the substrate so as to have opening widths differing from each other, etching the silicon oxide film and the silicon nitride film formed on the substrate by an reactive ion etching (RIE) process with the resist serving as a mask, and etching the polycrystalline or amorphous silicon film, the gate insulating film and the substrate by the RIE process with the etched silicon oxide film and silicon nitride film serving as a mask using reactive plasma including a halogen gas, fluorocarbon gas, Ar and O2, thereby simultaneously forming the trenches with opening widths differing from each other.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Ito, Hiroaki Tsunoda, Takanori Matsumoto
  • Patent number: 7241665
    Abstract: A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: July 10, 2007
    Assignee: SilTerra Malaysia Sdn. Bhd.
    Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Ch'ng Toh Ghee, Ramakrishnan Rajagopal, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Charlie Tay, Chang Gi Lee, Hitomi Watanabe, Naoto Inoue
  • Publication number: 20070155128
    Abstract: Provided is a method for forming a trench, capable of rounding a top corner without adding a separate mask or process. In the method, first and second insulating layers are stacked on a substrate having an isolation region and an active region. Subsequently, a photoresist pattern is formed on the second insulating layer, and the first and second insulating layers are patterned using the photoresist pattern as a mask to expose a portion of a substrate in the isolation region. After that, the substrate is etched using the first and second pad insulating layers as a mask to form an STI region such that an upper width of the STI region is greater than a lower width of the STI region.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 5, 2007
    Inventor: Kee Joon Choi
  • Patent number: 7208390
    Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: April 24, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rana P. Singh, Paul A. Ingersoll
  • Patent number: 7205206
    Abstract: Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: April 17, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Belyansky, Bruce B. Doris, Oleg Gluschenkov
  • Patent number: 7179717
    Abstract: Forming an integrated circuit device includes forming a hard mask layer overlying a semiconductor substrate. The hard mask layer is patterned to expose portions of the substrate and edges of the hard mask layer. Exposed portions of the substrate are removed. A first portion of the substrate is covered with a photoresist layer while leaving a second portion exposed. The exposed edges of the hard mask are recessed to expose a third portion of the substrate. Recessing the exposed edges of the hard mask includes using at least a dry-etch chemistry. The exposed second and third portions of the substrate are oxidized.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: February 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sukesh Sandhu, Kevin Torek
  • Patent number: 7169697
    Abstract: Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: January 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Seta, Makoto Sekine, Naofumi Nakamura
  • Patent number: 7163871
    Abstract: A manufacturing method of a semiconductor device having a trench is provided to form, at a corner portion of the trench, an oxide film which is greater in thickness and smaller in stress than at other portions. When the trench formed in the semiconductor substrate is oxidized, it is oxidized in an oxygen environment containing dichloroethylene at a predetermined weight percent to allow the formation of an oxide film having a greater thickness at the corner portion of the trench than thickness at other portions, whereby the semiconductor device improving dielectric breakdown characteristics can be obtained.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: January 16, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Taishi Kubota, Yoshihiro Kitamura, Takuo Ohashi, Susumu Sakurai, Takayuki Kanda, Shinichi Horibe
  • Patent number: 7160789
    Abstract: A shallow trench isolation (STI) structure and a method of forming the STI structure. The STI structure defines an active region formed with a recess channel transistor. The STI structure includes a STI trench has a laterally curved rounding portion on the bottom of the recess channel trench. In order to form the STI trench with the rounding portion, a semiconductor substrate is selectively and anisotropically dry etched to form the trench. Then, the semiconductor substrate is isotropically etched around the bottom height of the recess channel trench to form the rounding portion, and then further anisotropically dry etched, thereby forming the STI trench. After an insulating layer that fill the STI trench is formed on the resultant structure, an upper surface of the resultant structure is planarized to expose a surface of the semiconductor substrate.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: January 9, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Chul Park
  • Patent number: 7135379
    Abstract: A method of forming isolation trenches in a semiconductor fabrication process to reduce transistor channel edge effect currents includes forming a masking structure overlying a substrate to expose a first area of the substrate. Spacers are formed on sidewalls of the masking structure. The spacers cover a perimeter region of the first area thereby leaving a second smaller area exposed. The region underlying the second area is etched to form an isolation trench that is then filled with a dielectric. The spacers are removed to expose the perimeter region. Using the masking structure and the trench dielectric as a mask, an impurity distribution is implanted into a portion of the substrate underlying the perimeter region. The impurity distribution thus surrounds a perimeter of the trench dielectric proximal to an upper surface of the substrate. The perimeter impurity distribution dopant, in a typical case, is p-type for NMOS transistors and n-type for PMOS.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: November 14, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, James D. Burnett
  • Patent number: 7132349
    Abstract: An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active region. An epitaxial silicon layer extends from the active region through the insulation layer to a substrate beneath the insulation layer.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: November 7, 2006
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Sung-min Kim, Dong-gun Park, Chang-sub Lee, Jeong-dong Choe, Shin-ae Lee, Seong-ho Kim
  • Patent number: 7112511
    Abstract: A method for fabricating a CMOS image sensor with a prism includes the steps of: forming a plurality of photodiodes corresponding to respective unit pixels on a substrate; sequentially forming an inter-layer insulation layer and an uppermost metal line on the substrate and the photodiodes; etching the inter-layer insulation layer to form a plurality of trenches corresponding to the respective photodiodes; depositing a high density plasma (HDP) oxide layer such that the HDP oxide layer disposed between the trenches has a tapered profile; depositing a nitride layer having a higher refractive index than that of the inter-layer insulation layer to fill the trenches; and depositing an insulation layer having a lower refractive index than that of the nitride layer to fill the trenches, thereby forming a prism, wherein the prism induces a total reflection of lights incident to the photodiodes disposed in edge regions of a pixel array.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: September 26, 2006
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Hee Jeong Hong
  • Patent number: 7112510
    Abstract: Methods for forming a device isolating barrier, and methods for forming a gate electrode using the device isolation barrier are disclosed. In an illustrated method, a semiconductor device isolating barrier is formed by forming a pad oxide layer and a first nitride layer on a semiconductor substrate; forming a trench region by etching the pad oxide layer and the first nitride layer; forming spacers at sidewalls of the etched pad oxide layer and the etched first nitride layer; forming a first trench by etching the semiconductor substrate using the spacers and the etched first nitride layer as a mask; and, after forming a liner oxide layer and an oxide layer filling the trench, forming the device isolating barrier by flattening the liner oxide layer and the trench oxide layer to expose the etched first nitride layer.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: September 26, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kae Hoon Lee
  • Patent number: 7098115
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: 7091105
    Abstract: Disclosed is a method of forming the isolation film in the semiconductor device which can prevent concentration of an electric field by forming a dual slant angle at the top corner of the trench in the course of forming the trench. After a photoresist pattern containing silicon components or an amorphous silicon film is formed on a pad oxide film instead of a pad nitride film, the surface of the photoresist pattern or the amorphous silicon film is oxidized so that the oxidized portion is fused with the isolation film. Accordingly, it is possible to prevent generation of a moat in the course of removing the photoresist pattern and the pad oxide film after the trench is buried with an insulating material. Therefore, the disclosed method can improve reliability of the process and an electrical characteristic of the resulting device.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: August 15, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Won Kwon Lee
  • Patent number: 7081397
    Abstract: A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: July 25, 2006
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Baiocco, An L. Steegen, Ying Zhang
  • Patent number: 7071073
    Abstract: For manufacturing an SOI substrate, the following steps are carried out: providing a wafer of semiconductor material; forming, inside the wafer, a plurality of passages forming a labyrinthine cavity and laterally delimiting a plurality of pillars of semiconductor material; and oxidizing the pillars of semiconductor material to form a buried insulating layer. For forming the labyrinthine cavity, a trench is first formed in a substrate; an epitaxial layer is grown, which closes the trench at the top; the wafer is annealed so as to deform the pillars and cause them to assume a minimum-energy handlebar-like shape, and a peripheral portion of the wafer is removed to reach the labyrinthine cavity, and side inlet openings are formed in the labyrinthine cavity. Oxidation is performed by feeding an oxidizing fluid through the side inlet openings.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: July 4, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Flavio Villa, Gabriele Barlocchi, Pietro Corona
  • Patent number: 7023069
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: April 4, 2006
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6989561
    Abstract: Afin-type trench capacitor structure includes a buried plate diffused into a silicon substrate. The buried plate, which surrounds a bottle-shaped lower portion of the trench capacitor structure, is electrically connected to an upwardly extending annular poly electrode, thereby enabling the buried plate and the annular poly electrode to constitute a large-area capacitor electrode of the trench capacitor structure. A capacitor storage node consisting of a surrounding conductive layer, a central conductive layer and a collar conductive layer encompasses the upwardly extending annular poly electrode. A first capacitor dielectric layer isolates the capacitor storage node from the buried plate. A second capacitor dielectric layer and a third capacitor dielectric layer isolate the upwardly extending annular poly electrode from the capacitor storage node.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 24, 2006
    Assignee: Nanya Technology Corp.
    Inventors: Shian-Jyh Lin, Sam Liao, Chia-Sheng Yu
  • Patent number: 6969666
    Abstract: A method for fabricating an isolation layer in a semiconductor device is disclosed. The method comprises the steps of: forming a pad oxide film and a pad nitride film sequentially on a semiconductor substrate defining a cell region and a peripheral region; forming a trench on the semiconductor substrate by etching the pad oxide film, the pad nitride film and the substrate; forming an oxide film of side walls on a surface of the trench; depositing an amorphous silicon film on a resultant substrate inclusive of the trench; etching the amorphous silicon film so that the trench is partly filled; depositing an insulation film on a resultant substrate so that the partly filled trench is filled completely; carrying out a CMP process of the insulation film to expose the pad nitride film; and removing the pad nitride film.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: November 29, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Ho Pyi
  • Patent number: 6967141
    Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: November 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Kanamitsu, Kouzou Watanabe, Norio Suzuki, Norio Ishitsuka
  • Patent number: 6943088
    Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: September 13, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf van Bentum, Stephan Kruegel, Gert Burbach
  • Patent number: 6939779
    Abstract: On a substrate (1), a silicon oxide film (2) is formed. Thereon, a silicon nitride film (3) is formed. And, an opening for a trench is formed by patterning these films. Then, an oxide film including fluorine (8) is formed on the substrate (1). A fluorine diffusing layer (9) is formed by diffusing fluorine from the oxide film including fluorine (8) with its width wider than the opening for a trench. Then a trench (4) is formed, leaving fluorine diffusing layer portions (9a). After this, a thermal oxide film is formed on the inner wall of trench (4). Then the thermal oxide film includes fluorine near the corner of trench (4). This is diffused from the fluorine diffusing layer portions (9a). After all this, the trench (4) is filled with oxide film (6).
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: September 6, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masashi Takahashi
  • Patent number: 6936522
    Abstract: A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 30, 2005
    Assignee: International Business Machines Corporation
    Inventors: An L. Steegen, Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert Wong
  • Patent number: 6933159
    Abstract: In a method for fabricating a semiconductor laser device, a plurality of grooves are formed in a surface of one conductive type of an InP layer. The InP layer is thermally treated in an atmosphere including at least a gas containing phosphorus and a gas containing arsenic in a mixed state, thereby forming a plurality of active regions made of InAsP in the plurality of grooves. An other conductive type of semiconductor layer is formed after the active regions are formed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: August 23, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Kito, Masato Ishino, Tomoaki Toda, Yoshiaki Nakano
  • Patent number: 6924542
    Abstract: A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: August 2, 2005
    Assignee: ProMos Technologies, Inc.
    Inventors: Hua Ji, Dong Jun Kim, Jin-Ho Kim, Chuck Jang
  • Patent number: 6924209
    Abstract: A method for the fabrication of an integrated semiconductor component, in which at least one isolation trench is formed, a first layer of a nonconductive material is applied by a nonconformal deposition method, and a second layer of a nonconductive material is applied by a conformal deposition method at least to the back surface of the semiconductor component.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: August 2, 2005
    Assignee: Infineon Technologies AG
    Inventors: Hans-Peter Moll, Alexander Trueby, Andreas Wich-Glasen
  • Patent number: 6919612
    Abstract: An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: July 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, Shawn D. Lyonsmith, Regan S. Tsui
  • Patent number: 6913978
    Abstract: A method of fabricating a shallow trench isolation structure is disclosed. On a substrate, a pad oxide layer and a mask layer are successively formed. The pad oxide layer, the mask layer and a portion of the substrate are patterned to form a trench. After performing a rapid wet thermal process, a liner layer is formed on the exposed surface of the substrate, including the exposed silicon surface of the substrate in the trench and sidewalls and the surface of the mask layer. An oxide layer is deposited over the trench and the substrate and fills the trench. A planarization process is performed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to complete the shallow trench isolation structure.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: July 5, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Kuo Chen, Hsiu-Chuan Chu, Chih-An Huang, Hsiao-Ling Lu, Teng-Chun Tsai
  • Patent number: 6908830
    Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: June 21, 2005
    Assignee: International Business Machines Corporation
    Inventors: Andrew Lu, Donald M. Odiwo, Roger J. Yerdon
  • Patent number: 6905942
    Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: June 14, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Kazuo Tomita
  • Patent number: 6890833
    Abstract: A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: May 10, 2005
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Michael Belyansky, Andreas Knorr, Oleg Gluschenkov, Christopher Parks
  • Patent number: 6890832
    Abstract: A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (1013 to 1017 ions/cm2) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The implant is followed by an implant of a large group V element, such as P, As, Sb, or Bi using similar doses and energies to the group III element. The group V element compensates the group III element. The combination of the two large atoms decreases the diffusivity of small atoms, such as B, in the implanted areas. Furthermore, the combination of the group III and group V elements in roughly equal proportions creates recombination sites and electron traps in the field oxide, resulting in a radiation hardened semiconductor device.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: May 10, 2005
    Assignee: Aeroflex UTMC Microelectronic Systems, Inc.
    Inventors: David B. Kerwin, Bradley J Larsen
  • Patent number: 6887767
    Abstract: A method for manufacturing a semiconductor device including forming a buffer film on a semiconductor substrate, forming a element partitioning trench, forming a oxidized film on the surface of the element partitioning trench, and washing the semiconductor substrate with hydrofluoric acid. The washing removes part of the buffer film, and the end of the buffer film is inwardly removed from the top edge of the element partitioning trench by a predetermined distance. The distance and the thickness of the oxidized film are represented by the expression 0?x?(d/2 sin ?), where x represents the distance, and ? represents the angle between a plane parallel to the semiconductor substrate and a side surface of the element partitioning trench.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: May 3, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mayumi Nakasato, Kazuhiro Sasada, Masahiro Oda
  • Patent number: 6869859
    Abstract: A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in a second region. After that, by performing side etching of the pad oxide film of the first region while protecting the second region with a resist, a gap is formed between the substrate and the silicon nitride film. Subsequently, the inner surfaces of the first and second trenches are oxidized. At this time, a relatively large volume of oxidizing agent (oxygen) is supplied to a top edge portion of the first trench, and the curvature of the corner of the substrate increases.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: March 22, 2005
    Assignee: Fujitsu Limited
    Inventor: Hitoshi Saito
  • Patent number: 6858516
    Abstract: A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: February 22, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tzu-En Ho, Chang Rong Wu, Hsin-Jung Ho
  • Patent number: 6846721
    Abstract: A semiconductor device ensuring an isolation of elements by a trench is provided. A method of manufacturing the semiconductor device includes the step of forming a silicon nitride film having an aperture, the step of selectively removing a part of a silicon substrate along aperture to form a recess defined by a side surface and a bottom surface in silicon substrate, the step of oxidizing the side surface and the bottom surface of the recess to form a thermal oxide film having a side portion and a bottom portion, and the step of selectively removing bottom portion of thermal oxide film and a part of silicon substrate by using silicon nitride film as a mask to form a trench.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: January 25, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Shu Shimizu
  • Patent number: 6841452
    Abstract: A silicon oxide film having a ununiform thickness is deposited inside each of trenches defined in a silicon substrate by etching within a device isolation region, in such a manner that only corner portions of trench bottoms are exposed. The silicon substrate is selectively etched from the exposed trench corner portions of the silicon substrate lying inside the trenches to thereby increase the volume of each trench.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: January 11, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroyuki Tanaka