Conformal Insulator Formation Patents (Class 438/437)
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Publication number: 20140227858Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.Type: ApplicationFiled: February 13, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong, Sang Cheol Han, Tae Hoon Kim, Ja Hyung Han, Haigou Huang, Changyong Xiao, Huang Liu, Seung Yeon Kim
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Patent number: 8778751Abstract: A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle ? in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body.Type: GrantFiled: September 19, 2011Date of Patent: July 15, 2014Assignee: Infineon Technologies Austria AGInventor: Martin Poelzl
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Patent number: 8772904Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.Type: GrantFiled: June 13, 2012Date of Patent: July 8, 2014Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Chia-Lung Chang, Jei-Ming Chen, Jui-Min Lee, Yuh-Min Lin
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Publication number: 20140145251Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Laurent Favennec, Arnaud Tournier, François Roy
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Publication number: 20140134827Abstract: A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.Type: ApplicationFiled: November 7, 2013Publication date: May 15, 2014Applicant: Novellus Systems, Inc.Inventors: Shankar Swaminathan, Bart van Schravendijk, Adrien Lavoie, Sesha Varadarajan, Jason Daejin Park, Michal Danek, Naohiro Shoda
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Publication number: 20140127879Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgas sing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
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Patent number: 8709901Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.Type: GrantFiled: April 17, 2013Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Lung Chang, Wu-Sian Sie, Jei-Ming Chen, Wen-Yi Teng, Chih-Chien Liu, Jui-Min Lee, Chih-Hsun Lin
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Publication number: 20140099775Abstract: A method for fabricating a semiconductor device with mini-SONOS cell is disclosed. The method includes: providing a semiconductor substrate having a first MOS region and a second MOS region; forming a first trench in the semiconductor substrate between the first MOS region and the second MOS region; depositing a oxide liner and a nitride liner in the first trench; forming a STI in the first trench; removing a portion of the nitride liner for forming a second trench between the first MOS region of the semiconductor substrate and the STI and a third trench between the STI and the second MOS region of the semiconductor substrate; and forming a first conductive type nitride layer in the second trench.Type: ApplicationFiled: December 16, 2013Publication date: April 10, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventor: YA YA SUN
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Patent number: 8691659Abstract: A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.Type: GrantFiled: October 26, 2011Date of Patent: April 8, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Pin Hsu, Yi-Po Lin, Jiunn-Hsiung Liao, Chieh-Te Chen, Feng-Yi Chang, Shang-Yuan Tsai, Li-Chiang Chen
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Patent number: 8680602Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.Type: GrantFiled: March 6, 2012Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Jae-Bok Baek
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Patent number: 8679941Abstract: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 ?-100 ?) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.Type: GrantFiled: March 16, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Jason E Cummings, Lisa F Edge, Balasubramanian S. Haran, David V Horak, Hemanth Jagannathan, Sanjay Mehta
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Publication number: 20140073111Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.Type: ApplicationFiled: September 9, 2012Publication date: March 13, 2014Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
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Patent number: 8652933Abstract: Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material.Type: GrantFiled: November 11, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Paul C. Parries, Yanli Zhang
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Publication number: 20140030869Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Juengling Werner, Richard Lane
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Publication number: 20140015092Abstract: A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael V. Aquilino, Xiang Hu, Daniel J. Jaeger, Byeong Y. Kim, Yong M. Lee, Ying Li, Reinaldo A. Vega
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Publication number: 20140017875Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Toshitake YAEGASHI, Koki Ueno
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Patent number: 8614138Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a lower mask film on a semiconductor substrate. The method includes forming a barrier film in a first area. The method includes forming an upper mask film. The method includes removing an upper mask member and leaving a lower mask member in the first area and removing the upper mask member and the lower mask member in the second area. The removing is performed by etching in a condition in which an etching rate of the upper mask member and an etching rate of the lower mask member are higher than that of the barrier member. The method includes forming a conductive film. The method includes selectively removing the conductive film by performing etching in a condition in which an etching rate of the conductive film is higher than that of the lower mask member.Type: GrantFiled: August 22, 2012Date of Patent: December 24, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Gaku Sudo
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Patent number: 8603895Abstract: In one example, the method includes forming a patterned etch mask above a semiconducting substrate, performing an etching process through the patterned etch mask to thereby form a trench in the substrate, performing a first deposition process to form a first layer of insulating material above the patterned etch mask and in the trench, and performing an etching process on the first layer of insulating material such that the post-etch thickness of the first layer of insulating material is less than an as-deposited thickness of the first layer of insulating material. The method also includes performing a second deposition process to form a second layer of insulating material on the etched first layer of insulating material, wherein the second layer of insulating material overfills the trench, and removing portions of the etched first layer of insulating material and the second layer of insulating material positioned above the patterned etch mask.Type: GrantFiled: September 11, 2012Date of Patent: December 10, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Jakubowski, Joerg Radecker, Ralf Willecke
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Patent number: 8580653Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.Type: GrantFiled: February 25, 2013Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
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Publication number: 20130288452Abstract: The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Inventors: Shyue Seng TAN, Ying Keung LEUNG, Elgin QUEK
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Patent number: 8501633Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.Type: GrantFiled: August 10, 2012Date of Patent: August 6, 2013Assignee: Synos Technology, Inc.Inventor: Sang In Lee
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Publication number: 20130193548Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.Type: ApplicationFiled: September 14, 2012Publication date: August 1, 2013Applicant: SK HYNIX INC.Inventor: Tai Ho KIM
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Patent number: 8492868Abstract: A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.Type: GrantFiled: August 2, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Alan B. Botula, Alvin J. Joseph, James A. Slinkman, Randy L. Wolf
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Publication number: 20130161783Abstract: A semiconductor device includes an isolation trench formed in a semiconductor substrate; an isolation layer filling the isolation trench; and a first epitaxial layer interposed between the isolation layer and the semiconductor substrate, wherein a lattice structure of the semiconductor substrate has an angle difference from a lattice structure of the first epitaxial layer adjacent to the semiconductor substrate.Type: ApplicationFiled: September 6, 2012Publication date: June 27, 2013Inventors: Jeong-Seob OH, Young-Soo Ahn
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Patent number: 8470686Abstract: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 ? over the layer of porous aluminum oxide.Type: GrantFiled: April 17, 2012Date of Patent: June 25, 2013Assignee: Micron Technology, Inc.Inventors: Chris W. Hill, Garo J. Derderian
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Patent number: 8450183Abstract: A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.Type: GrantFiled: December 7, 2010Date of Patent: May 28, 2013Assignee: Mitsubishi Electric CorporationInventors: Ryoichi Fujii, Shigeto Honda, Atsushi Narazaki, Kaoru Motonami
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Patent number: 8440580Abstract: A method for fabricating a silicon nitride gap-filling layer is provided. A pre-multi-step formation process is performed to form a stacked layer constituting as a dense film on a substrate. Then, a post-single step deposition process is conducted to form a cap layer constituting as a sparse film on the stacked layer, wherein the cap layer has a thickness of at least 10% of the total film thickness.Type: GrantFiled: September 11, 2007Date of Patent: May 14, 2013Assignee: United Microelectronics Corp.Inventors: Neng-Kuo Chen, Chao-Ching Hsieh, Chien-Chung Huang
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Publication number: 20130102125Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajasekhar Venigalla, Michael Vincent Aquilino, Massud A. Aminpur, Michael P. Belyansky, Unoh Kwon, Christopher Duncan Sheraw, Daewon Yang
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Patent number: 8426274Abstract: Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.Type: GrantFiled: August 23, 2010Date of Patent: April 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Ho Yoon, Kyoung-Sub Shin, Sung-Sam Lee, Kung-Hyon Nam, Hong Cho, Joon-Seok Moon
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Patent number: 8404561Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.Type: GrantFiled: May 5, 2010Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
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Patent number: 8384188Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.Type: GrantFiled: May 14, 2012Date of Patent: February 26, 2013Assignee: Hynix Semiconductor Inc.Inventor: Hyung-Hwan Kim
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Patent number: 8372761Abstract: A silicon oxide film is formed in a processing chamber of a plasma processing apparatus by performing oxidation process, by using plasma to a processing object having a patterned irregularity, wherein the plasma is generated while high-frequency power is supplied to a mount table under the conditions that the oxygen content in a process gas is not less than 0.5% and less than 10% and the process pressure is 1.3 to 665 Pa.Type: GrantFiled: March 28, 2008Date of Patent: February 12, 2013Assignee: Tokyo Electron LimitedInventors: Yoshiro Kabe, Takashi Kobayashi, Toshihiko Shiozawa, Junichi Kitagawa
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Patent number: 8343846Abstract: A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.Type: GrantFiled: June 2, 2008Date of Patent: January 1, 2013Inventor: Cha Deok Dong
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Patent number: 8318584Abstract: The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.Type: GrantFiled: June 3, 2011Date of Patent: November 27, 2012Assignee: Applied Materials, Inc.Inventors: DongQing Li, Jingmei Liang, Nitin K. Ingle
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Patent number: 8313661Abstract: A liner removal process is described, wherein an excess portion of a conformal liner formed in a trench is substantially removed while reducing or minimizing damage to a bulk fill material in the trench.Type: GrantFiled: November 9, 2009Date of Patent: November 20, 2012Assignee: Tokyo Electron LimitedInventors: Vinh Luong, Akiteru Ko
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Patent number: 8294238Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.Type: GrantFiled: April 22, 2010Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kutsukake, Takayuki Toba, Yoshiko Kato, Kenji Gomikawa, Haruhiko Koyama
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Publication number: 20120252188Abstract: A plasma processing method for use in device isolation by shallow trench isolation in which an insulating film is embedded in a trench formed in silicon and the insulating film is planarized to form a device isolation film, the method includes a plasma nitriding the silicon of an inner wall surface of the trench by using a plasma before embedding the insulating film in the trench. The plasma nitriding is performed by using a plasma of a processing gas containing a nitrogen-containing gas under conditions in which a processing pressure ranges from 1.3 Pa to 187 Pa and a ratio of a volumetric flow rate of the nitrogen-containing gas to a volumetric flow rate of the entire processing gas ranges from 1% to 80% such that a silicon nitride film is formed on the inner wall surface of the trench to have a thickness of 1 to 10 nm.Type: ApplicationFiled: March 28, 2012Publication date: October 4, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Ryota YONEZAWA, Kazuyoshi Yamazaki, Masaki Sano
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Patent number: 8258028Abstract: Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.Type: GrantFiled: February 9, 2010Date of Patent: September 4, 2012Assignee: Infineon Technologies AGInventors: Armin Tilke, Danny Pak-Chum Shum, Laura Pescini, Ronald Kakoschke, Karl Robert Strenz, Martin Stiftinger
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Patent number: 8227318Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.Type: GrantFiled: November 19, 2009Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Max Levy, Natalie Feilchenfeld, Richard Phelps, BethAnn Rainey, James Slinkman, Steven H. Voldman, Michael Zierak, Hubert Enichlmair, Martin Knaipp, Bernard Loeffler, Rainer Minixhofer, Jong-Mun Park, Georg Roehrer
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Patent number: 8217472Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.Type: GrantFiled: July 7, 2011Date of Patent: July 10, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Richard J. Carter, George J. Kluth, Michael J. Hargrove
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Patent number: 8202784Abstract: A semiconductor device having high aspect ratio isolation trenches and a method for manufacturing the same is presented. The semiconductor device includes a semiconductor substrate, a first insulation layer, and a second insulation layer. The semiconductor substrate has a second trench that is wider than a first trench. The first insulation layer is partially formed within the wider second trench in which the first insulation layer when formed clogs the opening of the narrower first trench. A cleaning of the first insulation layer unclogs the opening of the narrower first trench in which a second insulation layer can then be formed within both the first and second trenches.Type: GrantFiled: August 16, 2011Date of Patent: June 19, 2012Assignee: Hynix Semiconductor Inc.Inventor: Tai Ho Kim
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Publication number: 20120149172Abstract: A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Jen-Jui Huang, Hung-Ming Tsai
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Patent number: 8198171Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.Type: GrantFiled: December 17, 2009Date of Patent: June 12, 2012Assignee: Hynix Semiconductor Inc.Inventor: Hyung-Hwan Kim
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Publication number: 20120112288Abstract: The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.Type: ApplicationFiled: March 2, 2011Publication date: May 10, 2012Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu, Huicai Zhong
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Patent number: 8173517Abstract: The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.Type: GrantFiled: July 1, 2010Date of Patent: May 8, 2012Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, David L. Chapek, Randhir P. S. Thakur
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Publication number: 20120094468Abstract: Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.Type: ApplicationFiled: July 14, 2011Publication date: April 19, 2012Applicant: Applied Materials, Inc.Inventors: Sidharth Bhatia, Hiroshi Hamana, Paul Edward Gee, Shankar Venkataraman
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Patent number: 8158488Abstract: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 ? over the layer of porous aluminum oxide.Type: GrantFiled: August 31, 2004Date of Patent: April 17, 2012Assignee: Micron Technology, Inc.Inventors: Chris W Hill, Garo J Derderian
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Patent number: 8153502Abstract: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.Type: GrantFiled: May 16, 2006Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: Li Li, Ronald Weimer, Richard Stocks, Chris Hill
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Publication number: 20120034757Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.Type: ApplicationFiled: June 16, 2011Publication date: February 9, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Soon Choi, Jun-Won Lee, Gil-Heyun Choi, Eunkee Hong, Hong-Gun Kim, Ha-Young Yi
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Publication number: 20120007218Abstract: A method for fabricating a semiconductor device includes forming a plurality of first trenches by etching a substrate, forming first spacers covering both sidewalls of each of the first trenches, forming a plurality of second trenches by etching a bottom of each of the first trenches, forming second spacers covering both sidewalls of each of the second trenches, forming a plurality of third trenches by etching a bottom of each of the second trenches, forming an insulation layer covering exposed surfaces of the plurality of the substrate, and forming a contact which exposes one sidewall of each of the second trenches by selectively removing the second spacers.Type: ApplicationFiled: December 29, 2010Publication date: January 12, 2012Inventor: You-Song KIM