Conformal Insulator Formation Patents (Class 438/437)
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Patent number: 8062955Abstract: A CoWB film is formed as a cap metal on a Cu interconnection line formed on a substrate or wafer W, by repeating a plating step and a post-cleaning step a plurality of times. The plating step is arranged to apply electroless plating containing CoWB onto the Cu interconnection line. The post-cleaning step is arranged to clean the wafer W by use of a cleaning liquid, after the plating step.Type: GrantFiled: June 22, 2007Date of Patent: November 22, 2011Assignee: Tokyo Electron LimitedInventors: Takashi Tanaka, Kenichi Hara, Mitsuaki Iwashita
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Patent number: 8058161Abstract: A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.Type: GrantFiled: September 29, 2006Date of Patent: November 15, 2011Assignee: Texas Instruments IncorporatedInventors: Gabriel George Barna, Andrew Marshall, Brian K. Kirkpatrick
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Publication number: 20110260238Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.Type: ApplicationFiled: December 28, 2010Publication date: October 27, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Seung Bum KIM
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Patent number: 8043933Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.Type: GrantFiled: November 18, 2009Date of Patent: October 25, 2011Assignee: Applied Materials, Inc.Inventors: Chien-Teh Kao, Xinliang Lu, Zhenbin Ge, Mei Chang, Hoiman Raymond Hung, Nitin Ingle
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Patent number: 8043918Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating filType: GrantFiled: July 21, 2010Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Patent number: 8030171Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).Type: GrantFiled: July 24, 2007Date of Patent: October 4, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Masaru Seto
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Publication number: 20110220914Abstract: A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.Type: ApplicationFiled: December 7, 2010Publication date: September 15, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Ryoichi Fujii, Shigeto Honda, Atsushi Narazaki, Kaoru Motonami
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Patent number: 8017496Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced.Type: GrantFiled: October 14, 2009Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Gyun Kim, Dong-Suk Shin
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Patent number: 8012846Abstract: A method of forming an isolation structure includes the steps of: (a) forming an opening within a substrate; (b) forming a substantially conformal layer comprising tetraethoxysilane (TEOS) layer along the opening; and (c) forming a dielectric layer over the TEOS layer, the dielectric layer substantially filling the opening.Type: GrantFiled: August 4, 2006Date of Patent: September 6, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yuan Tsai, Chih-Lung Lin, Cheng-Chen Calvin Hsueh
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Patent number: 7998832Abstract: A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material.Type: GrantFiled: August 27, 2008Date of Patent: August 16, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Richard J. Carter, George J. Kluth, Michael J. Hargrove
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Publication number: 20110195559Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF3, F2, and BF2. The trench is filled with a dielectric layer.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
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Patent number: 7994019Abstract: Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.Type: GrantFiled: September 27, 2010Date of Patent: August 9, 2011Assignee: Applied Materials, Inc.Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre
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Patent number: 7994605Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: GrantFiled: April 30, 2008Date of Patent: August 9, 2011Assignee: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Patent number: 7989911Abstract: In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low voltage transistor regions, and a third trench between the first and second trenches and between and adjacent to a high voltage transistor region and a low voltage transistor region. A thicker silicon dioxide layer lines the first trench and a first portion of the third trench adjacent to a high voltage transistor region. A thinner silicon dioxide layer lines the second trench and a second portion of the third trench adjacent to a low voltage transistor region.Type: GrantFiled: October 28, 2009Date of Patent: August 2, 2011Assignee: Lattice Semiconductor CorporationInventors: Sunil Mehta, Stewart Logie, Steven Fong
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Patent number: 7989310Abstract: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then RIE etched to initially remove the oxide layer from the wafer surface with continued etching to remove the oxide layers in upper trench portions to define later sealing portions of the voids or to displace the first bottlenecks downward to define further bottlenecks. A second SiO2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.Type: GrantFiled: February 5, 2005Date of Patent: August 2, 2011Assignee: X-Fab Semiconductor Foundries AGInventor: Karlheinz Freywald
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Patent number: 7985656Abstract: A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness. A silicon nitride layer is deposited on the silicon dioxide layer in the first and second trenches. The silicon nitride layer is then etched from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench. The exposed silicon dioxide layer in the first trench is oxidized to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench. The first and second trenches are then filled with a dielectric material.Type: GrantFiled: October 28, 2009Date of Patent: July 26, 2011Assignee: Lattice Semiconductor CorporationInventors: Sunil Mehta, Stewart Logie, Steven Fong
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Patent number: 7968422Abstract: A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate.Type: GrantFiled: February 9, 2009Date of Patent: June 28, 2011Assignee: TEL Epion Inc.Inventor: John J. Hautala
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Patent number: 7968425Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.Type: GrantFiled: July 14, 2006Date of Patent: June 28, 2011Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Xiaolong Fang
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Publication number: 20110136319Abstract: Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.Type: ApplicationFiled: December 8, 2009Publication date: June 9, 2011Inventors: Yunjun Ho, Matt Meyers, Kevin L. Beaman, Gregory J. Light
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Publication number: 20110117714Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.Type: ApplicationFiled: November 19, 2009Publication date: May 19, 2011Inventors: Max Levy, Natalie Feilchenfeld, Richard Phelps, BethAnn Rainey, James Slinkman, Steven H. Voldman, Michael Zierak, Hubert Enichlmair, Martin Knaipp, Bernhard Loeffler, Rainer Minixhofer, Jong-Mun Park, Georg Roehrer
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Publication number: 20110117724Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.Type: ApplicationFiled: January 25, 2011Publication date: May 19, 2011Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsin KO, Yee-Chia YEO, Wen-Chin LEE, Chung-Hu GE
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Patent number: 7939749Abstract: Provided is a solar cell including: a first electrode and a second electrode facing each other; a porous membrane interposed between the first electrode and the second electrode and having a dye adsorbed thereto; an electrolyte interposed between the first electrode and the second electrode; and a buffering layer interposed between the first electrode and the porous membrane and having at least two layers. According to the construction of the solar cell, an electron-hole recombination is prevented by preventing the contact between an electrode having a porous membrane and an electrolyte, thereby improving the electron collection property and the photoelectric conversion efficiency of the dye-sensitized solar cell.Type: GrantFiled: May 26, 2005Date of Patent: May 10, 2011Assignee: Samsung SDI Co., Ltd.Inventors: Kwang-Soon Ahn, Ji-Won Lee, Wha-Sup Lee, Jae-Man Choi, Byong-Cheol Shin, Joung-Won Park
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Publication number: 20110101488Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.Type: ApplicationFiled: December 17, 2009Publication date: May 5, 2011Inventor: Hyung-Hwan Kim
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Patent number: 7906407Abstract: A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.Type: GrantFiled: October 29, 2007Date of Patent: March 15, 2011Assignee: Agere Systems Inc.Inventors: Nace Rossi, Ranbir Singh, Arun K. Nanda
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Publication number: 20110053327Abstract: Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.Type: ApplicationFiled: August 23, 2010Publication date: March 3, 2011Inventors: Jun-Ho YOON, Kyoung-Sub Shin, Sung-Sam Lee, Kung-Hyon Nam, Hong Cho, Joon-Seok Moon
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Patent number: 7897460Abstract: The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.Type: GrantFiled: March 19, 2008Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: Kunal R. Parekh, Suraj Mathew, Jigish D. Trivedi, John K. Zahurak, Sanh D. Tang
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Publication number: 20110037115Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.Type: ApplicationFiled: October 22, 2010Publication date: February 17, 2011Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Unsoon KIM, Angela T. HUI, Yider WU, Kuo-Tung CHANG, Hiroyuki KINOSHITA
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Patent number: 7883987Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.Type: GrantFiled: April 16, 2010Date of Patent: February 8, 2011Assignee: Infineon Technologies AGInventors: Armin Tilke, Frank Huebinger, Hermann Wendt
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Patent number: 7872333Abstract: A layer system is described including a silicon layer and a passivation layer which is applied at least regionally to the silicon layer's surface, the passivation layer having a first, at least largely inorganic partial layer and a second partial layer, the second partial layer being made of an organic compound including silicon or containing such a material. In particular, the second partial layer is structured in the form of a “self-assembled monolayer.” Furthermore, a method is described for creating a passivation layer on a silicon layer, a first, inorganic partial layer being created on the silicon layer and a second partial layer, containing an organic compound including silicon or being made thereof, being created at least in certain areas on the first partial layer. Both partial layers form the passivation layer. The described layer system or the described method is particularly suited for creating self-supporting structures in silicon.Type: GrantFiled: May 6, 2003Date of Patent: January 18, 2011Assignee: Robert Bosch GmbHInventors: Franz Laermer, Lutz Mueller, Winfried Bernhard
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Publication number: 20110006390Abstract: A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench.Type: ApplicationFiled: April 9, 2010Publication date: January 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien HUANG, Han-Pin CHUNG, Shiang-Bau WANG
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Patent number: 7858492Abstract: A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material.Type: GrantFiled: December 19, 2008Date of Patent: December 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eunkee Hong, Kyung-Mun Byun, Jong-Wan Choi, Eun-Kyung Baek, Young-Sun Kim
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Patent number: 7855125Abstract: A method for manufacturing a semiconductor device includes: forming a groove in a semiconductor substrate and embedding an element isolation film made of a silicon oxide film in the groove; forming a silicon nitride film on the element isolation film; forming an oxidized silicon nitride film on the surface of the element isolation film through thermal treatment of the element isolation film and the silicon nitride film; and removing the silicon nitride film.Type: GrantFiled: February 27, 2008Date of Patent: December 21, 2010Assignee: Seiko Epson CorporationInventor: Takaoki Sasaki
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Patent number: 7851329Abstract: A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.Type: GrantFiled: December 12, 2007Date of Patent: December 14, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Hyun-Soo Shin
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Publication number: 20100273309Abstract: The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.Type: ApplicationFiled: July 1, 2010Publication date: October 28, 2010Applicant: Micron Technology, Inc.Inventors: Fernando Gonzalez, David Chapek, Randhir P.S. Thakur
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Patent number: 7807546Abstract: A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active region and isolation region form a surface having a step therein. The semiconductor further comprises a dielectric material formed over the step. The dielectric material has a dielectric constant greater than about 8.Type: GrantFiled: July 13, 2006Date of Patent: October 5, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lee, Yee-Chia Yeo
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Publication number: 20100240194Abstract: A method of fabricating a semiconductor device, the method including sequentially forming a pad oxide layer and a nitride layer on a substrate; etching the nitride layer, the pad oxide layer, and the substrate to form a trench; forming a sidewall oxide layer on a sidewall and a bottom of the trench; forming a oxide layer liner including nitrogen on the sidewall oxide layer; and forming a gap fill layer on the oxide layer linerType: ApplicationFiled: March 23, 2010Publication date: September 23, 2010Inventors: DeokYoung Jung, Ju-Seon Goo, Kyung-Mun Byun, Eunkee Hong, Jun-Won Lee
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Patent number: 7795110Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.Type: GrantFiled: February 21, 2008Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-seog Youn, Jong-hyon Ahn, Deok-hyung Lee, Sung-gun Kang, Kong-soo Cheong
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Publication number: 20100200946Abstract: A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate.Type: ApplicationFiled: February 9, 2009Publication date: August 12, 2010Applicant: Tel Epion Inc.Inventor: John J. Hautala
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Patent number: 7772069Abstract: A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.Type: GrantFiled: March 7, 2008Date of Patent: August 10, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Park, Sung-Hyun Kwon, Jae-Hwang Sim, Keon-Soo Kim, Jae-Kwan Park
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Publication number: 20100193898Abstract: A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by depositing a dielectric layer in at least one region on the substrate.Type: ApplicationFiled: April 23, 2009Publication date: August 5, 2010Applicant: Tel Epion Inc.Inventors: John J. Hautala, Edmund Burke, Martin D. Tabat, Luis Fernandez
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Patent number: 7749860Abstract: The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch.Type: GrantFiled: September 8, 1999Date of Patent: July 6, 2010Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, David Chapek, Ranshir P. S. Thakur
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Publication number: 20100167496Abstract: A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.Type: ApplicationFiled: May 28, 2009Publication date: July 1, 2010Inventors: Jae-Hyoung Koo, Jin-Woong Kim, Mi-Ri Lee, Chi-Ho Kim, Jin-Ho Bin
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Patent number: 7745305Abstract: A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.Type: GrantFiled: January 14, 2008Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Heon Lee, Kyu-Tae Na, Ju-Wan Kim, Taek-Jung Kim
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Patent number: 7745304Abstract: A method of manufacturing a semiconductor device begins when a first dielectric pattern is formed on and/or over a substrate, and a first etching process is performed to form a trench in the substrate. An edge portion of the first trench is exposed. An oxidation process is performed on and/or over the substrate rounding the edge portion of the trench. A second dielectric is formed on and/or over the substrate including the trench, and a planarization process is performed on the second dielectric. A photoresist pattern is formed on and/or over the second dielectric corresponding to the trench, and a second etching process is performed to form a second dielectric pattern filling the trench. The photoresist pattern is removed. A second cleaning process is performed on the substrate including the trench to form a device isolation layer, which is formed by removing a portion of the second dielectric pattern.Type: GrantFiled: June 17, 2008Date of Patent: June 29, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Hyun-Ju Lim
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Patent number: 7727856Abstract: A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer having stress layer sidewalls over the trench sidewalls. Ions are implanted into one or more portions of the stress layer to form ion-implanted relaxed portions with the portions of the stress layer that are not implanted are un-implanted portions, whereby the inherent stress of the one or more ion-implanted relaxed portions of stress layer portions is relaxed.Type: GrantFiled: December 24, 2006Date of Patent: June 1, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lee Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Elgin Quek, Dong Kyun Sohn
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Publication number: 20100129982Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to apparatus and methods for forming shallow trench isolations having recesses with rounded bottoms. One embodiment of the present invention comprises forming a recess in a filled trench structure by removing a portion of a material from the filled trench structure and rounding bottom corners of the recess. Rounding bottom corners is performed by depositing a conformal layer of the same material filled in the trench structure over the substrate and removing the conformal layer of the material from sidewalls of the recess.Type: ApplicationFiled: November 18, 2009Publication date: May 27, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Chien-Teh Kao, Xinliang Lu, Zhenbin Ge, Mei Chang, Hoiman Raymond Hung, Nitin Ingle
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Patent number: 7723818Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.Type: GrantFiled: May 22, 2007Date of Patent: May 25, 2010Assignee: Infineon Technologies AGInventors: Armin Tilke, Frank Huebinger, Hermann Wendt
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Patent number: 7713887Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.Type: GrantFiled: June 12, 2007Date of Patent: May 11, 2010Assignee: Hynix Semiconductor Inc.Inventor: Byung Soo Eun
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Publication number: 20100102377Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a plurality of charge storage layers formed on the first insulating layer, a plurality of element isolation insulating films formed between the charge storage layers respectively, a second insulating layer formed on the charge storage layers and the element isolation insulating films, the second insulating layer including a stacked structure of a first silicon nitride film, a first silicon oxide film, an intermediate insulating film having a relative dielectric constant of not less than 7 and a second silicon oxide film, and a control electrode formed on the second insulating layer. The first silicon nitride film has a nitrogen concentration of not less than 21×1015 atoms/cm2.Type: ApplicationFiled: May 18, 2009Publication date: April 29, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Hirofumi IIKAWA, Masayuki Tanaka
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Patent number: 7678664Abstract: According to a fabrication method for an element isolation structure section, that is, STI, of the present invention, by differing the etching rate of material to be embedded in a narrow-width, that is, a small area trench section (first trench section) formed in a small isolation area, from the etching rate of a material to be embedded in a wide-width (plane shape of larger area) trench section (second trench section) formed in a large isolation area, in the etching step, dishing (recessing) that inevitably occurs in a CMP step can be reduced. Therefore, a STI having a higher level of flatness can be formed. As a result, by simple steps, deterioration of the electrical characteristics of elements that are element-isolated by STI can be reduced. That is to say, not only STI having excellent electrical characteristics, but also a semiconductor device provided with such STI, can be provided at a good level of production yield.Type: GrantFiled: April 20, 2007Date of Patent: March 16, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Noriyuki Tokuichi