Abstract: A layer structure comprising substrate, a metal layer, a first amorphous silicon layer, an insulating layer, and a second amorphous silicon layer, and a method of crystallizing the second amorphous silicon layer by irradiating single pulse laser to the layer structure are provided. The method provides an effect of forming large grain of amorphous silicon as good as using dual pulse laser or higher just by using single pulse laser without additional optical system. A semiconductor device employing the layer structure maximizes an electron mobility.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

Abstract: A method for forming a transistor of a semiconductor device, includes forming a trench by etching a semiconductor substrate on which a pad oxide film and a pad nitride film are sequentially formed; forming a isolation oxide film by filling the trench with oxide; removing an upper portion of the isolation oxide film until an upper lateral portion of the semiconductor substrate is exposed; forming a barrier nitride film over the isolation oxide film, the semiconductor substrate, and the pad nitride film; forming a sacrificial oxide film over the barrier nitride film; performing a planarization process until the pad nitride film is exposed; performing a wet etching process until the active region is exposed; forming a photoresist pattern over the active region and the barrier nitride film; and performing a dry etching process by using the photoresist pattern as an etching mask, thereby forming a recessed gate trench.

Abstract: A method for forming an isolation layer for a semiconductor device is provided. The preferred method is capable of securing a gap fill margin during formation of an isolation layer. A device isolation layer formed according to a preferred method includes a trench formed in a device separation area of a semiconductor substrate; a thermal oxidation layer formed in a part of the trench; an oxidation silicon layer formed on the thermal oxidation layer; and an oxidation isolation layer formed on the oxidation silicon layer and filling the trench.

Abstract: A method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 200° C. to about 800° C. in a first atmosphere comprising an oxygen containing gas, and annealing the substrate at a second temperature of about 800° C. to about 1400° C. in a second atmosphere lacking oxygen. In addition, a method of annealing a substrate comprising a trench containing a dielectric material, the method including annealing the substrate at a first temperature of about 400° C. to about 800° C. in the presence of an oxygen containing gas, purging the oxygen containing gas away from the substrate, and raising the substrate to a second temperature from about 900° C. to about 1100° C. to further anneal the substrate in an atmosphere that lacks oxygen.

Abstract: A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.

Abstract: In a method of fabricating a trench isolation structure of a semiconductor device, excellent gap filling properties are attained, without the generation of defects. In one aspect, the method comprises: loading a substrate with a trench formed therein into a high-density plasma (HDP) chemical vapor deposition apparatus; primarily heating the substrate; applying a first bias power to the apparatus so as to form an HDP oxide liner on side wall and bottom surfaces of the trench, a gap remaining in the trench following formation of the HDP oxide liner; removing the application of the first bias power and secondarily heating the substrate; applying a second bias power at a power level that is greater than that of the first bias power to the substrate so as to form an HDP oxide film to fill the gap in the trench; and unloading the substrate from the apparatus.

Abstract: An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract: Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided.

Abstract: A method of forming a mask stack pattern and a method of manufacturing a flash memory device including an active area having rounded corners are provided. The method of manufacture including forming a mask stack pattern defining an active region, the mask stack pattern having a pad oxide layer formed on a semiconductor substrate, a silicon nitride layer formed on the pad oxide layer and a stack oxide layer formed on the silicon nitride layer, oxidizing a surface of the semiconductor substrate exposed by the mask stack pattern and lateral surfaces of the silicon nitride layer such that corners of the active region are rounded, etching the semiconductor substrate having an oxidized surface to form a trench in the semiconductor substrate, forming a device isolation oxide layer in the trench, removing the silicon nitride layer from the semiconductor substrate, and forming a gate electrode in a portion where the silicon nitride layer is removed.

Abstract: A capacitor is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor generally comprises a top conductive plate, a capacitor dielectric and a bottom conductive plate that respectively comprise a patterned layer of tantalum nitride TaN, a layer of a nitride based material and a layer of patterned polysilicon.

Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

Abstract: A method of fabricating a non-volatile memory device, A tunnel insulating layer, a floating gate, and a pad nitride layer is formed on a semiconductor substrate. A isolation region of the semiconductor substrate is formed by etching to a predetermined depth, and a liner insulating layer is formed on an entire surface of the resulting trench for device isolation. A filling insulation layer is formed on the liner insulating layer to fill the trench and a first etching process is performed on the filling insulation layer and the liner insulating layer. The surface of semiconductor is recessed by performing a second etching process on the filling insulation layer. A capping layer is formed on an entire surface of the result formed by the second etching process. The device isolation layer of a concave shape is formed by performing an etching process on the capping layer.

Abstract: A method for control of chemical mechanical polishing of a pattern dependant non-uniform wafer surfaces in a die scale wherein the die in the wafer surface have a plurality of zones of different heights and different pattern densities is provided. The method provides for varying pressure applied to the die both spatially and temporally to reduce both local and global step height variations. In one embodiment, pressure is varied both spatially and temporally using a look ahead algorithm. The algorithm looks ahead and recalculates/modifies the pressure values by identifying the step heights that could be formed after a specified time step. The final surface predictions have improved uniformity on the upper surface as well as on the step heights across the entire die.

Abstract: A semiconductor device can include a semiconductor substrate, a first trench formed in the semiconductor substrate, a second trench formed in the semiconductor substrate, a first device isolation layer formed in the first trench, a second device isolation layer formed in the second trench having a different structure than the first device isolation layer.

Abstract: A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer at an upper portion of the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI; d) performing a densifying annealing process to densify the APCVD oxide layer; and depositing an HDP-CVD oxide layer at an upper portion of the APCVD oxide layer so that the STI shallow trench is completely gap-filled.

Abstract: In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

Abstract: A semiconductor device includes a first structure having a recess having a bottom and opposing side surfaces, and a second structure conformally disposed on the bottom and side surfaces of the recess. The second structure includes a multilayer having two layers having a thickness substantially smaller than a width of the recess. Methods of manufacturing a semiconductor device include providing a first structure having a recess in a deposition chamber and flowing first and second reactants over the first structure for a first period at first and second flow rates. Then, the flow rates of the first second reactants to the first structure are substantially reduced for a pause period. The first and second reactants are then flowed over the first structure for a second period at third and fourth flow rates. The deposition and pause steps may be repeated until a multilayer having a desired thickness is formed.

Abstract: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench.

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

Abstract: A method of manufacturing a semiconductor device, includes preparing a work piece having a trench on its main surface side, forming a polymer film containing a polymer containing silicon, hydrogen and nitrogen on the main surface of the work piece, holding the work piece with the polymer film in a first atmosphere, which contains oxygen, and whose oxygen partial pressure is set in a range of 16 to 48 Torr, oxidizing the polymer film in a second atmosphere containing water vapor to form an oxide film containing a silicon oxide as a main component, after holding the work piece in the first atmosphere, and removing an upper portion of the oxide film to remain a lower portion of the oxide film in the trench.

Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

Abstract: A method of forming an isolation layer structure for a semiconductor device includes forming a first structure on a substrate, the first structure including an insulation layer pattern having a sacrificial pattern therein, the sacrificial pattern having an etching rate that is different from the insulation layer pattern, partially removing the insulation layer pattern until the sacrificial pattern is exposed to form a second structure, partially removing the sacrificial pattern from the insulation layer pattern to form a third structure having a recessed portion at a central portion thereof, and removing an upper portion of the third structure such that a top surface of the third structure is concave with respect to a top surface of the substrate.

Abstract: A method of fabricating a 3D field effect transistor employing a hard mask spacer includes forming a hard mask pattern on a semiconductor substrate. The semiconductor substrate is etched using the hard mask pattern as an etch mask to form a trench that defines an active region. A trench oxide layer and a liner are sequentially formed on the semiconductor substrate, and an isolation layer is formed to fill the trench. An upper surface of the isolation layer may by recessed below an upper surface of the hard mask pattern. A hard mask spacer is formed that covers sidewalls of the hard mask pattern. Some portions of the isolation layer where an etching is blocked by the hard mask spacer remain on sidewalls of the channel region, respectively, thereby preventing the liner from being damaged by etching.

Abstract: A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.

Abstract: A method of fabricating an integrated device on a substrate with an exposed surface region is disclosed. One embodiment provides introducing a first component into the exposed surface region of the substrate. A material is provided on the exposed surface region. The material on the exposed surface region is cured and the first component release from the exposed surface region of the substrate.

Abstract: A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and a second process after the first process. The method includes forming a silicon nitride layer in the recess along the profile of the same during the second process.

Abstract: A wafer including a high stressed thin film thereon is lifted, and a pre-heating process is performed while the wafer is lifted. Subsequently, a dielectric layer is deposited on the high stressed thin film.

Abstract: A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewall oxide film is formed overlying the first trenches. A first liner nitride film is formed overlying the first sidewall oxide film. Second trenches have a predetermined depth and are formed in the semiconductor substrate at the peripheral circuit regions. A second sidewall oxide film is formed overlying the second trenches. An oxide film fills the first overlying second trenches. A second liner nitride film formed on the filling oxide film. The second liner nitride film is separated from the sidewalls of the first and second trenches.

Abstract: Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.

Abstract: A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning the nitride film using an etch process employing a cell array mask; coating a photoresist on the entire structure including the patterned nitride film; patterning the photoresist using a peri ISO mask; sequentially etching the nitride film, the pad oxide film, and the semiconductor substrate using the patterned photoresist as an etch mask, thereby forming first trenches; stripping the photoresist; etching the semiconductor substrate of the cell region and the peri region using the patterned nitride film as an etch mask, thereby forming second trenches in the cell region and third trenches, which are consecutive to the first trenches, in the peri region; and, forming an isolation film within the second and third trenches.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.

Abstract: The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer.

Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Abstract: A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region.

Abstract: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.

Abstract: A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

Abstract: A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.

Abstract: A method for forming a thermal oxide layer on the surface of a semiconductor substrate exposed during a semiconductor fabricating process. The thermal oxide layer is to be thin to minimize silicon substrate defects caused by volume expansion. A chemical vapor deposition (CVD) layer is then formed on the thin thermal oxide layer, creating a required thickness. The thin thermal oxide layer and the CVD material layer are formed in the same CVD apparatus. As a result, a process can be simplified and a particle-leading pollution can be prevented.

Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

Abstract: A method of manufacturing a semiconductor device, includes forming a gate insulating film on a semiconductor substrate; forming a polycrystalline silicon film on the gate insulating film; forming a silicon nitride film on the polycrystalline silicon film; anisotropically etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film and the semiconductor substrate so as to form a trench; forming a first silicon oxide film on a surface of the trench by thermal CVD process; forming a second silicon oxide film on the first silicon oxide film, the second silicon oxide film including a silicon oxide film (SiOx: x?2) or a silicon oxide film containing 1×1013/cm3 or more metal atoms or carbon atoms; and executing plasma treatment on the second silicon oxide film in an oxidating atmosphere.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Abstract: By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride may be efficiently modified on the basis of an appropriate surface treatment, thereby providing a high degree of material integrity during a subsequent etch process for removing non-modified portions of silicon nitride, which may also be used as an efficient CMP stop layer.

Abstract: Methods of forming material in a gap in a substrate include forming a pattern to define a gap on a substrate. A bottom oxide layer is formed on a surface of the substrate and substantially filling the gap. The bottom oxide layer is etched back inside an opening in the gap to expose side walls of the gap so that a residual bottom oxide layer remains at a bottom of the gap. A top oxide layer is selectively deposited on the residual bottom oxide layer, wherein the top oxide layer is deposited in a first direction toward the opening at a faster rate than in a second direction away from the side walls.

Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.

Abstract: A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.

Abstract: A trench isolation method for a semiconductor device, wherein a capping layer formed of an insulating material fills a recess generated at a border edge between an active area and an inactive area. The border edge is defined by a trench filled with insulating material. Filling the recess suppresses defects of the semiconductor device. Reduction of the isolating ability, due to the formation of gate poly residue during the forming of a gate, is prevented. Reduction of the threshold voltage of a transistor, caused by electric field concentration due to the gate poly residue, is suppressed. An oxide layer is also provided which protects an nitride pad during a plasma process.