Abstract: A process for making a semiconductor structure, includes forming a second dielectric layer on exposed regions of an intermediate structure. The intermediate structure includes: a semiconductor substrate having the regions, a first dielectric layer on at least a first portion of the semiconductor substrate, an etch-stop layer on at least a second portion of the first dielectric layer, and spacers on at least a third portion of said semiconductor substrate. The spacers are adjacent edges of the etch-stop layer and adjacent the exposed regions.

Abstract: A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.

Abstract: A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.

Abstract: A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

Abstract: A method of manufacturing a semiconductor device, in which the depth of a divot in a shallow trench isolation can be decreased. The method comprises forming a trench in a semiconductor substrate, for isolating elements, forming a nitride film on a surface of the trench, depositing mask material on an entire surface of the semiconductor substrate, filling the trench with the mask material, etching the mask material until a surface level of the mask material in the trench falls below the surface of the semiconductor substrate, removing an exposed upper portion of the nitride film on the surface of the trench, removing the mask material from the trench, filling the trench with element-isolating material, thereby forming an element-isolating region, and forming a transistor in an element region isolated from another element region by the element-isolating region.

Abstract: A pad layer and a silicon nitride layer are respectively formed on a substrate. The multi-layer is then patterned to define active areas. Next, the substrate is etched to form a recessed portion. A sidewal barrier is formed on the sidewall of the recessed portion. A thermal oxidation process is performed using the silicon nitride layer and the sidewal barrier as a mask to form FOX for suppressing oxygen penetration into the substrate during the oxidation process. Therefore, the conventional bird's beak effect is reduced by the method of the present invention.

Abstract: A semiconductor wafer includes a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. The present invention forms a doped area in the silicon substrate and within the active area and then deposits a dielectric layer on the surface of the semiconductor wafer. A dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area by the dry etching process, and to reduce the leakage current of the doped area. Additionally, the present invention also uses a wet etching process to remove the dielectric layer, which prevents an anisotropic physical impact on the silicon substrate near the field oxide layer to reduce the leakage current of the doped area.

Abstract: A number of npn and pnp bipolar transistors are formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others The higher frequency transistors have their emitters located closer to the collectors, by positioning a collector, or emitter, of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidising the silicon surface, and subsequently removing the oxide to leave the recess.

Abstract: The present invention provides a method of forming a lateral diffused metal-oxide semiconductor (LD MOS) transistor on a semiconductor wafer. An ion implantation process is performed on a predetermined area of the silicon substrate so as to form a p-well adjacent to an n-well. An insulation layer is then formed on a predetermined area of the n-well. A gate layer is formed on a portion of the p-well and the n-well, and one side of the gate layer is positioned on the surface of the insulation layer. Finally, an ion implantation process is performed to form two n-type doped regions on the p-well and the n-well. The two doped regions are used as the source and the drain of the LD MOS transistor.

Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.

Abstract: The present invention relates to a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load. The method includes filling the recess with a material that imparts a compressive load upon the film under conditions that oppose the tensile load. The present invention is particularly well suited for shallow isolation trench filling in the 0.13 micron geometry range, and smaller.

Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.

Abstract: The present invention discloses a method to form CMOS transistors for high speed and lower power applications. A high energy and low dose phosphorous is implanted in a silicon substrate to fabricate an N-well after a pad oxide layer and a silicon nitride layer is formed. After a thick field oxide is formed by using a high temperature steam oxidation process, another high energy and low dose multiple boron implantation is then performed to fabricate a buried heavily boron doped region. A rapid thermal processing (RTP) system is following used to activate the boron dopant to form buried p+ layer and to recover the implanted damages. All the field oxide films are then removed by using a diluted HF or BOE solution. After porous silicon is obtained via anodic electrochemical dissolution in the HF solution, the porous silicon is then thermally oxidized to form the separate n-type silicon islands. Next, a thick CVD oxide film is deposited and then etched back to planarize device surface.

Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

Abstract: A semiconductor device and a method for fabricating the same is disclosed, which minimizes device degradation, minimizes noises, and simplifies the fabrication process. The device includes a substrate having a first semiconductor layer, a buried insulating film, and a second semiconductor layer stacked; a field oxide film for separating the second semiconductor layer into a first region and a second region; a recess region formed in a particular region of the second region; gate insulating films and gate electrodes formed in stacks on each of a particular region in the first region and the recess region in the second region; first impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the first region; and second impurity regions formed in surfaces of the second semiconductor layer on both sides of the gate electrode in the recess region in the second region so that the second semiconductor layer below the gate electrode is fully depleted.

Abstract: A resist pattern (51) is formed only on buried silicon oxide films (2) on the whole surface of an alignment mark area (11A) and a trench (10C). With the resist pattern (51), preetching is performed by dry etching, to remove the silicon oxide film (2) on the whole of a memory cell area (11B) and part of a peripheral circuit area (11C) by a predetermined thickness. After removing the resist pattern (51), a silicon oxide film (3) and a silicon nitride film (4) are removed by CMP polishing, to provide a height difference between the highest portion and the lowest portion of the silicon oxide film (2A) which serves as an alignment mark. Thus, a semiconductor device with trench isolation structure which achieves a highly accurate alignment without deterioration of device performance and a method for manufacturing the semiconductor device can be provided.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.

Abstract: An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap.

Abstract: With the present invention, a filled isolation trench is fabricated as part of an integrated circuit on a semiconductor wafer using nitrogen implantation into at least one side wall of the isolation trench. An isolation trench is etched within a layer of semiconductor material. The isolation trench has at least one side wall comprised of the semiconductor material, and the isolation trench has a bottom wall. Nitrogen ions are implanted into the at least one side wall of the isolation trench. A layer of an insulator material is thermally grown from the at least one side wall and the bottom wall of the isolation trench. The isolation trench is then filled with the insulator material using a deposition process to form the filled isolation trench. With the present invention, the nitrogen ions implanted into the at least one side wall of the isolation trench reduce a radius of a bird's beak formed on the at least one side wall of the isolation trench.

Abstract: A method for fabricating a high voltage MOS device. A substrate has a first P-type well region and a N-type well region formed thereon. A field oxide is then formed on the N-well region and patterned until field oxide projections project from the field oxide layer. With the field oxide projections serving as masks, second P-type well regions are formed in both P-type and N-type lightly doped well regions. A gate oxide layer and a gate polysilicon layer are formed in sequence on a part of the substrate and the field oxide projection, wherein the gate oxide layer and the gate polysilicon layer form a gate electrode. With the gate electrode and the field oxide layer serving masks, a source/drain region is consequently formed in the first P-type well region and the N-type well region.

Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.

Abstract: A method for forming enhanced field oxide (FOX) region of low voltage devices in a high voltage process is disclosed. The method includes providing a semiconductor structure comprising a substrate, two field oxide regions on the substrate, a well between the two field oxide regions in the substrate and a silicon nitride layer between the two field oxide regions above the well. As a key step, nitrogen is implanted into the semiconductor structure, and the silicon nitride layer is then removed. Then, a gate oxide layer on the well and silicon oxynitride layer on the field oxide regions are all formed in-situ.

Abstract: A method of manufacturing a semiconductor device comprises the steps of: (a) forming a first oxide film and a first silicon nitride film on a surface semiconductor layer of an SOI substrate, the SOI substrate comprising the surface semiconductor layer formed on a support substrate with the intervention of a buried insulating film; (b) patterning the first silicon nitride film into a desired shape and performing a first LOCOS oxidization using the thus patterned first silicon nitride film as a mask to form a first LOCOS oxide film in a region for device isolation in the surface semiconductor layer; (c) selectively removing the first LOCOS oxide film, (d) forming sidewall spacers of a second silicon nitride film on sidewalls of the first silicon nitride film and the first oxide film; (e) performing a second LOCOS oxidization using the first silicon nitride film and the sidewall spacers as a mask to form a second LOCOS oxide film which is thinner than the first LOCOS oxide film; and (f) removing the first and se

Abstract: A method of fabricating a semiconductor device which includes providing a silicon substrate having a patterned mask thereover to expose a portion of the surface of the substrate. The exposed surface portion is oxidized to form a sacrificial silicon oxide region to a predetermined depth in the substrate at the exposed portions of the substrate. The sacrificial silicon oxide is then removed by a HF etch and a second region of silicon oxide is formed in the substrate in the region from which the sacrificial silicon oxide was removed. The step of removing the silicon oxide also includes removing a portion of the pad oxide. The sacrificial silicon oxide has a thickness less than the second region of silicon oxide which is from about 10 percent to about 30 percent of the thickness of the second region of silicon oxide. The oxidation steps are thermal oxidation steps in an oxygen-containing ambient.

Abstract: A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate. The implant mask regions are removed, leaving bulk silicon regions between the buried oxide regions.

Abstract: STI is sometimes effected by etching back shallow trenches that have been over-filled with oxide in order to make the upper surfaces co-planar with the semiconductor. This results in the formation of a groove at the oxide-semiconductor interface which exposes the source/drain PN junction, making it vulnerable to shorting during subsequent SALICIDE processes. In the present invention, manufacture of the LDD device proceeds in the normal way except that when silicon nitride spacers are grown on the vertical sides of the gate pedestal, the depositing silicon nitride is also allowed to coat the exposed vertical walls of the trenches (i.e. inside the groove). Following standard practice, a layer of pad oxide is interposed between the trench wall and this additional silicon nitride for purposes of stress relief.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.

Abstract: Disclosed is a method for making a semiconductor device where a device region and a device isolation region for electrically isolating between devices are formed on a semiconductor substrate, said device region including a transistor, which has the steps of: forming device isolation film by using polysilicon film or amorphous silicon film as a buffer; and oxidizing the polysilicon film or amorphous film into silicon oxide film and then removing the silicon oxide film after forming the device isolation film.

Abstract: A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.

Abstract: A method for forming a photodiode is provided. A substrate having a well with a first electric type therein is provided. An insulating layer is formed on the substrate. The insulating layer is patterned to form an opening. The insulating layer still remains with a thin thickness below the bottom of the opening. A heavily doped region with a second electric type is formed in the well in the position below the opening. A junction is thus formed between the heavily doped region and the well.

Abstract: A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating layer is etched proximate the line along at least a portion of at least one sidewall of the line. An insulating spacer forming layer is then deposited over the substrate and the line. It is anisotropically etched to form an insulating sidewall spacer. A method of forming a local interconnect comprises forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates.

Abstract: A LOCOS method uses a reagent mixed of etchant and oxidizer to simultaneously perform the step of forming the FOX layer and the step of removing a mask layer of the conventional LOCOS method. The applied temperature is about 950-1150° C. The etchant. such as a HF acid solution, is used to remove the mask layer, and the oxidizer, such as O2, is used to form the FOX layer on a silicon substrate.

Abstract: A method for producing a low-impedance contact between a metallizing layer and a semiconductor material and a method for producing a capacitor. The two methods are adapted to one another such that in the course of a single process, both contacts and capacitors can be formed. In particular, by the methods of the invention, the insulation layer, which forms when the first dopant for the contact is forced inward, can be used as a capacitance dielectric of a capacitor.

Abstract: The present invention provides a fabricating method of a high-voltage device. The invention provides N.sup.-- -type doped regions with properly low doping concentration in order to increase breakdown voltage. Field oxide layers are used as masks in a self-aligned ion implantation step to form N.sup.- -type doped drift regions with a higher doping concentration than the N.sup.-- -type doped regions. A recessed gate is formed so that the channel length is increased and the curvature of the electrical distribution lines on the edge of a drain region nearby a channel is decreased while the device is operated under high voltage.

Abstract: A method of forming field oxide during the manufacture of a semiconductor device comprises the steps of providing a semiconductor wafer having a plurality of recesses or trenches therein. A layer of texturized polycrystalline silicon is formed within the recesses, which is subsequently oxidized to form field oxide. The instant method reduces stress imparted to the die as the texturized polycrystalline silicon has voids or holes which absorb the expanding volume as the silicon is oxidized to form field oxide.

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Abstract: A method for forming ETOX cells (Intel Type Flash EPROM Cell) using a self-aligned source etching process comprising the steps of depositing a silicon nitride layer up to a thickness of 100 .ANG. to 700 .ANG., and then etching back the layer to form spacers. Thereafter, common source regions are defined using a photomask, and then the field oxide layer is etched using either a wet etching method or a dry etching method having a high selectivity ratio. The spacers are capable of protecting the oxide/nitride/oxide ONO layer against any damages during processing, thereby avoiding charge retention and reliability problems.

Abstract: In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

Abstract: A method to fabricate nonvolatile memories with a trench-pillar cell structure is disclosed. A pad oxide is formed on a substrate. A pad nitride is then formed on the pad oxide. An ion implantation is performed to form a lightly doping drain (LDD) in the substrate. The pad nitride, the pad oxide and the substrate are etched to form a trench. A nitride layer is then formed on the pad nitride to fill into the trench. The nitride layer is etched back to form spacers on the sidewalls of the trench. The substrate is etched back to form a subtrench in the trench. Afterward, a polysilicon layer is deposited to refill the trench region and covers a surface of the nitride. The polysilicon is etched back to remove the polysilicon layer on a surface of the nitride. The pad nitride, the nitride and the pad oxide are removed. A tunnel oxide is formed on the pillar, the trench region and the substrate. A floating gate is then formed. The floating is in the trench region and is extended to the top of the trench.

Abstract: Undesirable birds beak pull back due to ion implant damage is alleviated by additional oxide growth.

Abstract: A method for forming planarized isolation by combining LOCOS and STI isolation processes is described. A first nitride layer is deposited over a pad oxide layer on the surface of a semiconductor substrate. The first nitride layer and pad oxide layer are etched through where they are not covered by a mask to provide openings where the surface of the semiconductor substrate is exposed wherein there is at least one wide opening and one narrow opening. A second nitride layer is deposited over the substrate and etched back to leave spacers on the sidewalls of the openings wherein the narrow opening is filled by the spacers. The exposed semiconductor substrate within the wide opening is oxidized wherein a field oxide region is formed within the wide opening. A portion of the first nitride layer and spacers is etched away whereby the semiconductor substrate within the narrow opening is exposed. A trench is etched into the semiconductor substrate where it is exposed within the narrow opening.

Abstract: In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.

Abstract: A method for fabricating a high-voltage device substrate comprising the steps of forming a pad oxide layer and a mask layer over a substrate. Then, the pad oxide layer and the mask layer are patterned to define a region for a first ion implantation. Next, the exposed substrate is oxidized to form a field oxide layer. Thereafter, the mask layer is removed followed by a first ion implantation. Next, a portion of the field oxide layer is removed, and then a second ion implantation is performed implanting ions into the exposed substrate. Then, a conformal oxide layer is formed over the substrate surface. Next, a high temperature drive-in and oxidation operation is carried out, in which ions in the first ion implanted region and the second ion implanted region are driven deeper into the substrate interior, and at the same time the substrate above those regions are oxidized. Finally, the oxide layer on the substrate surface is removed, and then an epitaxial layer is formed over the substrate.

Abstract: A method is provided for forming a shallow trench isolation that has rounded and protected corners by first forming a bird's beak field oxide layer prior to the trench-forming step such that a rounded and protected top corner and a rounded bottom corner of the trench can be formed. The rounded top and bottom corners of the shallow trench opening have a radius of at least 100 .ANG. and a trench depth of not more than 5000 .ANG.. The top corner of the trench opening is protected by the beak portion of the bird's beak against etching in a subsequent oxide dip process before gate formation.

Abstract: A method for forming an element isolating film of a semiconductor device, which is capable of achieving a reduction in topology and a reduction in the occurrence of a bird's beak phenomenon, so that subsequent processes can be easily carried out to fabricate highly integrated semiconductor devices.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked by the oxidation mask. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. In accordance with a first implementation, a portion of the semiconductive substrate is removed after removal of the oxidation mask but before the formation and removal of a sacrificial oxide layer. In accordance with this implementation, removal of the semiconductive substrate material forms an undercut region under the bird's beak region which is subsequently filled in with material when the sacrificial oxide layer is formed. In accordance with a second implementation, a portion of the semiconductive substrate is removed after formation and removal of the sacrificial oxide layer.

Abstract: A semiconductor processing method of forming field oxide regions includes, a) providing a sacrificial pad oxide layer over a semiconductor substrate; b) providing a Ge.sub.x Si.sub.y layer over the pad oxide layer, where x is greater than 0.2, y is from 0 to 0.8, and x+y=1.0; c) providing a patterned nitride oxidation masking layer over the Ge.sub.x Si.sub.y layer to define at least one pair of adjacent nitride masking blocks overlying desired active area regions of the substrate; d) etching exposed portions of the Ge.sub.x Si.sub.y layer and thereby defining exposed sidewall edges of the Ge.sub.x Si.sub.y layer; e) providing an oxidation restriction layer over the respective Ge.sub.x Si.sub.y sidewalls, the oxidation restriction layer restricting rate of oxidation of the Ge.sub.x Si.sub.y layer from what would otherwise occur if the oxidation restriction layer were not present; f) oxidizing portions of the substrate unmasked by the masking layer to form at least one pair of adjacent SiO.sub.

Abstract: A method for use in the fabrication of semiconductor devices in accordance with the present invention includes providing a silicon nitride region and oxidizing a region of material in proximity to the silicon nitride region. The silicon nitride region is then hydrogenated and thereafter, the hydrogenated silicon nitride region is removed. The hydrogenation step may include immersing the silicon nitride region into pressurized boiling water and/or treating the silicon nitride region with pressurized water vapor and the removing step includes removing the hydrogenated silicon nitride region with hot phosphoric acid. The method may be used in a local oxidation of silicon process. Further, the oxidation of the material and the hydrogenation of the silicon nitride may be performed in the same pressurizable unit.

Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.