Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits lights when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Abstract: A method of depositing a high quality low defect single crystalline Group III-Nitride film. A patterned substrate having a plurality of features with inclined sidewalls separated by spaces is provided. A Group III-Nitride film is deposited by a hydride vapor phase epitaxy (HVPE) process over the patterned substrate. The HVPE deposition process forms a Group III-Nitride film having a first crystal orientation in the spaces between features and a second different crystal orientation on the inclined sidewalls. The first crystal orientation in the spaces subsequently overgrows the second crystal orientation on the sidewalls and in the process turns over and terminates treading dislocations formed in the first crystal orientation.

Abstract: Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.

Abstract: Manufacturing a laser diode includes growing an active layer, a first InP layer, and a diffraction grating layer; forming an alignment mark having a recess by etching the diffraction grating layer and the first InP layer; forming a first etching mask; forming a diffraction grating in the diffraction grating layer using the first etching mask; forming a modified layer containing InAsP on a surface of the alignment mark recess by supplying a first source gas containing As and a second source gas containing P; growing a second InP layer on the diffraction grating layer and on the alignment mark; forming a second etching mask on the second InP layer; selectively etching the second InP layer embedded in the recess of the alignment mark through the second etching mask by using the modified layer serving as an etching stopper; and forming a waveguide structure using the alignment mark.

Abstract: The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (103) is formed on a substrate (101), the method including: a substrate processing step of forming, on the (0001) C-plane of the substrate (101), a plurality of convex parts (12) of surfaces (12c) not parallel to the C-plane, to thereby form, on the substrate, an upper surface (10) that is composed of the convex parts (12) and a flat surface (11) of the C-plane; and an epitaxial step of epitaxially growing the group III nitride semiconductor layer (103) on the upper surface (10), to thereby embed the convex parts (12) in the group III nitride semiconductor layer (103).

Abstract: An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.

Abstract: The present invention provides a method of super flat chemical mechanical polishing (SF-CMP) technology, which is a method characterized in replacing laser lift-off in a semiconductor fabricating process. SF-CMP has a main step of planting a plurality of polishing stop points before polishing the surface, which is characterized by hardness of the polishing stop points material being larger than hardness of the surface material. Therefore, the present method can achieve super flat polishing surface without removing polishing stop points.

Abstract: A photodiode includes a first doped layer and a second doped layer that share a common face. A deep isolation trench has a face contiguous with the first and second doped layers. A conducting layer is in contact with a free face of the second doped layer. A protective layer is provided at an interface with the first doped layer and second doped layer. This protective layer is capable of generating a layer of negative charge at the interface. The protective layer may further be positioned within the second doped layer to form an intermediate protective structure.

Abstract: A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.

Abstract: A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer.

Abstract: A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films are grown on a substrate having an off-angle between a direction normal to the surface of ridges and the crystal direction <0001>. This helps either reduce or intentionally promote diffusion or movement of the atoms or molecules of a source material of the nitride semiconductor thin films through migration thereof. As a result, a nitride semiconductor growth layer with good surface flatness can be formed, and thus a nitride semiconductor device with satisfactory characteristics can be obtained.

Abstract: A light emitting system is disclosed. The system comprises an active region having a stack of bilayer quantum well structures separated from each other by barrier layers. Each bilayer quantum well structure is formed of a first layer made of a first semiconductor alloy for electron confinement and a second layer made of a second semiconductor alloy for hole confinement, wherein a thickness and composition of each layer is such that a characteristic hole confinement energy of the bilayer quantum well structure is at least 200 meV.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: A method for manufacturing a gallium nitride (GaN) wafer is provided. In the method for manufacturing the GaN wafer according to an embodiment, an etch stop layer is formed on a substrate, and a first GaN layer is formed on the etch stop layer. A portion of the first GaN layer is etched with a silane gas, and a second GaN layer is formed on the etched first GaN layer. A third GaN layer is formed on the second GaN layer.

Abstract: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

Abstract: A method of epitaxial growth of cubic phase, nitrogen-based compound semiconductor thin films on a semiconductor substrate, for example a <001> substrate, which is periodically patterned with grooves oriented parallel to the <110> crystal direction and terminated in sidewalls, for example <111> sidewalls. The method can provide an epitaxial growth which is able to supply high-quality, cubic phase epitaxial films on a <001> silicon substrate. Controlling nucleation on sidewall facets, for example <111>, fabricated in every groove and blocking the growth of the initial hexagonal phase at the outer region of an epitaxial silicon layer with barrier materials prepared at both sides of each groove allows growth of cubic-phase thin film in each groove and either be extended to macro-scale islands or coalesced with films grown from adjacent grooves to form a continuous film. This can result in a wide-area, cubic phase nitrogen-based compound semiconductor film on a <001> substrate.

Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Abstract: This invention directs to a light-emitting diode. The light-emitting diode includes a substrate, a semiconductor layer and an active layer. The semiconductor layer is disposed on the substrate and has a plurality of undulating structures. The active layer is conformably disposed on the semiconductor layer to have another plurality of undulating structures.

Abstract: A compound semiconductor light-emitting element includes: a substrate; a first electrode provided on one face of the substrate; a plurality of nanoscale columnar crystalline structures in which an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer are stacked in order on the other face of the substrate; a second electrode connected to top portions of the plurality of columnar crystalline structures; and a foundation layer, provided on the side of the other face, in a first region being a partial region of the substrate; wherein a level difference is provided, on the other face, between the first region and a second region being at least part of a remaining region of the substrate excluding the first region.

Abstract: A light-emitting diode chip structure including a conductive substrate, a semiconductor stacking layer and a patterned seed crystal layer is provided. The conductive substrate has a surface. The surface has a first region and a second region alternately distributed over the surface. The semiconductor stacking layer is disposed on the conductive substrate, and the surface of the conductive substrate faces the semiconductor stacking layer. The patterned seed crystal layer is disposed on the first region of the surface of the conductive substrate and between the conductive substrate and the semiconductor stacking layer. The patterned seed crystal layer separates the semiconductor stacking layer from the first region. The semiconductor stacking layer covers the patterned seed crystal layer and the second region, and is electrically connected to the conductive substrate through the second region. A fabrication method of the light-emitting diode chip structure is also provided.

Abstract: A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer.

Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.

Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: An image sensor and a method of manufacturing an image sensor. A method of manufacturing an image sensor may include forming an interconnection and/or an interlayer dielectric over a semiconductor substrate including circuitry connected to an interconnection. A method of manufacturing an image sensor may include forming a photodiode having a first doping layer and/or a second doping layer over an interlayer dielectric, and forming a via hole through a photodiode, which may expose a portion of a surface of an interconnection. A method of manufacturing an image sensor may include forming a barrier pattern over a via hole which may cover an exposed surface of a second doping layer, and a contact plug on and/or over a via hole, which may connect an interconnection and a first doping layer. An upper portion of a contact plug may be etched. An insulating layer may be formed over a contact plug.

Abstract: A manufacturing method of a nitride crystalline film includes following steps. First, a substrate is provided. Next, a first nitride crystalline film is formed on the substrate. A patterned mask is then formed on the first nitride crystalline film. The patterned mask covers a first part of the first nitride crystalline film and exposes a second part of the first nitride crystalline film. Afterwards, the second part is etched, and the first part is maintained. After that, the patterned mask is removed. The first part is then etched to form a plurality of nitride crystal nuclei. Next, a second nitride crystalline film is formed on the substrate, and the second nitride crystalline film is made to cover the nitride crystal nuclei. A nitride film and a substrate structure are also provided.

Abstract: A photonic crystal is grown within a semiconductor structure, such as a III-nitride structure, which includes a light emitting region disposed between an n-type region and a p-type region. The photonic crystal may be multiple regions of semiconductor material separated by a material having a different refractive index than the semiconductor material. For example, the photonic crystal may be posts of semiconductor material grown in the structure and separated by air gaps or regions of masking material. Growing the photonic crystal, rather than etching a photonic crystal into an already-grown semiconductor layer, avoids damage caused by etching which may reduce efficiency, and provides uninterrupted, planar surfaces on which to form electric contacts.

Abstract: A semiconductor device in which semiconductor epitaxial layers are embedded in the source/drain regions includes an element formation region formed in the major surface of a semiconductor substrate, a gate electrode formed on a part of the element formation region, the semiconductor epitaxial layers formed in the source/drain regions of the element formation region so as to sandwich the channel region below the gate electrode, and silicide layers formed on the gate electrode and semiconductor epitaxial layers. Each semiconductor epitaxial layer has a three-layered structure in which first semiconductor films different in material or composition from the semiconductor substrate sandwich a second semiconductor film having a silicidation reactivity higher than that of the first semiconductor films. Each silicide layer extends to the second semiconductor film along the interface between the semiconductor substrate and semiconductor epitaxial layer.

Abstract: In a method for fabricating a vertical light emitting device, the separation or lift-off of the substrate from the light emitting diode structure formed thereon is facilitated by forming voids at the interface between the substrate and the light emitting diode structure where the separation or lift-off occurs. A substrate assembly contains a substrate and an epitaxial layer, and voids are formed at the interface between the substrate and the epitaxial layer in a controlled manner. A light emitting diode structure is then formed on the epitaxial layer, followed by attaching the light emitting diode structure to a superstrate, separating the substrate from the epitaxial layer, and forming a conductive layer and a contact pad in place of the substrate, so as to form a vertical light emitting device.

Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.

Abstract: A method for fabricating a semiconductor layer comprising: a) growing a semiconductor layer on a foreign substrate; b) forming at least one opening on the semiconductor layer, wherein the opening exposes the interface between the semiconductor layer and the foreign substrate; and c) removing at least part of the semiconductor solid state material along the interface between the semiconductor layer and the foreign substrate. The removing step c) is preferably achieved by selective interfacial chemical etching. The semiconductor layer may be utilized as a substrate for fabrication of a wide variety of electronic and opto-electronic devices and integrated circuitry products.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: A semiconductor light emitting diode having a textured structure and a method of manufacturing the same are provided. The semiconductor light emitting diode includes a first semiconductor layer formed into a textured structure, an intermediate layer formed between the textured structures of the patterned first semiconductor layer, and a second semiconductor layer, an active layer, and a third semiconductor layer sequentially formed on the first semiconductor layer and the intermediate layer.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: The present invention discloses a light emitting diode (LED) element and a method for fabricating the same, which can promote light extraction efficiency of LED, wherein a substrate is etched to obtain basins with inclined natural crystal planes, and an LED epitaxial structure is selectively formed inside the basin. Thereby, an LED element having several inclines is obtained. Via the inclines, the probability of total internal reflection is reduced, and the light extraction efficiency of LED is promoted.

Abstract: A MEMS-based display device is described, wherein an array of interferometric modulators are configured to reflect light through a transparent substrate. The transparent substrate is sealed to a backplate and the backplate may contain electronic circuitry fabricated on the backplane. The electronic circuitry is placed in electrical communication with the array of interferometric modulators and is configured to control the state of the array of interferometric modulators.

Abstract: A nondestructive testing method for an oxide semiconductor layer includes the steps of applying excitation light to an amorphous or polycrystalline target oxide semiconductor layer to be tested and measuring an intensity of photoluminescence in a wavelength region longer than a wavelength corresponding to a bandgap energy among light emitted from the target oxide semiconductor layer; and estimating a film property of the target oxide semiconductor layer on the basis of measurement results.

Abstract: By using a first substrate which has a light-transmitting property and whose first face is provided with a light-absorbing layer, a mixture including an organic compound and an inorganic material is irradiated with light having a wavelength, which is absorbed by the inorganic material to heat the mixture, and thereby a film of the organic compound included in the mixture is formed on the first face of the first substrate. Then, the first face of the first substrate and a deposition surface of a second substrate are arranged to be adjacent to or in contact with each other, irradiation with light having a wavelength, which is absorbed by the light-absorbing layer is conducted from a second face side of the first substrate, to heat the organic compound, and thereby at least part of the organic compound is formed as a film on the deposition surface of the second substrate.

Abstract: A light-emitting diode (LED) includes a p-type layer, an n-type layer, and an active layer arranged between the p-type layer and the n-type layer. The active layer includes at least one quantum well adjacent to at least one modulation-doped layer. Alternatively, or in addition thereto, at least one surface of the n-type layer or the p-type layer is texturized to form a textured surface facing the active layer.

Abstract: A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor -on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on -insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed.

Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.

Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.

Abstract: In a method for fabricating a nitride-based compound layer, first, a GaN substrate is prepared. A mask layer with a predetermined pattern is formed on the GaN substrate to expose a partial area of the GaN substrate. Then a buffer layer is formed on the partially exposed GaN substrate. The buffer layer is made of a material having a 10% or less lattice mismatch with GaN. Thereafter, the nitride-based compound is grown laterally from a top surface of the buffer layer toward a top surface of the mask layer and the nitride-based compound layer is vertically grown to a predetermined thickness. Also, the mask layer and the buffer layer are removed via wet-etching to separate the nitride-based compound layer from the GaN substrate.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device structure. The field effect device structure includes a gate electrode located over a channel region within a semiconductor substrate that separates a plurality of source and drain regions within the semiconductor substrate. The channel region includes a surface layer that comprises a carbon doped semiconductor material. The source and drain regions include a surface layer that comprises a semiconductor material that is not carbon doped. The particular selection of material for the channel region and source and drain regions provide for inhibited dopant diffusion and enhanced mechanical stress within the channel region, and thus enhanced performance of the field effect device.

Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

Abstract: Provided is a Group III nitride-based compound semiconductor light-emitting device including aluminum regions. The Group III nitride-based compound semiconductor light-emitting device includes a sapphire substrate; aluminum regions which are formed on the substrate; an AlN buffer layer; an Si-doped GaN n-contact layer; an n-cladding layer formed of multiple layer units, each including an undoped In0.1Ga0.9N layer, an undoped GaN layer, and a silicon (Si)-doped GaN layer; an MQW light-emitting layer including alternately stacked eight well layers formed of In0.2Ga0.8N and eight barrier layers formed of GaN and Al0.06Ga0.94N; a p-cladding layer formed of multiple layers including a p-type Al0.3Ga0.7N layer and a p-type In0.08Ga0.92N layer; a p-contact layer having a layered structure including two p-type GaN layers having different magnesium concentrations; and an ITO light-transmitting electrode.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: A method for forming emitter layer of a solar cell includes preparing a substrate including a first impurity of a first conductive type, diffusing a second impurity of a second conductive type opposite to the first conductive type in the substrate to form a first emitter portion of the emitter layer in the substrate, and selectively heating a portion of the first emitter portion, which corresponds to a position for forming at least one electrode, to form a second emitter portion.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.

Abstract: In a method of manufacturing a vertical type light-emitting diode, a multilayered structure of group III nitride semiconductor compounds is epitaxy deposited on an irregular surface of a substrate. The substrate is then removed to expose an irregular surface of the multilayered structure corresponding to the irregular surface of the substrate. A portion of the exposed irregular surface of the multilayered structure is then etched for forming an electrode contact surface on which an electrode layer is subsequently formed. With this method, no specific planarized region is required on the irregular surface of the substrate. As a result, planarization treatment of the substrate is not necessary. The same substrate with the irregular surface can be reused for fabricating vertical and horizontal light-emitting diodes.