Abstract: A surface protective tape, which is used for a method of producing a semiconductor chip including the steps (a) to (d), and contains a substrate film, and a radiation-curable temporary-adhesive layer and a radiation-curable mask material layer provided on the film in this order; wherein, in the step (b), peeling occurs between the temporary-adhesive layer and the mask material layer before irradiation, and between the mask material layer and the patterned surface described below after irradiation: (a) in the state of having laminated the tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the wafer; laminating a wafer fixing tape on the backing-face side of the ground wafer; and supporting and fixing the wafer to a ring flame; (b) after integrally peeling both the film and the temporary-adhesive layer from the tape thereby to expose the mask material layer on top, forming an opening by cutting a portion of the mask material layer corresponding to a street of the

Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.

Abstract: A method of growing a two-dimensional transition metal dichalcogenide (TMD) thin film and a method of manufacturing a device including the two-dimensional TMD thin film are provided. The method of growing the two-dimensional TMD thin film may include a precursor supply operation and an evacuation operation, which are periodically and repeatedly performed in a reaction chamber provided with a substrate for thin film growth. The precursor supply operation may include supplying two or more kinds of precursors of a TMD material to the reaction chamber. The evacuation operation may include evacuating the two or more kinds of precursors and by-products generated therefrom from the reaction chamber.

Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

Abstract: A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an amount greater than 1 wt. %. The carbon black filler converts the phenoxy resin thermoplastic component from a material that transmits infra-red (IR) wavelengths to a material that absorbs a substantial portion of infra-red (IR) wavelengths.

Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.

Abstract: A wafer processing method is used in processing a wafer including a device area and a peripheral marginal area surrounding the device area. The device area has a plurality of devices and an electrode connected to each device. The wafer processing method includes the steps of cutting a first area of the peripheral marginal area, fixing the front side of the wafer through an adhesive to a carrier substrate, grinding a back side of the wafer, supplying a chemical solution to the back side of the wafer to thereby etch the wafer such that the electrode projects from the back side of the wafer, forming an insulating film on the back side of the wafer, cutting a second area of the peripheral marginal area, the second area being not in contact with the adhesive, thereby removing the second area, and polishing the insulating film.

Abstract: Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.

Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.

Abstract: A wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure are provided. The method includes providing a device wafer including a first front surface and a first back surface and providing a plurality of second chips. The method also includes forming an adhesive layer on the first front surface and patterning the adhesive layer to form a plurality of first through-holes. In addition, the method includes bonding the plurality of second chips with a remaining adhesive layer to cover the plurality of first through-holes. Moreover, the method includes forming a plurality of second through-holes, which are connected with the plurality of first through-holes to form a plurality of first conductive through-holes, each first conductive through-hole includes a second through-hole and a first through-hole. Further, the method includes forming a first conductive plug in a first conductive through-hole to electrically connect to one of the plurality of second chips.

Abstract: A wafer structure and a trimming method thereof are provided. The trimming method includes the following steps. A first wafer having a first surface and a second surface opposite to the first surface is provided. A first pre-trimming mark is formed on the first surface of the first wafer, wherein forming the first pre-trimming mark includes forming a plurality of recesses arranged as a path along a periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon.

Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.

Abstract: A wafer-level packaging method and a package structure are provided. In the packaging method, a device wafer integrated with a first chip is provided. The device wafer includes a first front surface integrated with the first chip and a first back surface opposite to the first front surface. A first oxide layer is formed on the first front surface. A second chip is provided to include a bonding surface, on which a second oxide layer is formed. A carrier substrate is provided to be temporarily bonded with the surface of the second chip that faces away from the bonding surface. The second chip is bonded with the device wafer through bonding the first and the second oxide layers using a fusion bonding process. The second chip and the carrier substrate are debonded. An encapsulation layer is formed on the first oxide layer and covers the second chip.

Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.

Abstract: There is provided a holding apparatus which is capable of rotatably holding, while cooling to a cryogenic temperature, a to-be-processed object in a vacuum chamber. A holding apparatus for rotatably holding, while cooling, a to-be-processed object in a vacuum chamber Vc, has a stage on which the to-be-processed object is placed, a rotary drive device for rotatably supporting the stage, and a cooling device for cooling the stage. Provided that a stage surface side on which the to-be-processed object is placed is defined as an upside, the rotary drive device has: a tubular rotary shaft body which is mounted on a wall surface of the vacuum chamber, in a penetrating manner, through a first vacuum seal; a connection member for connecting an upper end part of the rotary shaft body and a lower surface of the stage in a manner to define a space below the stage; and a driving motor for driving to rotate the rotary shaft body.

Abstract: A method of growing a two-dimensional transition metal dichalcogenide (TMD) thin film and a method of manufacturing a device including the two-dimensional TMD thin film are provided. The method of growing the two-dimensional TMD thin film may include a precursor supply operation and an evacuation operation, which are periodically and repeatedly performed in a reaction chamber provided with a substrate for thin film growth. The precursor supply operation may include supplying two or more kinds of precursors of a TMD material to the reaction chamber. The evacuation operation may include evacuating the two or more kinds of precursors and by-products generated therefrom from the reaction chamber.

Abstract: A method of fabricating a semiconductor structure includes: growing a dielectric layer on a substrate; defining an epitaxial region and a gap region on the dielectric layer; etching a dielectric layer of the epitaxial region to expose the substrate; sequentially growing a gallium nitride buffer layer and an aluminum gallium nitride barrier layer on the exposed substrate. The method of fabricating a semiconductor structure provided by the present application divides the aluminum gallium nitride barrier layer into a plurality of independent portions, thus preventing the microcracks from occurring in the aluminum gallium nitrogen film while increasing the aluminum component, thereby improving the yield rate and reliability of the device.

Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Abstract: A method for producing a semiconductor layer (3), including the following method steps: A creating a release layer (2) on a carrier substrate (1); B applying a semiconductor layer (3) to the release layer (2); C detaching the semiconductor layer (3) from the carrier substrate. The invention is characterized in that, in method step A, the release layer (2) is created so as to fully cover at least a processing side of the carrier substrate, in that, in method step B, the semiconductor layer (3) is applied so as to fully cover the release layer (2) at least on the processing side and partially overlap one or more peripheral sides (5a, 5b) of the carrier substrate and in that, between method steps B and C, in a method step C0, regions of the semiconductor layer (3) that overlap a peripheral side are removed. The invention also relates to a semiconductor wafer, to a device for edge correction, to a detaching unit and to a device for producing a semiconductor layer.

Abstract: A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material.

Abstract: Disclosed are a substrate bonding apparatus and a method of manufacturing a semiconductor device. The substrate bonding apparatus comprises vacuum pumps, a first chuck engaged with the vacuum pumps and adsorbing a first substrate at vacuum pressure of the vacuum pumps, and a pushing unit penetrating a center of the first chuck and pushing the first substrate away from the first chuck. The first chuck comprises adsorption sectors providing different vacuum pressures in an azimuth direction to the first substrate.

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate at low cost and with low total thickness variation (TTV). In some embodiments, an etch stop layer is epitaxially formed on a sacrificial substrate. A device layer is epitaxially formed on the etch stop layer and has a different crystalline lattice than the etch stop layer. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the etch stop layer are between the sacrificial and handle substrates. The sacrificial substrate is removed. An etch is performed into the etch stop layer to remove the etch stop layer. The etch is performed using an etchant comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.

Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack over a first main surface of a substrate, forming a polymer layer over a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.

Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

Abstract: The pressure-sensitive adhesive film according to the present invention comprises a resin film as a substrate and a pressure-sensitive adhesive layer provided at least on a face of the resin film. The resin film has a multi-layer constitution consisting of at least two layers. The resin film has a laser beam reflectance of 5% or higher, but 40% or lower in a wavelength range of 1000 nm to 1100 nm, and has a laser beam transmittance of 5% or lower in the said wavelength range.

Abstract: There is provided a pressure sensitive adhesive sheet for wafer protection (1a) comprising a base material (11), an intermediate layer (12), and a pressure sensitive adhesive layer (13) in this order, wherein the intermediate layer is a layer formed from an intermediate layer-forming composition containing 100 parts by mass of a non-energy ray-curable acrylic polymer (A) and 25 parts by mass or more of an energy ray-curable acrylic polymer (B) having a mass average molecular weight of 50,000 to 250,000; and the pressure sensitive adhesive layer is a layer formed from a pressure sensitive adhesive composition containing an energy ray-curable acrylic polymer (C). The inventive pressure sensitive adhesive sheet for wafer protection is excellent in interfacial adhesion between an intermediate layer and a pressure sensitive adhesive layer after energy ray irradiation.

Abstract: A method for producing a SOI wafer that includes implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer formed of a silicon single crystal to form an ion implanted layer, bonding the ion-implanted surface of the bond wafer to a surface of a base wafer formed of a silicon single crystal through a silicon oxide film formed on the base wafer surface, delaminating the bond wafer at the ion implanted layer by performing delamination heat treatment to fabricate a SOI wafer having a buried oxide film layer and a SOI layer on the base wafer, and performing flattening heat treatment on the SOI wafer in an atmosphere containing argon gas.

Abstract: A Field Effect Transistor (FET) having a substrate; a plurality of active regions disposed on the substrate; and a laterally extending finger-like control electrode disposed on a portion of a surface of the substrate. The active regions are laterally spaced one from the other successively along the laterally extending finger-like control electrode. The laterally extending finger-like control electrode controls a flow of carriers through each one of the plurality of active regions between a source electrode and a drain electrode.

Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a normal-temperature vacuum bonding method, and a fourth step of obtaining an active layer by thinning the first substrate.

Abstract: The present disclosure relates to a method for fabricating a micro-electromechanical system (MEMS) device. In the method, a carrier wafer is received. A MEMS wafer, which includes a plurality of die, is bonded to the carrier wafer. A cavity is formed to separate an upper surface of the carrier wafer from a lower surface of a die of the MEMS wafer. A separation trench is formed to laterally surround the die, wherein formation of the cavity and the separation trench leaves a tethering structure suspending the die over the upper surface of the carrier wafer. The die and carrier wafer are translated with respect to one another to break the tethering structure and separate the die from the carrier wafer.

Abstract: Temporary adhesive material for wafer processing, the temporary adhesive material being used for temporarily bonding support to wafer having circuit-forming front surface and back surface to be processed, including complex temporary adhesive material layer that has first temporary adhesive layer composed of thermosetting siloxane polymer layer (A), second temporary adhesive layer composed of thermosetting polymer layer (B), and third temporary adhesive layer composed of thermoplastic resin layer (C), wherein the polymer layer (A) is cured layer of composition containing (A-1) an organopolysiloxane having alkenyl group within its molecule, (A-2) an organopolysiloxane having R103SiO0.5 unit and SiO2 unit, (A-3) organohydrogenpolysiloxane having two or more Si—H groups per molecule, and (A-4) platinum-based catalyst.

Abstract: The inventive concepts provide a method of completely removing a damage region of a surface of an etch target layer after plasma-etching the etch target layer. The method includes performing a first post-etch plasma treatment process using a first post-treatment gas on the plasma-etched etch target layer. A polarity of ions of the first post-treatment gas may be the same as a polarity of bias power applied to a stage in a plasma apparatus.

Abstract: A wafer processing laminate including support, temporary adhesive material layer laminated on the support, and wafer stacked on temporary adhesive material layer, wafer having front surface on which circuit is formed and back surface to be processed, temporary adhesive material layer including first temporary adhesive layer composed of thermoplastic resin layer (A) laminated on front surface of wafer and second temporary adhesive layer composed of thermosetting resin layer (B) laminated on first temporary adhesive layer, thermoplastic resin layer (A) being soluble in cleaning liquid (D) after processing wafer, thermosetting resin layer (B) being insoluble in cleaning liquid (D) after heat curing and capable of absorbing cleaning liquid (D) such that cleaning liquid (D) permeates into layer (B). This wafer processing laminate allows a wide selection of materials, facilitates separation and collection of processed wafer, meets requirements on various processes, and can increase productivity of thin wafers.

Abstract: A method for manufacturing an SOI wafer having SOI layer includes a thinning step to adjust SOI film thickness of the SOI wafer, including the steps of: (A1) measuring the SOI film thickness of the SOI wafer having the SOI layer before the thinning step; (A2) determining rotational position of the SOI wafer in the thinning step on the basis of a radial SOI film thickness distribution obtained in the measuring of the film thickness and previously determined radial stock removal distribution in the thinning step, and rotating the SOI wafer around the central axis thereof so as to bring the SOI wafer to the determined rotational position; and (A3) thinning the SOI layer of the rotated SOI wafer. The method for manufacturing the SOI wafer can produce an SOI wafer with an excellent radial film thickness uniformity of the SOI layer after the thinning step.

Abstract: A method of preparing a laminate, in which the laminate has a substrate and a support plate, and is provided with a release layer capable of being altered by irradiation with infrared ray, the method including forming the release layer on only a periphery of one of the substrate and the support plate; and laminating the substrate and the support plate through the release layer and a first adhesive layer.

Abstract: De are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a plate structure to apply a pressure to the wafer to separate the back layer in the singulation lines. The pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.

Abstract: A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs.

Abstract: A bonding method including an adhesive layer forming process in which a thermoplastic adhesive is applied to a substrate or a support plate and an adhesive layer is formed; a heating process in which the adhesive layer that is formed on the substrate or the support plate is heated; and a bonding process in which the substrate and the support plate are pressed against each other via the heated adhesive layer, thereby bonding the substrate and the support plate.

Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a bonding thermal processing, and a fourth step of obtaining an active layer by thinning the first substrate.

Abstract: A method of manufacturing an SOI wafer, including (a) forming a thermal oxide film on an SOI layer of an SOI wafer by a heat treatment under an oxidizing gas atmosphere, (b) measuring thickness of the SOI layer after forming the thermal oxide film, (c) performing a batch cleaning, wherein an etching amount of SOI layer is adjusted depending on thickness of the SOI layer measured in step (b) such that thickness of the SOI layer is adjusted to be thicker than a target value after etching, (d) measuring thickness of the SOI layer after batch cleaning, (e) performing a single-wafer cleaning, wherein an etching amount of the SOI layer is adjusted depending on thickness of the SOI layer measured in step (d) such that thickness of the SOI layer is adjusted to be the target value after etching, and removing the thermal oxide film formed in step (a) before or after step (b).

Abstract: The invention relates to a process for transferring an active layer to a final substrate using a temporary substrate, the active layer comprises a first side having a three-dimensional surface topology, the process comprising: a first step of bonding the first side of the active layer to one side of the temporary substrate; a second step of bonding a second side of the active layer to the final substrate; and a third step of separating the active layer and the temporary substrate; the process being characterized in that the side of the temporary substrate possesses a surface topology complementary to the surface topology of the first side of the active layer, so that the surface topology of the temporary substrate encapsulates the surface topology of the first side of the active layer in the bonding first step.

Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

Abstract: A bonding arrangement comprising a silicone-base adhesive composition is suited for temporarily bonding a wafer to a support for wafer processing. The bonding arrangement includes a first temporary bond layer of non-silicone thermoplastic resin, and a second temporary bond layer of thermosetting silicone polymer and/or a third temporary bond layer of thermosetting siloxane-modified polymer. The second and/or third bond layer contains an antistatic agent.

Abstract: Method for processing a semiconductor-wafer having a front surface, back surface, and chamfered-portion composed of a chamfered surface on the front surface side, a chamfered surface on the back surface side, and an end face at a peripheral end, including: mirror-polishing of each portion of the chamfered surface on the front surface side, the chamfered surface on the back surface side, the end face, and an outermost peripheral-portion on the front or back surface adjacent to the chamfered surface; wherein the end face mirror-polishing and mirror-polishing of the outermost peripheral-portion on the front or back surface are performed in one step, after step of mirror-polishing the chamfered surface on the front surface side and step of mirror-polishing the chamfered surface on the back surface side; roll-off amount of the outermost peripheral-portion on the front or back surface is adjusted by one step-performed mirror-polishing of the end face and outermost peripheral-portion.

Abstract: The present invention is a temporary adhesion method for temporarily bonding a support and a wafer via a temporary adhesive material, including attaching the wafer to the support via the temporary adhesive material including a complex temporary adhesive material layer that consists of a thermoplastic resin layer (A) exhibiting a storage modulus E? of 1 to 500 MPa and a tensile rupture strength of 5 to 50 MPa at 25° C. and a thermosetting polymer layer (B) exhibiting a storage modulus E? of 1 to 1000 MPa and a tensile rupture strength of 1 to 50 MPa at 25° C.

Abstract: Provided is a method of treating a wafer in the state where the wafer is fixed on a support plate with an adhesive composition. Although the wafer is treated by a chemical, heating, or exothermic treatment, the method achieves sufficient adhesiveness during the step of treating a surface of the wafer and allows detachment of the support plate from the wafer without damaging the wafer or leaving the adhesive on the wafer after the wafer treating step. The method of treating a wafer of the present invention includes the steps of: fixing a wafer on a support plate via an adhesive composition containing a curable adhesive component to be crosslinked and cured by light irradiation or heating; crosslinking and curing the curable adhesive component by light irradiation or heating of the adhesive composition; treating a surface of the wafer fixed on the support plate by a chemical, heating, or exothermic treatment; and detaching the support plate from the treated wafer.

Abstract: A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched epitaxial oxide interlayer inhibits propagation of threading dislocations from one semiconductor layer of the graded buffer layer material stack into an overlying semiconductor layer of the graded buffer layer material stack. This allows for decreasing the thickness of each semiconductor layer within the graded buffer layer material stack. The topmost semiconductor layer of the graded buffer layer material stack, which is a relaxed layer, contains a lower defect density than the other semiconductor layers of the graded buffer layer material stack.