Thinning Of Semiconductor Substrate Patents (Class 438/459)
  • Patent number: 9330957
    Abstract: A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 3, 2016
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Aomar Halimaoui, Marc Zussy
  • Patent number: 9306116
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface by interfusing optical interconnects on one wafer with optical interconnects on a second wafer, interfusing electrical interconnects on one wafer with electrical interconnects on the second wafer, and interfusing a dielectric intermediary bonding layer on one wafer with the dielectric intermediary bonding layer on the second wafer to bond the wafers together with electrical interconnections and optical interconnections between the wafers. The methods are also applicable to the bonding of semiconductor wafers to provide a high density of electrical interconnects between wafers.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 5, 2016
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Patent number: 9297998
    Abstract: An electrowetting display device including an electrowetting element with a first support plate, a second support plate, a first fluid and a second fluid immiscible with the first fluid. A voltage may be applied between a first electrode and a second electrode. At least one of the first electrode and the second electrode comprises a semiconducting material.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 29, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Pavel Novoselov, Sukhdip Sandhu
  • Patent number: 9263258
    Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: February 16, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Seiji Nagai, Shiro Yamazaki, Takayuki Sato, Yasuhide Yakushi, Koji Okuno, Koichi Goshonoo
  • Patent number: 9245736
    Abstract: A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 26, 2016
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hocine Bouzid Ziad, Peter Moens, Eddy De Backer
  • Patent number: 9230894
    Abstract: A method for manufacturing a chip package is provided. The method including: arranging a plurality of dies over a carrier; depositing encapsulation material over the carrier wherein the plurality of dies are covered by the encapsulation material thereby forming a structure including the encapsulation material and the plurality of dies; and removing encapsulation material thereby forming a thinned portion of the structure and a further portion of the structure including encapsulation material thicker than the thinned portion.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 5, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Edward Fuergut, Irmgard Escher-Poeppel
  • Patent number: 9224696
    Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 29, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shih-Wei Li, Yun-Han Chu, Guo-Chih Wei
  • Patent number: 9224630
    Abstract: A method for producing a product wafer having chips thereon, comprising the steps of: processing the first side of the product wafer bonding the product wafer with its first side onto a first rigid carrier wafer with a first intermediate layer consisting of one first adhesion layer applied at least on the edge side, processing a second side of the product wafer, bonding of the product wafer with its second side on a second rigid carrier wafer with a second intermediate layer consisting of one second adhesion layer applied at least on the edge side, characterized in that the first intermediate layer and the second intermediate layer are made different such that the first carrier wafer can be separated selectively before the second carrier wafer.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 29, 2015
    Assignee: EV GROUP E. THALLNER GMBH
    Inventors: Jürgen Burggraf, Markus Wimplinger, Harald Wiesbauer
  • Patent number: 9224904
    Abstract: Composite substrates include a silicon layer disposed on a ceramic layer. Different thermal expansion coefficient for the composite substrates can be achieved by changing the thermal expansion coefficient of the ceramic layer. Composite substrates can include two layers of silicon sandwiching a layer of ceramic.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: December 29, 2015
    Inventors: Ananda Kumar, Tue Nguyen
  • Patent number: 9219058
    Abstract: A high voltage switching circuit includes first and second group III-V transistors, the second group III-V transistor having a greater breakdown voltage than the first group III-V transistor. The circuit further includes a silicon diode in a parallel arrangement with the first group III-V transistor, the parallel arrangement being in cascade with the second group III-V transistor. The circuit is effectively a three-terminal device, where a first terminal is coupled to a gate of the second III-V transistor, a source of the first III-V transistor, and an anode of the silicon diode. A second terminal is coupled to a gate of the first group III-V transistor, and a third terminal is coupled to a drain of the second group III-V transistor. The first group III-V transistor might be an enhancement mode transistor. The second group III-V transistor might be a depletion mode transistor. The first and second group III-V transistors can be GaN HEMTs.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9214398
    Abstract: A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jam-Wem Lee
  • Patent number: 9202752
    Abstract: A semiconductor device includes a first semiconductor substrate including a first integrated circuit, a second semiconductor substrate mounted over the first semiconductor substrate, the second semiconductor substrate including a second integrated circuit, a post made of an inorganic substance and formed over the first semiconductor substrate, an adhesive layer made of an organic substance arranged between the first and the second semiconductor substrates, and a substrate-through-via made of an electrical conductor extending through the second semiconductor substrate and the post, the substrate-through-via extending to the first semiconductor substrate.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: December 1, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Hideki Kitada
  • Patent number: 9202711
    Abstract: A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 1, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Qingmin Liu, Jeffrey L. Libbert
  • Patent number: 9202753
    Abstract: A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 1, 2015
    Assignee: Infineon Technologies AG
    Inventors: Johann Kosub, Michael Ledutke
  • Patent number: 9190539
    Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 17, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Crocifisso Marco Antonio Renna
  • Patent number: 9177921
    Abstract: A method for manufacturing a semiconductor device with a treated member, includes: subjecting an adhesive support having a substrate and an adhesive layer capable of increasing or decreasing in adhesiveness upon irradiation with an actinic ray, radiation or heat to irradiation of the adhesive layer with an actinic ray, radiation or heat, adhering a first surface of a to-be-treated member to the adhesive layer of the adhesive support, applying a mechanical or chemical treatment to a second surface different from the first surface of the to-be-treated member to obtain a treated member, and detaching a first surface of the treated member from the adhesive layer of the adhesive support, wherein the irradiation of the adhesive layer with an actinic ray, radiation or heat is conducted so that adhesiveness decreases toward an outer surface from an inner surface on the substrate side of the adhesive layer.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: November 3, 2015
    Assignee: FUJIFILM Corporation
    Inventors: Shiro Tan, Kazuhiro Fujimaki, Yu Iwai, Ichiro Koyama, Atsushi Nakamura
  • Patent number: 9159610
    Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDIRES, INC.
    Inventors: Xunyuan Zhang, Moosung Chae, Larry Zhao
  • Patent number: 9159863
    Abstract: In a method of forming a CIGS film absorption layer, a first precursor is provided including a first substrate having a major process precursor film formed thereon, the major process precursor film containing two or more of Cu, In, Ga, and Se. A second precursor is provided including a second substrate having an element supplying precursor film formed thereon, the element supply precursor film containing two or more of Cu, In, Ga and Se. The precursors are oriented with the major process precursor film and element supplying precursor film facing one another so as to allow diffusion of elements between the films during annealing. The oriented films are annealed and then the precursors are separated, wherein the CIGS film is formed over the first substrate and either a CIGS film or a precursor film containing two or more of Cu, In, Ga, and Se remains over the second substrate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: October 13, 2015
    Assignee: TSMC Solar Ltd.
    Inventors: Chung-Hsien Wu, Wen-Chin Lee
  • Patent number: 9136144
    Abstract: A semiconductor wafer contains first semiconductor die. TSVs are formed through the semiconductor wafer. Second semiconductor die are mounted to a first surface of the semiconductor wafer. A first tape is applied to on a second surface of the semiconductor wafer. A protective material is formed over the second die and first surface of the wafer. The protective material can be encapsulant or polyvinyl alcohol and water. The wafer is singulated between the second die into individual die-to-wafer packages each containing the second die stacked on the first die. The protective material protects the wafer during singulation. The die-to-wafer package can be mounted to a substrate. A build-up interconnect structure can be formed over the die-to-wafer package. The protective material can be removed. Underfill material can be deposited beneath the first and second die. An encapsulant is deposited over the die-to-wafer package.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: September 15, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: TaegKi Lim, JaEun Yun, SungYoon Lee
  • Patent number: 9129899
    Abstract: Embodiments of a method for thinning a wafer are provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. Embodiments of system for forming the thinned wafer are also provided.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Chung-Shi Liu
  • Patent number: 9123769
    Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 1, 2015
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Ho Hyun Kim, Seung Bae Hur, Seung Wook Song, Jeong Hwan Park, Ha Yong Yang, In Su Kim
  • Patent number: 9087767
    Abstract: The invention relates to a process for manufacturing a semiconductor structure comprising a functionalized layer on a support substrate, comprising the following steps: (a) implanting ionic species in a source substrate comprising the said functionalized layer and a sacrificial buffer layer located under the functionalized layer relative to the direction of implantation, to a depth delimiting the thickness of an upper part of the source substrate comprising the functionalized layer and at least part of the buffer layer; (b) bonding the source substrate to the support substrate; (c) fracturing the source substrate and transferring the upper part of the source substrate to the support substrate; (d) removing the buffer layer by selective etching with respect to the functionalized layer.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 21, 2015
    Assignee: SOITEC
    Inventor: Ionut Radu
  • Patent number: 9076841
    Abstract: A method of transferring a layer including: a) providing a layer joined to an initial substrate with a binding energy E0; b) bonding a front face of the layer on an intermediate substrate according to an intermediate bonding energy Ei; c) detaching the initial substrate from the layer; e) bonding a rear face onto a final substrate according to a final bonding energy Ef; and f) debonding the intermediate substrate from the layer to transfer the layer onto the final substrate; step b) comprising a step of forming siloxane bonds Si—O—Si, step c) being carried out in a first anhydrous atmosphere and step f) being carried out in a second wet atmosphere such that the intermediate bonding energy Ei takes a first value Ei1 in step c) and a second value Ei2 in step f), with Ei1>E0 and Ei2<Ef.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: July 7, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frank Fournel, Maxime Argoud, Jeremy Da Fonseca, Hubert Moriceau
  • Patent number: 9076840
    Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer having the step of performing a first sacrificial oxidation treatment on the aforementioned bonded SOI wafer in which the delamination has been performed after a first RTA treatment has been performed thereon and then performing a second sacrificial oxidation treatment thereon after a second RTA treatment has been performed thereon, wherein the first and second RTA treatments are performed under a hydrogen gas containing atmosphere and at a temperature of 1100° C. or more, wherein after a thermal oxide film has been formed on the aforementioned SOI layer front surface by performing only thermal oxidation by a batch type heat treating furnace at a temperature of 900° C. or more and 1000° C. or less in the first and second sacrificial oxidation treatments, a treatment for removing the thermal oxide film is performed.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 7, 2015
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Hiroji Aga, Isao Yokokawa, Toru Ishizuka, Masahiro Kato
  • Patent number: 9070637
    Abstract: A via hole is formed on a base substrate before a device circuit is formed, and thermal oxidation is performed to form a thermal oxidation layer on a surface of the base substrate on which the device circuit is formed and a surface in the via hole. The device circuit having a conductive section is formed on the base substrate after the thermal oxidation, and then, a conductive body is embedded in the via hole.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: June 30, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Tsuyoshi Yoda, Nobuaki Hashimoto
  • Patent number: 9064858
    Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: June 23, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9058990
    Abstract: A spall releasing plane is formed embedded within a Group III nitride material layer. The spall releasing plane includes a material that has a different strain, a different structure and a different composition compared with the Group III nitride material portions that provide the Group III nitride material layer and embed the spall releasing plane. The spall releasing plane provides a weakened material plane region within the Group III nitride material layer which during a subsequently performed spalling process can be used to release one of the portions of Group III nitride material from the original Group III nitride material layer. In particular, during the spalling process crack initiation and propagation occurs within the spall releasing plane embedded within the original Group III nitride material layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Stephen W. Bedell, Keith E. Fogel, John A. Ott, Devendra K. Sadana
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 9040355
    Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Philip H. Bowles, Paige M. Holm, Stephen R. Hooper, Raymond M. Roop
  • Patent number: 9034730
    Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: May 19, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
  • Publication number: 20150132923
    Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 14, 2015
    Inventor: Gweltaz Gaudin
  • Patent number: 9029204
    Abstract: A method for manufacturing a semiconductor device is provided, the method comprising: fabricating a semiconductor element on a semiconductor substrate; joining a surface of the semiconductor substrate to a support member, the surface being on a side where the semiconductor element is fabricated; and polishing a surface on an opposite side of the surface of the semiconductor substrate where the semiconductor element is fabricated and reducing a thickness of the semiconductor substrate, in a state where the semiconductor substrate and the support member are joined.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: May 12, 2015
    Assignee: OMRON Corporation
    Inventors: Yasuhiro Horimoto, Yusuke Nakagawa, Tadashi Inoue, Toshiyuki Takahashi
  • Patent number: 9029241
    Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 12, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mineo Shimotsusa, Takeshi Ichikawa, Yasuhiro Sekine
  • Patent number: 9029200
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Patent number: 9029184
    Abstract: To provide a resource-saving photoelectric conversion device with excellent photoelectric conversion characteristics. Thin part of a single crystal semiconductor substrate, typically a single crystal silicon substrate, is detached to structure a photoelectric conversion device using a thin single crystal semiconductor layer, which is the detached thin part of the single crystal semiconductor substrate. The thin part of the single crystal semiconductor substrate is detached by a method in which a substrate is irradiated with ions accelerated by voltage, or a method in which a substrate is irradiated with a laser beam which makes multiphoton absorption occur. A so-called tandem-type photoelectric conversion device is obtained by stacking a unit cell including a non-single-crystal semiconductor layer over the detached thin part of the single crystal semiconductor substrate.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura
  • Patent number: 9018078
    Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics SA, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Benoit Sklenard, Perrine Batude
  • Patent number: 9018031
    Abstract: A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Akira Tsukamoto
  • Publication number: 20150108502
    Abstract: The present invention relates to a heat dissipation substrate, which is a composite substrate composed of two layers, and which is characterized in that a surface layer (first layer) (1) is configured of single crystal silicon and a handle substrate (second layer) (2) is configured of a material that has a higher thermal conductivity than the first layer. A heat dissipation substrate of the present invention has high heat dissipation properties.
    Type: Application
    Filed: May 7, 2013
    Publication date: April 23, 2015
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Makoto Kawai
  • Patent number: 9011632
    Abstract: A support disk fixing apparatus which includes an upper surface to which a wafer is bonded, a lower surface, a cylindrical side surface between the upper surface and the lower surface, and a chamfered portion between the upper surface and the side surface, includes a base upon which the support disk is placed; and a fixture that is provided on the base, and that has a first surface that abuts against the side surface of the support disk and covers the side surface of the support disk, and a second surface that abuts against the chamfered portion of the support disk and covers the chamfered portion of the support disk.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: April 21, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Taichi Yoshida
  • Patent number: 9013039
    Abstract: A method for handling and supporting a device wafer during a wafer thinning process and the resulting device are provided. Embodiments include forming a plurality of solder bumps on a first surface of a substrate having a first and a second surface; removing a portion from a periphery of the first surface of the substrate; forming a temporary bonding material on a first carrier; bonding the first surface of the substrate with the temporary bonding material of the first carrier; affixing the second surface of the substrate to a second carrier; and removing the temporary bonding material.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Rahul Agarwal
  • Publication number: 20150104927
    Abstract: A method for fabricating a semiconductor device is provided. The method includes: providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit; thinning the second wafer from the second rear surface; and forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit.
    Type: Application
    Filed: December 17, 2014
    Publication date: April 16, 2015
    Inventors: Shang-Chun Chen, Cha-Hsin Lin, Yu-Chen Hsin
  • Patent number: 9006081
    Abstract: Methods of manufacturing a plurality of semiconductor chips are provided. The method may include providing a middle layer between a substrate and a carrier to combine the carrier with the substrate, thinning the substrate; after thinning the substrate, separating the carrier from the substrate; and after the carrier is separated from the substrate, cutting the substrate to form the plurality of semiconductor chips, wherein the middle layer is adhered to the carrier with a first bonding force, and the middle layer is adhered to the substrate with a second bonding force, and wherein the second bonding force is greater than the first bonding force.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Seok Ahn, Il Hwan Kim, Jung-Hwan Kim, Sangwook Park, Chungsun Lee, Kwang-chul Choi
  • Patent number: 9006085
    Abstract: A wafer processing method including a fixing step of providing a wafer on a protective member so that a device area of the wafer faces an unevenness absorbing member provided in a recess of the protective member and providing an adhesive outside the device area to thereby fix the protective member and the wafer, a grinding step of holding the protective member on a holding table in the condition where the back side of the wafer is exposed and next grinding the back side of the wafer by using a grinding unit to thereby reduce the thickness of the wafer to a predetermined thickness, and a removing step of removing the protective member from the wafer. The adhesive is locally provided outside of the device area, so that the protective member can be easily removed from the wafer without leaving the adhesive on the front side of each device.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Disco Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 8997822
    Abstract: According to an embodiment of the present disclosure, a substrate inverting device for inverting front and rear surfaces of a substrate is provided. The substrate includes a first holding unit configured to hold one surface of the substrate and a second holding unit disposed to face the first holding unit and configured to hold one surface of the substrate. Further, the substrate includes a moving mechanism configured to relatively move at least one of the first holding unit and the second holding unit to approach each other and stay spaced apart from each other, and a transfer mechanism configured to hold the one surface of the substrate. In this case, a support of the substrate in the first holding unit, the second holding unit and the transfer mechanism is performed by a Bernoulli chuck.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Yasuharu Iwashita, Osamu Hirakawa, Masaru Honda, Akira Fukutomi
  • Patent number: 8999814
    Abstract: A semiconductor device fabricating method includes forming device chip regions and a monitor chip region for processing management, on a substrate surface layer on one main surface side of a semiconductor substrate wafer, each device chip region having an active region and an edge region; after forming metal films on front surface of the device chip regions and the monitor chip region by vapor deposition and photolithography, forming protective films on the front surfaces of the device chip regions and monitor chip region; and grinding and polishing another main surface side of the semiconductor substrate wafer to thin the semiconductor substrate wafer. A difference between an area of one chip occupied by the protective film of the monitor chip region and an area of one chip occupied by the protective film of the device chip region is 20% or less.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: April 7, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Takashi Shiigi
  • Patent number: 8999815
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: April 7, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Publication number: 20150093880
    Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Inventors: Sang-wook Ji, Hyoung-yol Mun, Yeong-Iyeol Park, Tae-je Cho
  • Patent number: 8993411
    Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
    Type: Grant
    Filed: February 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Siliconfile Technologies Inc.
    Inventors: Heui-Gyun Ahn, Se-Jung Oh, In-Gyun Jeon, Jun-Ho Won
  • Patent number: 8993413
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor wafer having a thick portion in an outer circumferential end portion and a thin portion in a central portion, attaching a support material to one surface of the semiconductor wafer, dividing the semiconductor wafer into the thick portion and the thin portion, and cutting the thin portion, after the division, while supporting the thin portion by the support material.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Yoshiaki Terasaki
  • Patent number: 8987109
    Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Isao Yokokawa, Nobuhiko Noto