Compound Semiconductor Patents (Class 438/46)
  • Patent number: 9666429
    Abstract: A method for growing Group III nitride is provided, which includes the following steps. A plurality of notches separated from each other are formed at the epitaxial substrate surface via the pattering process. The plurality of notches each has at least one stepping structure with a predetermined inclination angle, wherein the stepping structure in each notch gradually descends towards the center of the corresponding notch. The Group III nitride is grown on the epitaxial substrate via epitaxy process. Wherein, the Group III nitride growing at an upper portion of the epitaxial substrate restricts the vertical growth of the Group III nitride growing at the lower portion of the epitaxial substrate, and the Group III nitride growing at the lower portion of the epitaxial substrate promotes the lateral growth of the Group III nitride growing at the upper portion of the epitaxial substrate.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: May 30, 2017
    Assignee: EPILEDS TECHNOLOGIES, INC.
    Inventors: Kung-Hsieh Hsu, Ming-Sen Hsu
  • Patent number: 9634181
    Abstract: In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a substrate. The III-nitride layer has a bulk lattice constant a layer. In some embodiments, [(|a substrate?a layer|)/asubstrate]*100% is no more than 1%.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: April 25, 2017
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Nathan Frederick Gardner, Melvin Barker McLaurin, Michael Jason Grundmann, Werner Goetz, John Edward Epler, Qi Ye
  • Patent number: 9614155
    Abstract: The vapor deposition apparatus employs scanning vapor deposition, and includes a limiting component including a first plate portion; a second plate portion provided with a space from the first plate portion; and a joint portion combining the first plate portion with the second plate portion, the first plate portion being provided with an first opening, the second plate portion being provided with an second opening that faces the first opening, the vapor deposition apparatus including a first space between the first opening and the second opening, the vapor deposition apparatus including a second space between the first plate portion and the second plate portion, the first space being connected to the second space, the vapor deposition apparatus including a third space that is in the outside of the limiting component, the second space being connected to the third space.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 4, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiyuki Isomura, Katsuhiro Kikuchi, Shinichi Kawato, Satoshi Inoue, Takashi Ochi, Yuhki Kobayashi, Eiichi Matsumoto, Masahiro Ichihara
  • Patent number: 9590177
    Abstract: An organic light-emitting display panel and a fabrication method thereof include using an inkjet printing process to form the organic emission material of the display panel and providing a specific design of the relative position of the spacer and the planarization layer with ink-repellent material such that the spacer can be effectively fixed on the array substrate without falling from the planarization layer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: March 7, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Shou-Wei Fang, Wei-Hao Tseng, Chia-Yang Lu, Chien-Tao Chen, Tsung-Hsiang Shih, Hung-Che Ting
  • Patent number: 9553267
    Abstract: A method of manufacturing an organic light-emitting device including a plurality of pixels using an organic solution spray apparatus, where each of the pixels comprises a plurality of sub-pixels having different colors, includes: preparing a substrate on which a plurality of sub-pixel regions is defined; generating a potential difference between a nozzle of the organic solution spray apparatus and the sub-pixel regions; spraying an organic solution from the nozzle of the organic solution spray apparatus to the sub-pixel regions; and forming an organic material layer by selectively depositing the organic solution to the sub-pixel regions using the potential difference between the nozzle and the sub-pixel regions.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventor: Sunghwan Cho
  • Patent number: 9553013
    Abstract: A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: January 24, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Michael A. Stuber, George Imthurn
  • Patent number: 9543146
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device, comprising: forming a first nitride semiconductor layer on a substrate using a first temperature; decreasing a substrate temperature to a second temperature lower than the first temperature, after the forming the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer using the second temperature; increasing the substrate temperature to a third temperature higher than the first temperature, after the forming the second nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer using the third temperature.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: January 10, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Yasuhiro Isobe, Hung Hung, Akira Yoshioka
  • Patent number: 9543520
    Abstract: A manufacturing method of a mask for deposition including forming a second layer on a side of a first layer, coating a photoresist layer on a side of the second layer, forming a plurality of photoresist patterns which penetrate the photoresist layer according to an exposing and developing process, forming a plurality of pattern grooves in the second layer by etching portions of the second layer, which are exposed through the plurality of photoresist patterns, forming an electro-forming mold by removing the photoresist layer from the second layer, disposing an electrode plate to contact the second layer of the electro-forming mold, performing an electro-forming process of growing a metal layer from the electrode plate in spaces in the corresponding pattern grooves of the second layer of the electro-forming mold, to form a deposition mask, and separating the deposition mask from the electrode plate.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 10, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minho Moon, Youngmin Moon, Sungsoon Im
  • Patent number: 9530962
    Abstract: Methods of fabricating a device having laterally patterned first and second sub-devices, such as subpixels of an OLED, are provided. Exemplary methods may include depositing via organic vapor jet printing (OVJP) a first organic layer of the first sub-device and a first organic layer of the second sub-device. The first organic layer of the first sub-device and the first organic layer of the second sub-device are both the same type of layer, but have different thicknesses. The type of layer is selected from an ETL, an HTL, an HIL, a spacer and a capping layer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 27, 2016
    Assignee: Universal Display Corporation
    Inventors: Siddharth Harikrishna Mohan, Paul E. Burrows, Julia J. Brown
  • Patent number: 9496348
    Abstract: The method for doping a GaN-base semiconductor to fabricate a p-n junction includes a first step consisting in providing a substrate including a GaN-base semiconductor material layer covered by a silicon-base mask. The method includes a second step of performing implantation of impurities in the mask so as to transfer additional dopant impurities of Si type by diffusion from the mask to the semiconductor material layer to form an n-type area adjacent to a p-type area. Configured heat treatment is then performed to activate the dopant impurities and the additional dopant impurities.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: November 15, 2016
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Claire Agraffeil
  • Patent number: 9444077
    Abstract: A method of manufacturing a light-emitting element. The method includes forming an underlayer that includes a reflective electrode, forming a bank that has liquid repellency, irradiating the bank with characteristic energy rays to decrease liquid repellency of the bank, and forming a functional layer. The bank is formed on the underlayer and is provided with an opening and an inclined portion surrounding the opening. The opening has a shape that has a long axis and a short axis and is positioned above the reflective electrode. In plan view, end sections of the inclined portion in a direction of the long axis overlap the upper surface of the reflective electrode, while central sections of the inclined portion in the direction of the long axis do not overlap the upper surface of the reflective electrode.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 13, 2016
    Assignee: JOLED INC.
    Inventor: Yumeji Takashige
  • Patent number: 9425436
    Abstract: A method of making organic light emitting diode array includes following steps. A base having a number of first electrodes on a surface of the base is provided. A first organic layer is located on the surface of the base to cover the first electrodes. A template with a first patterned surface is provided, wherein the first patterned surface includes a number of grooves with different depths. The first patterned surface of the template is attached on the first organic layer and separated from each other, wherein a number of protruding structures with different heights is formed. An organic light emitting layer is deposited to cover the protruding structures. A second organic layer is located on the organic light emitting layer. A second electrode is applied to electrically connected to the second organic layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 23, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jung-An Cheng, Liang-Neng Chien, Dong An, Zhen-Dong Zhu, Chang-Ting Lin, I-Wei Wu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9356191
    Abstract: An epitaxial wafer includes a growth substrate, a mask pattern disposed on the growth substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern and including a first void disposed on the masking region. The first void includes a lower void disposed between a lower surface of the epitaxial layer and the masking region, and an upper void extending from the lower void into the epitaxial layer, the lower void having a greater width than the upper void.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 31, 2016
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Kyu Ho Lee, Chang Suk Han, Hwa Mok Kim, Daewoong Suh, Chi Hyun In, Jong Hyeon Chae
  • Patent number: 9349908
    Abstract: Provided are a highly reliable semiconductor light-emitting element having uniform protrusions that are arranged regularly and have the same size and a method of producing the same. The method of producing a semiconductor light-emitting element according to the present invention includes: forming a mask layer having a plurality of openings that are arranged at equal intervals along a crystal axis of a semiconductor structure layer on the surface of the semiconductor structure layer; performing a plasma treatment on the surface of the semiconductor structure layer exposed from the openings in the mask layer; removing the mask layer; and wet-etching the surface of the semiconductor structure layer to form protrusions on the surface of the semiconductor structure layer.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 24, 2016
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Takanobu Akagi, Tatsuma Saito, Mamoru Miyachi
  • Patent number: 9331252
    Abstract: Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength. The structure can further include a second region positioned adjacent to the first region to emit radiation at a second wavelength different than the first wavelength. The second region has a second value of the material characteristic that is different than the first value, with the first and second values of the characteristic forming a potential gradient to drive electrons, holes, or both electrons and holes in the radiative structure from the first region to the second region. In a further particular embodiment, the material characteristic includes material polarization.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 3, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 9324909
    Abstract: Disclosed herein is a light emitting diode, the structure of the light emitting diode comprises a substrate, a first-type semiconductor layer, a structural layer, a light emitting layer, a second-type semiconductor layer, a transparent conductive layer, a first contact pad and a second contact pad in regular turn. The structural layer comprises a stacked structure having a trapezoid sidewall and nano columns extending from the trapezoid sidewall in regular arrangement. Also, a method for fabricating the light emitting diode is disclosed.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: April 26, 2016
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chang-Chin Yu, Hsiu-Mu Tang, Mong-Ea Lin
  • Patent number: 9318559
    Abstract: A semiconductor substrate includes a sapphire substrate including a c-plane main surface and a groove in a surface thereof, the groove including side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. The side surfaces of the groove are an a-plane of sapphire. An axis of the Group III nitride semiconductor layer, perpendicular to one of the side surface of the groove, is a c-axis of Group III nitride semiconductor. A plane of the Group III nitride semiconductor, parallel to the main surface of the sapphire substrate, is an a-plane of Group III nitride semiconductor.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 19, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Naoyuki Nakada, Koji Okuno, Yasuhisa Ushida
  • Patent number: 9281437
    Abstract: Disclosed are a light emitting device, a method of fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, an electron blocking layer on the active layer, and a second conductive semiconductor layer on the electron blocking layer. The electron blocking layer includes a first electron blocking layer and an interrupted diffusion layer on the first electron blocking layer.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 8, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dong Wook Kim, June O Song, Rak Jun Choi, Jeong Tak Oh
  • Patent number: 9246312
    Abstract: A Fabry-Pérot tuneable filter device is described with reflecting elements separated by an optical path length to form an optical resonator cavity. A first actuator means is directly or indirectly coupled with a first reflecting element. And the first actuator means is configured to modulate the optical path length between first and second reflecting elements by a modulation amplitude to thereby sweep the optical resonator cavity through a band of optical resonance frequencies with a sweep frequency of 70 kHz or more. And the mechanical coupling between selected elements of the arrangement is sufficiently low such that when operated at the sweep frequency, the selected elements act as a system of coupled oscillating elements. In addition or alternatively, the first actuator means is directly or indirectly coupled with the first reflecting element so as to substantially drive the first reflecting element only.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: January 26, 2016
    Assignee: Ludwig-Maximilians-Universität München
    Inventors: Robert Huber, Wolfgang Wieser, Thomas Klein, Christoph Eigenwillig, Benjamin Biedermann, Dieter Muellner, Michael Eder
  • Patent number: 9210775
    Abstract: A method and system for storage of perishable items is provided. The system includes at least one enclosed compartment to store the perishable items. At least one of the walls of the enclosed compartment is detachable to allow movement of the perishable items in and out of the compartment. The system further includes a plurality of light emitting diodes (LEDs) that are disposed on one of the walls of the compartment. The LEDs include one or more blue LEDs that are coated with a layer of phosphor material. The LEDs are electrically coupled with a power source. The system further includes a control unit that is configured to control power supplied by the power source to the LEDs based on presence of the perishable items in the compartment.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 8, 2015
    Assignee: General Electric Company
    Inventors: James Edward Murphy, Anant Achyut Setlur
  • Patent number: 9196687
    Abstract: A semiconductor substrate includes a sapphire substrate including an a-plane main surface and a groove in a surface thereof, the groove includes side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. Both side surfaces of the groove assume a c-plane of sapphire. An axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor. A plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 24, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Naoyuki Nakada, Koji Okuno, Yasuhisa Ushida
  • Patent number: 9184051
    Abstract: A method of producing a nitride compound semiconductor component includes providing a growth substrate having a silicon surface, growing a buffer layer containing an aluminum-containing nitride compound semiconductor onto the silicon surface, growing a stress layer structure that produces a compressive stress, and growing a functional semiconductor layer sequence onto the stress layer structure, wherein the stress layer structure includes a first GaN semiconductor layer and a second GaN semiconductor layer, a masking layer is embedded in the first GaN semiconductor layer, an Al(Ga)N-intermediate layer that produces a compressive stress is disposed between the first GaN semiconductor layer and the second GaN semiconductor layer, and the stress layer structure does not contain further Al(Ga)N-intermediate layers.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 10, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Peter Stauss, Philipp Drechsel
  • Patent number: 9147809
    Abstract: A flip chip light emitting diode packaging structure includes a substrate and an LED located on the substrate. The LED includes a P electrode and a N electrode. The substrate includes a first electrode and a second electrode mounted on a top surface of the substrate. The first electrode and the second electrode have a first protrusion and a second protrusion. The P electrode and the N electrode are fixed on the top surface of the first protrusion and the second protrusion through the solder. The bottom edge of the P electrode and the N electrode is beyond the top edge of the first protrusion and the second protrusion.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: September 29, 2015
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Hou-Te Lin, Chao-Hsiung Chang, Pin-Chuan Chen, Lung-Hsin Chen
  • Patent number: 9142724
    Abstract: A nitride-based semiconductor light-emitting device includes an n-type nitride-based semiconductor layer, an active layer, a p-type nitride-based semiconductor layer, an ohmic contact layer covering a portion of the p-type nitride-based semiconductor layer upper surface, and a p electrode including a first portion contacting the p-type nitride-based semiconductor layer and a second portion contacting the ohmic contact layer.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-sub Kim, Jin-sub Lee, Cheol-soo Sone, Kyung-wook Hwang
  • Patent number: 9136425
    Abstract: A semiconductor light emitting element includes a first substrate, a stacked body, an electrode, and a conductive layer. The first substrate has a first face and a first side face. The first side face intersects the first face. The first substrate includes a plurality of conductive portions and a plurality of insulating portions arranged alternately. The stacked body is aligned with the first substrate. The stacked body includes first and second semiconductor layers and a light emitting layer. The electrode is electrically connected to the first semiconductor layer. The conductive layer is electrically connected to at least one of the conductive portions and the second semiconductor layer. At least one of the insulating portions is disposed between the first side face and a portion of the conductive layer nearest to the first side face.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Shigeya Kimura, Hiroshi Ono, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 9130069
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor layer. The method can include forming a first nitride semiconductor layer on a substrate in a reactor supplied with a first carrier gas and a first source gas. The first nitride semiconductor layer includes indium. The first carrier gas includes hydrogen supplied into the reactor at a first flow rate and includes nitrogen supplied into the reactor at a second flow rate. The first source gas includes indium and nitrogen and supplied into the reactor at a third flow rate. The first flow rate is not less than 0.07% and not more than 0.15% of a sum of the first flow rate, the second flow rate, and the third flow rate.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nago, Yoshiyuki Harada, Hisashi Yoshida, Shigeya Kimura, Shinya Nunoue
  • Patent number: 9130068
    Abstract: A method for forming a light emitting device comprises forming a buffer layer having a plurality of layers comprising a substrate, an aluminum gallium nitride layer adjacent to the substrate, and a gallium nitride layer adjacent to the aluminum gallium nitride layer. During the formation of each of the plurality of layers, one or more process parameters are selected such that an individual layer of the plurality of layers is strained.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 8, 2015
    Assignee: Manutius IP, Inc.
    Inventors: Long Yang, Will Fenwick
  • Patent number: 9123635
    Abstract: A manufacturing method of a semiconductor device includes the steps of: forming a first electrode layer on a n-type semiconductor layer; forming a second electrode layer on a p-type semiconductor layer; and performing heat treatment for the first electrode layer and the second electrode layer formed on the semiconductor layers. Temperature of the heat treatment is not lower than 400 degrees centigrade and not higher than 650 degrees centigrade.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 1, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Toru Oka, Nariaki Tanaka
  • Patent number: 9112116
    Abstract: A method for fabricating LED devices. The method includes providing a gallium and nitrogen containing substrate member (e.g., GaN) comprising a backside surface and a front side surface. The method includes subjecting the backside surface to a polishing process, causing a backside surface to be characterized by a surface roughness, subjecting the backside surface to an anisotropic etching process exposing various crystal planes to form a plurality of pyramid-like structures distributed spatially in a non-periodic manner on the backside surface, treating the backside surface comprising the plurality of pyramid-like structures, to a plasma species, and subjecting the backside surface to a surface treatment. The method further includes forming a contact material comprising an aluminum bearing species or a titanium bearing species overlying the surface-treated backside to form a plurality of LED devices with the contact material.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 18, 2015
    Assignee: Soraa, Inc.
    Inventors: Michael J. Cich, Kenneth John Thomson
  • Patent number: 9099649
    Abstract: Provided are an apparatus for manufacturing an OLED display and a method of manufacturing OLED display. According to another aspect of the present invention, there is provided the method of manufacturing an OLED display which includes placing a substrate having rows and columns of pixels through on a stage, ejecting organic light-emitting ink to the pixels through on the substrate by using a print head placed above the stage, and sequentially covering pixels through coated with the organic light-emitting ink with a cover plate placed above the stage.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: August 4, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jang Sub Kim, Geun Tak Kim, Hyea Weon Shin, Jae Kwon Hwang
  • Patent number: 9093605
    Abstract: An optoelectronic device comprises: a substrate having a first surface and a normal direction perpendicular to the first surface; a first semiconductor formed on the first surface of the substrate, comprising a plurality of hollow components formed in the first semiconductor layer; a first protection layer formed on a sidewall and a bottom wall of the plurality of the hollow components, and the bottom wall comprises a portion of the first surface; and a buffer layer formed on the first semiconductor layer wherein the buffer layer comprises a first surface and a second surface opposite to the first surface.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: July 28, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: De Shan Kuo, Tsun Kai Ko
  • Patent number: 9087932
    Abstract: A method for manufacturing a semiconductor light emitting device includes forming an isolation pattern on a semiconductor single crystal growth substrate. A first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer are sequentially grown in one chip unit region of the semiconductor single crystal growth substrate defined by the isolation pattern, and a reflective metal layer is formed to cover the light emitting structure and the isolation pattern. A support substrate is formed on the reflective metal layer, and the semiconductor single crystal growth substrate is removed from the light emitting structure. The support substrate is then cut into individual light emitting devices.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Hun Kim, Sung Joon Kim, Yong Il Kim, Yung Ho Ryu, Myeong Rak Son, Su Yeol Lee, Seung Hwan Lee, Tae Sung Jang, Su Min Hwangbo
  • Patent number: 9070837
    Abstract: A semiconductor light-emitting device includes: a laminated structure, a first electrode, a second electrode and a dielectric laminated film. The laminated structure includes, a first semiconductor layer, a second semiconductor layer, and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, in which the second semiconductor layer and the light-emitting layer are selectively removed and a part of the first semiconductor layer is exposed to a first main surface on the side of the second semiconductor layer.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: June 30, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Katsuno, Yasuo Ohba, Kei Kaneko, Mitsuhiro Kushibe
  • Patent number: 9070814
    Abstract: The sapphire substrate has a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device and comprising a plurality of projections of the principal surface, wherein an outer periphery of a bottom surface of each of the projections has at least one depression. This depression is in the horizontal direction. The plurality of projections are arranged so that a straight line passes through the inside of at least any one of projections when the straight line is drawn at any position in any direction in a plane including the bottom surfaces of the plurality of projections.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: June 30, 2015
    Assignee: NICHIA CORPORATION
    Inventors: Junya Narita, Takuya Okada, Yohei Wakai, Yoshiki Inoue, Naoya Sako, Katsuyoshi Kadan
  • Patent number: 9064798
    Abstract: An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: June 23, 2015
    Assignee: University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar, Islam A. Salama
  • Patent number: 9064996
    Abstract: The object of the present invention is to improve extraction efficiency of light of a Group III nitride-based compound semiconductor light-emitting device of a multiple quantum well structure. The device comprises a multiple quantum well structure comprising a well layer comprising a semiconductor including at least In for composition, a protective layer which comprises a semiconductor including at least Al and Ga for composition and has a band gap larger than a band gap of the well layer and is formed on and in contact with the well layer in a positive electrode side. And also the device comprises a barrier layer comprising a band gap which is larger than a band gap of the well layer and is smaller than a band gap of the protective layer, and formed on and in contact with the protective layer in a positive electrode side and a periodical structure of the well layer, the protective layer and the barrier layer.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: June 23, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Koji Okuno
  • Patent number: 9059012
    Abstract: An epitaxial wafer having a void for separation of a substrate and a semiconductor device fabricated using the same. The epitaxial wafer includes a substrate, a mask pattern disposed on the substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern. The epitaxial layer includes a void disposed on the masking region. The epitaxial layer can be separated from the growth substrate by applying chemical lift-off or stress lift-off, at the void.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: June 16, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Kyu Ho Lee, Chang Suk Han, Hwa Mok Kim, Daewoong Suh, Chi Hyun In, Jong Hyeon Chae
  • Patent number: 9054275
    Abstract: A light emitting diode includes an epitaxial substrate, an active layer, a tunneling layer, a current spreading layer, and an electrode unit. The active layer includes a first conductive type film, a quantum well structure, and a second conductive type film that is made from AlyInzGa(1-y-z)N, wherein 0<y<1, 0?z<1, and 0<(y+z)?1. The tunneling layer is stacked on the second conductive type film and is made from AlxIn1-xN, wherein 0<x<1 and x>y. The tunneling layer has a band gap greater than that of the second conductive film. The current spreading layer is stacked on the tunneling layer.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 9, 2015
    Assignee: National Chung-Hsing University
    Inventors: Dong-Sing Wuu, Ray-Hua Horng, Tsung-Yen Tsai
  • Patent number: 9054496
    Abstract: Provided are a wavelength swept vertical-cavity surface-emitting laser and a method of fabricating the same. The laser may include a substrate, a lower reflection layer on the substrate, an active layer on the lower reflection layer, a sacrificial layer disposed on a first side of the active layer, a stopper disposed on a second side of the active layer that may be spaced apart from the sacrificial layer, and an upper reflection layer fixed on the sacrificial layer, the upper reflection layer extending over the stopper and the active layer. The stopper defines a minimum separation distance between the upper reflection layer and the active layer.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 9, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Hyun Woo Song
  • Publication number: 20150144869
    Abstract: Group-III nitride structure comprising at least one structure pyramid having a base having at least four sides. The structure pyramid comprises an inner pyramid having a base having at least four sides, which inner pyramid is made of a first group-III nitride. The inner pyramid is coated with an inner first layer made of a second group-III nitride and an outer second layer made of a third group-III nitride, wherein the second group-III nitride has a lower band gap than the first group-III nitride and a lower band gap than the third group-III nitride. The base of the structure pyramid is elongated resulting in an upper ridge creating at least one anisotropic quantum dot.
    Type: Application
    Filed: June 26, 2013
    Publication date: May 28, 2015
    Inventors: Anders Lundskog, Chih-Wei Hsu, Fredrik Karlsson
  • Publication number: 20150144914
    Abstract: Provided is a display device, including a pixel electrode in each of a plurality of pixels; an auxiliary wiring part including a first auxiliary wiring having a first edge portion, and a second auxiliary wiring having a second edge portion spaced apart from and facing the first edge portion; an insulating layer on the pixel electrode and the auxiliary wiring part, and in which a first opening and a second opening are defined, the first opening overlapping the pixel electrode, and the second opening overlapping the first edge portion and the second edge portion; an organic light-emitting layer on the insulating layer and contacting the pixel electrode through the first opening; and an upper electrode on the organic light-emitting layer and having a connection portion electrically connected with the auxiliary wiring part through the second opening.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 28, 2015
    Inventors: Mitsuhiro KASHIWABARA, Toshiyuki MATSUURA
  • Publication number: 20150147840
    Abstract: Provided is a 5,6-diaryl-2-pyrazyl triflate, its synthetic method, and a method for synthesizing an organometallic complex having a triarylpyrazine ligand from the 5,6-diaryl-2-pyrazyl triflate. The triflate is readily obtained from the corresponding 5,6-diarylpyrazin-2-ol, and the palladium-catalyzed coupling of the 5,6-diaryl-2-pyrazyl triflate with an arylboronic acid derivative leads to a high yield of a triarylpyrazine derivative having high purity. The use of the triarylpyrazine derivative in the reaction with a metal compound such as a metal chloride results in an ortho-metallated organometallic complex with high purity. The high purity of the organometallic complex contributes to the extremely high durability of a light-emitting element.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventors: Hideko Inoue, Tomohiro Kubota, Miki Kanamoto
  • Publication number: 20150147839
    Abstract: A method for manufacturing a semiconductor device may include: forming a metal layer structure over a semiconductor workpiece; forming a first layer over the metal layer structure, the first layer including a first material; forming at least one opening in the first layer and the metal layer structure; depositing a second layer to fill the at least one opening and at least partially cover a surface of the first layer facing away from the metal layer structure, the second layer including a second material that is different from the first material; removing the second layer from at least the surface of the first layer facing away from the metal layer structure; and removing the first layer.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Infineon Technologies Dresden GmbH
    Inventors: Alessia Scire, Alfred Vater, Mirko Vogt, Momtchil Stavrev, Tarja Hauck, Bee Kim Hong, Heiko Estel
  • Publication number: 20150144956
    Abstract: Provided is a self-supporting gallium nitride substrate useful as an alternative material for a gallium nitride single crystal substrate, which is inexpensive and also suitable for having a large area. This substrate is composed of a plate composed of gallium nitride-based single crystal grains, wherein the plate has a single crystal structure in the approximately normal direction. This substrate can be manufactured by a method comprising providing an oriented polycrystalline sintered body; forming a seed crystal layer composed of gallium nitride on the sintered body so that the seed crystal layer has crystal orientation mostly in conformity with the crystal orientation of the sintered body; forming a layer with a thickness of 20 ?m or greater composed of gallium nitride-based crystals on the seed crystal layer so that the layer has crystal orientation mostly in conformity with crystal orientation of the seed crystal layer; and removing the sintered body.
    Type: Application
    Filed: September 29, 2014
    Publication date: May 28, 2015
    Inventors: Morimichi WATANABE, Jun YOSHIKAWA, Tsutomu NANATAKI, Katsuhiro IMAI, Tomohiko SUGIYAMA, Takashi YOSHINO, Yukihisa TAKEUCHI, Kei SATO
  • Patent number: 9040332
    Abstract: A submount for a light emitting stack includes a substrate and a metallization layer having circuit traces and a planar dielectric layer that fills regions between the circuit traces. The planar dielectric layer serves to minimize the amount of light lost/absorbed by the substrate and preferably reflects the internally reflected light back toward the desired light output element. To facilitate efficient manufacture, a dielectric paste is applied over the metallized layer, then planed to expose at least portions of the metal conductors for the subsequent coupling to the light emitting stack. Pedestal elements are preferably provided at select locations on the circuit traces to facilitate this coupling while allowing the remainder of the circuit traces to be covered with the dielectric layer.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: May 26, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Brendan Moran, Jeffrey Kmetec, Iain Black, Frederic Diana, Serge Laurent Rudaz, Li Zhang
  • Patent number: 9041027
    Abstract: A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 26, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Aaron Joseph Ptak, Yong Lin, Andrew Norman, Kirstin Alberi
  • Patent number: 9041005
    Abstract: Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Lifang Xu, Scott D. Schellhammer, Thomas Gehrke, Zaiyuan Ren, Anton J. De Villiers
  • Patent number: 9040319
    Abstract: A group-III nitride compound semiconductor light-emitting device, a method of manufacturing the group-III nitride compound semiconductor light-emitting device, and a lamp. The method includes the steps of: forming an intermediate layer (12) made of a group-III nitride compound on a substrate (11) by activating and reacting gas including a group-V element with a metal material in plasma; and sequentially forming an n-type semiconductor layer (14), a light-emitting layer (15), and a p-type semiconductor layer (16) each made of a group-III nitride compound semiconductor on the intermediate layer (12). Nitrogen is used as the group-V element, and the thickness of the intermediate layer (12) is in the range of 20 to 80 nm.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 26, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Patent number: 9040965
    Abstract: A donor substrate includes a base layer having a first surface and a second surface, a complementary hardness layer on the first surface of the base layer, and a transfer layer on the complementary hardness layer. A hardness of the complementary hardness layer is greater than that of the base layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young Gil Kwon, Hyung Tag Lim
  • Publication number: 20150137087
    Abstract: An organic light-emitting element including: a substrate; a light-emitting part above the substrate, the light-emitting part including an organic layer; and banks defining bounds of the organic layer in a direction along a main surface of the substrate. In the organic light-emitting element, in plan view, a surface of the organic layer is longer in a first direction than in a second direction perpendicular to the first direction, and in the second direction, the surface of the organic layer is convex, protruding upwards in a thickness direction of the organic layer, and in the first direction, the surface of the organic layer is concave, protruding downwards in the thickness direction.
    Type: Application
    Filed: September 26, 2012
    Publication date: May 21, 2015
    Applicant: PANASONIC CORPORATION
    Inventor: Tsuyoshi Yamamoto