Abstract: A cell plate electrode is shared between storage capacitors of memory cells incorporated in a semiconductor dynamic random access memory device of the type having the storage capacitors over bit lines, and slits are formed in the cell plate electrode in such a manner that the boundaries between channel regions and gate oxide layers are horizontally spaced from the outer periphery of the cell plate electrode and the slits by distances equal to or less than a critical distance determined on the basis of a diffusion length of hydrogen in an inter-level insulating layer, thereby causing the hydrogen to surely reach the boundaries for reducing the density of surface state.

Abstract: Disclosed herein is a cleaning process for a substrate surface on which a high-density film and a low-density film lower in density than the high-density film are carried in combination. According to the cleaning process, a mixed gas of anhydrous hydrogen fluoride gas and a heated inert gas is brought into contact with the substrate surface such that at least a portion of the low-density film is removed without impairing the high-density film beyond a tolerance. The substrate is, for example, a semiconductor substrate.

Abstract: It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped impurity regions are formed. A coating mainly made of silicon is formed on the entire surface including the surface of the gate electrode. Side walls mainly made of silicon are formed on the side faces of the gate electrode by anisotropically or semi-anisotropically etching the thus-formed coating in an atmosphere of ClF3, for instance. In this etching step, since a selective etching ratio of the side walls to the gate insulating film is sufficiently large, etching of the gate insulating film is negligible. A source and a drain are then formed by doping an impurity at a high concentration using the gate electrode and the side walls as a mask.

Abstract: A method of manufacturing a semiconductor device has a step whereby, when forming a gate oxide film, a thin oxide film is left on a silicon substrate onto which it is formed and whereby a heavy metal at the surface of the silicon substrate is diffused into the substrate, and a step of forming a gate oxide film onto the silicon substrate.

Abstract: A semiconductor manufacturing system includes a getter-based gas purifier coupled in flow communication with a gas distribution network for a semiconductor fabrication facility. The gas distribution network supplies purified gas to at least one wafer processing chamber in the semiconductor fabrication facility. The gas purifier includes a getter column having a metallic vessel with an inlet, an outlet, and a containment wall extending between the inlet and the outlet. Getter material which purifies gas flowing therethrough by sorbing impurities therefrom is disposed in the vessel. A first temperature sensor is disposed in a top portion of the getter material. The first temperature sensor is located in a melt zone to detect rapidly the onset of an exothermic reaction which indicates the presence of excess impurities in the incoming gas to be purified. A second temperature sensor is disposed in a bottom portion of the getter material.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film is formed in this step. At this time, gettering of the nickel element into the thermal oxide film takes place. Then, the thermal oxide film is removed. Thereby, a crystal silicon film having low concentration of the metal element and a high crystalinity can be obtained.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to establish a vacancy concentration profile within the wafer. The oxidized wafer is then cooled from the temperature of said oxidizing heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.

Abstract: A method for analyzing impurities within a silicon wafer in a convenient and simple manner with high accuracy and sensitivity. In a first example 1, a silicon wafer is subjected on its surface to a sandblasting process with use of powder of SiO2 and then to a thermal oxidation process in a dry-oxygen gas atmosphere to easily move impurities present within the silicon wafer into a distorted layer and to form a thermal oxide film and a surface layer of the wafer positioned directly therebelow and containing the distorted layer. The thermal oxide film or the surface layer containing the distorted layer is dissolved with, e.g., a solution of hydrofluoric acid to recover and analyze the dissolved solution. In a comparative example 1, the same processes as in the example 1 are carried out to analyze a predetermined solution, except that the sandblasting process is omitted.

Abstract: A process for significantly reducing the thickness of and improving the quality and uniformity of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process. The native oxide forms on exposed silicon surfaces after selectively etching away regions of a first thicker gate oxide and prior to growing a thinner gate oxide. The thinner gate oxide used to form high performance devices is between about 15 and 50 Å thick. The native oxide which forms on the exposed silicon surfaces has an initial thickness of about 10 Å. After the selective regions have been patterned the wafer is cleaned using a totally HF free cleaning procedure and subjected to a low pressure rapid thermal annealing between about 600 and 1,050° C. in an ambient of H2 and N2. The residual oxide thickness is reduced to about 4 Å with an accompanying improvement in thickness uniformity and oxide quality.

Abstract: The present invention relates to a method of cleaning a surface of a substrate employed prior to film formation by using the CVD method which uses a reaction gas containing an ozone containing gas which contains ozone (O.sub.3) in oxygen (O.sub.2) and tetraethylorthosilicate (TEOS). The substrate surface cleaning method comprises the steps of oxidizing particles 13 by contacting a pre-process gas containing ozone 15 to a surface 12 of a substrate 11 on which the particles 13 are present, and removing the particles 13 by heating the substrate 11 to exceed a decomposition point of oxide 13a of the particles 13.

Abstract: A process for removing a Group I or Group II metal species from a surface of a semiconductor substrate. The process comprises exposing the surface to a gaseous reactant mixture comprising HF, a second compound and a silane compound, and removing volatile products from the surface. The invention is further directed to a process for etching oxides from a semiconductor substrate comprising exposing the surface to a gaseous reactant mixture comprising HF, a second compound and a silane compound, and removing volatile products from the surface.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Abstract: Fluorination can be used to neutralize transition metal impurities in Si. Fluorine is incorporated into the near-surface region of Si by implantation or annealing in a fluorine containing ambient. Thermal treatments at appropriate temperatures are used to initiate the interdiffusion and reaction between fluorine and metal contaminants. The impurities readily react with fluorine to form a compound or complex, thus significantly reducing the number of mid-gap impurities.

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: In a method of manufacturing a semiconductor device, a first heat treatment for crystallization is conducted after nickel elements are introduced in an amorphous silicon film. Then, after the crystalline silicon film is obtained, a heat treatment is again conducted through the heating method which is identical with the first heat treatment. In this state, HCl or the like is added to the atmosphere to conduct gettering of the nickel elements remaining in the crystalline silicon film. With this process, there can be obtained a crystalline silicon film low in the concentration of the metal elements and high in crystallinity.

Abstract: It is intended to provide a method of forming a gate overlap lightly doped impurity region (GOLD). After a gate insulating film is formed by a material mainly made of silicon oxide and a gate electrode is formed with, for instance, silicon, lightly doped impurity regions are formed. A coating mainly made of silicon is formed on the entire surface including the surface of the gate electrode. Side walls mainly made of silicon are formed on the side faces of the gate electrode by anisotropically or semi-anisotropically etching the thus-formed coating in an atmosphere of ClF.sub.3, for instance. In this etching step, since a selective etching ratio of the side walls to the gate insulating film is sufficiently large, etching of the gate insulating film is negligible. A source and a drain are then formed by doping an impurity at a high concentration using the gate electrode and the side walls as a mask.