Abstract: A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.

Abstract: A method of manufacturing a nanostructure semiconductor light emitting device including providing a base layer formed of a first conductivity type semiconductor. A mask including an etch stop layer is formed on the base layer. A plurality of openings are formed in the mask so as to expose regions of. A plurality of nanocores are formed by growing the first conductivity type semiconductor on the exposed regions of the base layer to fill the plurality of openings. The mask is partially removed by using the etch stop layer to expose side portions of the plurality of nanocores. An active layer and a second conductivity type semiconductor layer are sequentially grown on surfaces of the plurality of nanocores.

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Abstract: Photovoltaic thin-film materials comprising crystalline tin sulfide alloys of the general formula Sn1-x(R)xS, where R is selected from magnesium, calcium and strontium, as well as methods of producing the same, are disclosed.

Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four ? atoms and hexa-coordinated Al atoms each surrounded by six ? atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.

Abstract: A retinal prosthesis system can comprise: a flexible substrate; a nanowire light detector which is placed on the substrate, and comprises one or more nanowires of which the resistance changes according to the applied light; one or more micro-electrodes which are placed on the substrate, are electrically connected to the nanowire light detector, and come in contact with retinal cells; and an electric power supply source for applying electric power to the nanowire light detector and the micro-electrodes. The retinal prosthesis system can be implemented into a very thin and flexible substrate type high resolution retinal system by manufacturing a nanowire light detector on a substrate in which micro-electrodes are implemented.

Abstract: Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphization of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphization of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallization of the source and drain blocks such that the second semiconducting material i

Abstract: A substrate having a native oxide film formed on its surface is heated in a hydrogen atmosphere to reduce silicon dioxide to hydrogen. Additionally, silicon near an interface between the native oxide film and the substrate is hydrogen-terminated. A hydrogen-introduced layer containing silicon bonded with hydrogen is accordingly formed on the substrate surface. A dopant solution is supplied to the substrate surface having the hydrogen-introduced layer formed thereon, and hydrogen in the hydrogen-introduced layer is replaced with a dopant, thereby introducing the dopant into the substrate surface. A relatively large thickness of the hydrogen-introduced layer formed through the reduction of the native oxide film allows the dopant to be uniformly introduced into the substrate surface for a required depth. A flashing light is emitted to the substrate surface containing the introduced dopant, activating the dopant.

Abstract: A sublimation grown SiC single crystal includes vanadium dopant incorporated into the SiC single crystal structure via introduction of a gaseous vanadium compound into a growth environment of the SiC single crystal during growth of the SiC single crystal.

Abstract: Merged fin structures for finFET devices and methods of manufacture are disclosed. The method of forming the structure includes forming a plurality of fin structures on an insulator layer. The method further includes forming a faceted structure on adjacent fin structures of the plurality of fin structures. The method further includes spanning a gap between the faceted structures on the adjacent fin structures with a semiconductor material.

Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

Abstract: A method for forming a contact region for a solar cell is disclosed. The method includes depositing a paste composed of a first metal above a substrate of the solar cell, curing the paste to form a first metal layer, electrolessly plating a second metal layer on the first metal layer and electrolytically plating a third metal layer on the second metal layer, where the second metal layer electrically couples the first metal layer to the third metal layer. The method can further include electrolytically plating a fourth metal layer on the third metal layer.

Abstract: Methods of forming semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less. The method includes forming a group III-V material over the group III material.

Abstract: A semiconductor light emitting diode comprising: a support substrate; an intermediate layer including an intermediate electrode portion, a second conductive semiconductor layer, an active layer, a first conductive semiconductor layer and an upper electrode portion sequentially disposed on the upper surface side of the support substrate in this order; and a lower electrode layer provided on the lower surface side of the support substrate, wherein: the intermediate layer has at least one intermediate electrode portion extending linearly or in an island-like shape; and the upper electrode portion and the intermediate electrode portion are disposed, in a view obtained by projecting these electrode portions, on an imaginary plane in parallel with the upper surface of the support substrate, respectively, in a positional relationship that these electrode portions, are offset from each other.

Abstract: An ohmic electrode (6) of a silicon carbide semiconductor apparatus is fabricated by forming an ohmic metal film on a silicon carbide substrate (1) by sputtering a target including a mixture or an alloy having therein nickel, and a metal(s) reducing the magnetic permeability of nickel and producing a carbide, where compositional ratios of the mixture or alloy are adjusted to predetermined compositional ratios, and by executing heat treatment for the ohmic metal film to calcinate the ohmic metal film. Thus, the ohmic electrode (6) that is for the silicon carbide semiconductor apparatus and capable of improving the use efficiency of the target can be manufactured, whose film thickness is even and that does not peel off.

Abstract: An object of the present invention is to provide an epitaxial growth apparatus and an epitaxial growth method that can suppress variation in in-face temperature of a semiconductor wafer caused by deflection of a susceptor and manufacture an epitaxial wafers of high quality. Specifically, the present invention provides an epitaxial growth apparatus for forming an epitaxial film on a semiconductor wafer placed in a chamber having a supply port and an exhaust port for a treatment gas, the apparatus comprising: a susceptor for placing the semiconductor wafer thereon within the chamber; and a susceptor support shaft for supporting the susceptor at an underneath portion of the susceptor, wherein the susceptor support shaft has a support column located substantially coaxial with the center of the susceptor, and at least four support arms extending radially from the top end of the support column with equal intervals therebetween.

Abstract: A semiconductor apparatus includes a semiconductor substrate that has a diameter of 2 inches or larger, and an N-type semiconductor layer that is stacked on the semiconductor substrate using a material including gallium nitride (GaN). A median of a plurality of measured values of the concentration of carbon (C) at a plurality of locations on a face of a region of the N-type semiconductor layer is equal to or lower than 1.0×1016 cm?3. The maximum value in difference between the median and the other measured values is lower than 5×1015 cm?3.

Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.

Abstract: Lattice-mismatched semiconductor devices having a substrate, a first epitaxial film disposed thereon, a dielectric material, and a second epitaxial film. The first epitaxial film contains etch pits that extend from the outer surface of the first epitaxial film into the first epitaxial film. The dielectric material is disposed within the etch pits and blocks at least some of the threading dislocations in the first epitaxial film from propagating into the second epitaxial film. Semiconductor devices containing a silicon (Si) substrate or a silicon germanium (SiGe) substrate, a germanium (Ge) film disposed over the substrate, and a dielectric material. Methods for producing such semiconductor devices.

Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate.

Abstract: A metamaterial includes a first continuous layer formed with a first material by atomic layer deposition (ALD), a first non-continuous layer formed with a second material by ALD on first upper surface portions of a first upper surface of the first continuous layer, and a second continuous layer formed with the first material by ALD on second upper surface portions of the first upper surface of the first continuous layer and on a second upper surface of the first non-continuous layer.

Abstract: A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×1018 cm?3 and the dislocation density in the III-N semiconductor layer is less than 2×109 cm?2.

Abstract: A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5×1018 cm?3 and the dislocation density in the III-N semiconductor layer is less than 2×109 cm?2.

Abstract: Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat.

Abstract: Method for manufacturing at least one semiconductor structure (130) on the surface (105) of a substrate (100) wherein the surface comprises silicon. The method comprises steps consisting of providing the substrate (100), forming in contact with an area (101) of the surface (105), referred to as the formation area, a layer (120) of a first material, the remainder (102) of the surface (105), referred to as the free area, remaining free from the first material, the dimensions of the formation area (101) and the first material being suitable for forming the structure (130), the first material comprising gallium, the formation of said layer (120) taking place at a temperature less than 600° C., and forming the structure (130) in contact with the layer (120).

Abstract: Exemplary embodiments of the present invention provide a method of fabricating a semiconductor substrate, the method including growing a first compound semiconductor layer on a first surface of a substrate, etching the first compound semiconductor layer using HF, KOH, or NaOH to roughen a first surface of the first compound semiconductor layer, forming cavities in the first compound semiconductor layer, separating the first compound semiconductor layer from the first surface of the substrate, flattening the first surface of the substrate after separating the first compound semiconductor layer, and growing a second compound semiconductor layer on the flattened first surface of the substrate.

Abstract: A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×105 cm?2. Thus, a silicon carbide semiconductor substrate enabling improved yield of semiconductor devices can be provided.

Abstract: A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.

Abstract: A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract: A method for forming a backside illuminated photo-sensitive device includes forming a gradated sacrificial buffer layer onto a sacrificial substrate, forming a uniform layer onto the gradated sacrificial buffer layer, forming a second gradated buffer layer onto the uniform layer, forming a silicon layer onto the second gradated buffer layer, bonding a device layer to the silicon layer, and removing the gradated sacrificial buffer layer and the sacrificial substrate.

Abstract: A production method of aluminum based group III nitride single crystal includes a reaction step, wherein a halogenated gas and an aluminum contact at 300° C. or more to 700° C. or less, producing a mixed gas including an aluminum trihalide gas and an aluminum monohalide gas; a converting step, wherein the aluminum monohalide gas is converted to a solid by setting a temperature of the mixed gas equal to or higher than a temperature to which a solid aluminum trihalide deposit, and lower by 50° C. or more than a temperature to which halogenated gas and aluminum contact in the reaction step; a separation step, wherein the aluminum trihalide gas is removed; and a crystal growth step, wherein the aluminum trihalide gas is used for an aluminum based group III nitride single crystal raw material, keeping its temperature equal to or higher than a temperature of the converting step.

Abstract: Systems and methods for MBE growing of group-III Nitride alloys, comprising establishing an average reaction temperature range from about 250 C to about 850 C; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source. Produced alloys include AlN, InN, GaN, InGaN, and AlInGaN.

Abstract: A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.

Abstract: A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.

Abstract: A nanopillar photonic crystal laser includes a plurality of nanopillars and a support structure in contact with at least a portion of each of the nanopillars. Each nanopillar has an axial dimension and two mutually orthogonal cross dimensions. The axial dimension of each of the nanopillars is greater than the two mutually orthogonal cross dimensions, where there mutually orthogonal cross dimensions are less than about 1 ?m and greater than about 1 nm. The support structure holds the plurality of nanopillars in preselected relative orientations and displacements relative to each other to form an array pattern that confines light of a preselected wavelength to a resonance region that intercepts at least one nanopillar of the plurality of nanopillars. The at least one nanopillar includes a lasing material to provide an output laser beam of light at the preselected wavelength.

Abstract: Fabrication method. At least first and second hardmasks are deposited on a substrate, the thickness and materials of the first and second hardmask selected to provided etch selectivity with respect to the substrate. A nanoscale pattern of photoresist is created on the first hardmask and the hardmask is etched through to create the nanoscale pattern on a second hardmask. The second hardmask is etched through to create the desired taper nanocone structures in the substrate. Reactive ion etching is preferred. A glass manufacturing process using a roller imprint module is also disclosed.

Abstract: The present invention relates to a method for preparing a CIS- or CIGS-based light-absorbing layer which is included in a thin film solar cell. More particularly, the present invention relates to a method for preparing a CIS- or CIGS-based light-absorbing layer which ultimately improves the efficiency of a solar cell since the remaining carbon impurities in the formed light-absorbing layer are minimized and additional sulfurization treatment or selenium treatment is made optional, not requisite.

Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.

Abstract: Disclosed is that a method of manufacturing horizontally aligned single crystalline inorganic nanowire patterns, including mixing an inorganic precursor and an organic polymer in water or an organic solvent to prepare an inorganic-polymer liquid, forming inorganic precursor/organic polymer composite nanowire patterns aligned on a substrate using the inorganic-polymer liquid, and irradiating eximer laser along the aligned inorganic precursor/organic polymer composite nanowire patterns.

Abstract: A semiconductor device is disclosed. The device includes a plurality of gates formed on a surface of a substrate, a plurality of sidewalls formed on side surfaces of the gates, a Sigma-shaped recess formed in the substrate between adjacent gates, a SiGe seed layer formed on an inner surface of the Sigma-shaped recess, boron-doped bulk SiGe formed on a surface of the SiGe seed layer, with the boron-doped bulk SiGe filling the Sigma-shaped recess, and a boron-doped SiGe regeneration layer formed in a first recess beneath the surface of the substrate. The first recess is formed by etching a portion of the SiGe seed layer and the boron-doped bulk SiGe in the Sigma-shaped recess, and the boron-doped SiGe regeneration layer has a higher concentration of boron than the SiGe seed layer or the boron-doped bulk SiGe.

Abstract: A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate.

Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Abstract: The present invention relates to a method for manufacturing a semiconductor device by wet-process chemical etching, the device comprising at least one layer of silicon (Si) and at least one layer of silicon-germanium (SiGe) and at least one layer of photosensitive resin forming a mask partly covering the layer of silicon-germanium (SiGe) and leaving the layer of silicon-germanium uncovered in certain zones, characterized in that it comprises a step of preparation of an etching solution, having a pH between 3 and 6, from hydrofluoric acid (HF), hydrogen peroxide (H2O2), acetic acid (CH3COOH) and ammonia (NH4OH), and a step of stripping of the layer of silicon-germanium (SiGe) at least at the said zones by exposure to the said etching solution. The invention will be applicable for the manufacture of integrated circuits and more precisely of transistors. In particular, for optimization of CMOS transistors of the latest generation.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.

Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A p-type region, a p? type region, and a p+ type region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type region and the p? type region are disposed in a breakdown voltage structure portion that surrounds an active region. The p+ type region is disposed in the active region to make up a JBS structure. The p? type region surrounds the p-type region to make up a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the p-type region and this overhanging portion acts as a field plate. The p+ type region has an acceptor concentration greater than or equal to a predetermined concentration and can make a forward surge current larger.

Abstract: A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.