On Insulating Substrate Or Layer Patents (Class 438/479)
  • Publication number: 20150144884
    Abstract: A reliable graphene film that provides complete semiconductive properties without mixing of metallic properties, redacts an off current, achieves a high current on/off ratio of 105 or more sufficient for practical use, and prevents variations in electric properties is obtained. In a grapheme film 3, a plurality of ribbon-shaped graphenes 3a having a longitudinal edge structure of as arm chair type constitute a network structure, and the grapheme 3a includes three or more six-membered rings of carbon atoms bonded in parallel in a short direction and has a width of 0.7 nm or more.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Junichi YAMAGUCHI, Shintaro SATO
  • Patent number: 9040391
    Abstract: The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with germanium, the concentration of germanium in the layer of silicon oxide being such that it lowers the flow temperature of the layer of silicon oxide below the oxidation temperature allowing germanium condensation of the SiGe layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 26, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Jean-François Damlencourt, Benjamin Vincent
  • Patent number: 9040981
    Abstract: Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9041105
    Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Qizhi Liu, Robert M. Rassel, Yun Shi
  • Patent number: 9040384
    Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Hongning Yang, Jiang-Kai Zuo
  • Publication number: 20150140792
    Abstract: A method for depositing a Group III nitride semiconductor film on a substrate is provided that comprises: providing a sapphire substrate; placing the substrate in a vacuum chamber; conditioning a surface of the substrate by etching and providing a conditioned surface; holding the substrate away from a substrate facing surface of a heater by a predetermined distance; heating the substrate to a temperature by using the heater whilst the substrate is held away from the substrate facing surface of the heater, and depositing a Group III nitride semiconductor film onto the conditioned surface of the substrate by a physical vapour deposition method whilst the substrate is held away from the substrate facing surface of the heater and forming an epitaxial Group III nitride semiconductor film with N-face polarity on the conditioned surface of the substrate.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Inventors: Lorenzo Castaldi, Martin Kratzer, Heinz Felzer, Robert Mamazza, JR.
  • Patent number: 9035383
    Abstract: A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 9029246
    Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
  • Publication number: 20150125976
    Abstract: A method of producing a bulk semiconductor material comprises the steps of providing a base comprising a substantially planar substrate having a plurality of etched nano/micro-structures located thereon, each structure having an etched, substantially planar sidewall, wherein the plane of each said etched sidewall is arranged at an oblique angle to the substrate, and selectively growing the bulk semiconductor material onto the etched sidewall of each nano/micro-structure using an epitaxial growth process. A layered semiconductor device may be grown onto the bulk semiconductor material.
    Type: Application
    Filed: June 7, 2013
    Publication date: May 7, 2015
    Inventor: Wang Nang Wang
  • Patent number: 9024331
    Abstract: Disclosed is a semiconductor light emitting element (LC) provided with a substrate (110) having one surface on which plural hexagonal-pyramid-shaped protrusions (110b) are provided, a base layer (130) provided so as to be in contact with the surface on which the protrusions (110b) are provided, an n-type semiconductor layer (140) provided so as to be in contact with the base layer (130), a light emitting layer (150) provided so as to be in contact with the n-type semiconductor layer (140), and a p-type semiconductor layer (160) provided so as to be in contact with the light emitting layer (150). Each protrusion (110b) scatters light in lateral and oblique directions within the semiconductor light emitting element (LC). The protrusions are densely arranged on a substrate on which semiconductor layers are laminated, so that the light extraction efficiency is improved.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: May 5, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yohei Sakano
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
  • Publication number: 20150115480
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 30, 2015
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • Publication number: 20150115416
    Abstract: A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried oxide (BOX) layer is disclosed. The semiconductor device includes a semiconductor stack structure with a first surface and a second surface wherein the second surface is on an opposite side of the semiconductor stack structure from the first surface. At least one device terminal is included in the semiconductor stack structure and at least one electrical contact extends from the second surface and is electrically coupled to the at least one device terminal. The semiconductor stack is protected by a polymer disposed on the first surface of the semiconductor stack. The polymer has high thermal conductivity and high electrical resistivity.
    Type: Application
    Filed: October 31, 2014
    Publication date: April 30, 2015
    Inventors: Julio C. Costa, David M. Shuttleworth, Michael J. Antonell
  • Publication number: 20150118830
    Abstract: The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate (10) including a support substrate (11) dissoluble in hydrofluoric acid and a single crystal film (13) arranged on a side of a main surface (11m) of the support substrate (11), a coefficient of thermal expansion in the main surface (11m) of the support substrate (11) being more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal, forming a GaN-based film (20) on a main surface (13m) of the single crystal film (13) arranged on the side of the main surface (11m) of the support substrate (11), and removing the support substrate (11) by dissolving the support substrate (11) in hydrofluoric acid. Thus, the method of manufacturing a GaN-based film capable of efficiently obtaining a GaN-based film having a large main surface area, less warpage, and good crystallinity, as well as a composite substrate used therefor are provided.
    Type: Application
    Filed: January 5, 2015
    Publication date: April 30, 2015
    Inventors: Issei SATOH, Yuki SEKI, Koji UEMATSU, Yoshiyuki YAMAMOTO, Hideki MATSUBARA, Shinsuke FUJIWARA, Masashi YOSHIMURA
  • Patent number: 9018052
    Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9018081
    Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
    Type: Grant
    Filed: November 23, 2013
    Date of Patent: April 28, 2015
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
  • Publication number: 20150108616
    Abstract: A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Brian J. Greene, Augustin J. Hong, Byeong Y. Kim, Dan M. Mocuta
  • Patent number: 9012309
    Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 21, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung
  • Patent number: 9012912
    Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Publication number: 20150102470
    Abstract: Presented herein is a method for forming a semiconductor film using an adhesion layer, comprising providing an oxide layer disposed over a substrate, forming at least one adhesion layer over the oxide layer, and forming a film layer over the at least one adhesion layer in a same process step as the forming the at least one adhesion layer. Forming the at least one adhesion layer further comprises at least forming a first adhesion layer over the oxide layer and forming a second adhesion layer over the first adhesion layer. Forming the first adhesion layer comprises providing the terminating gas at a substantially constant first flow rate, and wherein the forming the second adhesion layer comprises ramping a flow rate of the terminating gas to a zero flow rate from the first flow rate.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Liao, Chun-Heng Chen, Sheng-Po Wu, Ming-Feng Hsieh, Hongfa Luan
  • Publication number: 20150102412
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: PIERRE MORIN, Qing Liu, Nicolas Loubet
  • Patent number: 9006087
    Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 9006083
    Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 14, 2015
    Inventor: Ananda H. Kumar
  • Patent number: 9006086
    Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 14, 2015
    Inventors: Chien-Min Sung, Ming-Chi Kan, Shao Chung Hu
  • Patent number: 9006785
    Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Jung-Hun Seo, Max G. Lagally
  • Publication number: 20150097270
    Abstract: A method of forming a semiconductor structure includes forming a first fin in a p-FET device region of a semiconductor substrate and a second fin in an n-FET device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each comprise a strained semiconductor material. Next, the second fin is amorphized to form a relaxed fin by implanting ions into the second fin while protecting the first fin.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Dominic J. Schepis, Matthew W. Stoker
  • Publication number: 20150097217
    Abstract: A semiconductor device includes a semiconductor substrate and attenuated semiconductor fins (e.g. FinFET fins) that include an outer portion that is a composite of a first material and a second material, an inner portion that is the second material, and an attenuation portion that is an attenuated composite of the first and second materials. The attenuation portion may be formed by diffusing the first material into a plurality of fins made of the second material. The attenuated composite attenuates from a first composite to a second composite, the first composite comprising a majority of the first material, the second composite comprising a majority of the second material. The outer portion may be located on the fin perimeter and the inner portion may be located central to the fin. The first material may be Germanium, the second material may be Silicon, and the attenuated composite may be attenuated Silicon Germanium.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Jinghong Li, Alexander Reznicek
  • Patent number: 8999751
    Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Patent number: 8999861
    Abstract: A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 7, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance Scudder, Pushkar Ranade, Charles Stager, Lucian Shifren, Dalong Zhao, U.C. Sridharan, Michael Duane
  • Publication number: 20150093884
    Abstract: Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.
    Type: Application
    Filed: April 22, 2014
    Publication date: April 2, 2015
    Inventors: Wei-E Wang, Mark S. Rodder, Robert C. Bowen
  • Publication number: 20150091010
    Abstract: A method for forming low-temperature polysilicon thin film, a thin film transistor and a display device are provided. The method for forming low-temperature polysilicon thin film comprises: depositing an amorphous silicon thin film on a base substrate; covering the amorphous silicon thin film with an anti-reflective optical film; performing photolithography and etching on the anti-reflective optical film such that light condensing structures are provided in an array on the anti-reflective optical film; and irradiating the amorphous silicon thin film with the anti-reflective optical film covered by laser light such that the amorphous silicon film is converted into the low-temperature polysilicon thin film.
    Type: Application
    Filed: December 10, 2013
    Publication date: April 2, 2015
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Wang, Xueyan Tian, Jang Soon Im
  • Patent number: 8993418
    Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 31, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Vincent Destefanis, Nicolas Loubet
  • Patent number: 8994019
    Abstract: The invention is to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics of a transistor, and to provide a highly reliable semiconductor device. In a transistor in which a semiconductor layer, a source and drain electrode layers, a gate insulating film, and a gate electrode are sequentially stacked, a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen is used as the semiconductor layer. The Group 3 element functions as a stabilizer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20150084002
    Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Applicant: HRL LABORATORIES LLC
    Inventors: Hyok J. SONG, James H. Schaffner, Jeong-Sun Moon, Kyung-Ah Son
  • Patent number: 8987119
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 24, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Publication number: 20150076558
    Abstract: The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: YI-JING LEE, CHENG-HSIEN WU, CHIH-HSIN KO, CLEMENT HSINGJEN WANN
  • Publication number: 20150076507
    Abstract: An epitaxy substrate (11, 12, 13) for a nitride compound semiconductor material is specified, which has a nucleation layer (2) directly on a substrate (1) wherein the nucleation layer (2) has at least one first layer (21) composed of AlON with a column structure. A method for producing an epitaxy substrate and an optoelectronic semiconductor chip comprising an epitaxy substrate are furthermore specified.
    Type: Application
    Filed: April 24, 2013
    Publication date: March 19, 2015
    Applicant: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Joachim Hertkorn, Alexander Frey, Christian Schmid
  • Publication number: 20150079770
    Abstract: Selective layer disordering in a doped III-nitride superlattice can be achieved by depositing a dielectric capping layer on a portion of the surface of the superlattice and annealing the superlattice to induce disorder of the layer interfaces under the uncapped portion and suppress disorder of the interfaces under the capped portion. The method can be used to create devices, such as optical waveguides, light-emitting diodes, photodetectors, solar cells, modulators, laser, and amplifiers.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 19, 2015
    Inventors: Jonathan J. Wierer, JR., Andrew A. Allerman
  • Patent number: 8980729
    Abstract: An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Aries Chen
  • Patent number: 8980733
    Abstract: The semiconductor device has a semiconductor layer, a gate electrode which covers an end portion of the semiconductor layer, and an insulating layer for insulating the semiconductor layer and the gate electrode. The film thickness of the insulating layer which insulates a region where an end portion of the semiconductor layer and the gate electrode overlap each other is thicker than the film thickness of the insulating layer which covers the central portion of the semiconductor layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Yasuyuki Arai, Yoshitaka Moriya, Kazuko Ikeda, Yoshifumi Tanada, Shuhei Takahashi
  • Publication number: 20150069409
    Abstract: A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 12, 2015
    Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun
  • Patent number: 8975153
    Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Hong-Seng Shue, Kun-Ming Huang, Tzu-Cheng Chen, Ming-Che Yang, Po-Tao Chu
  • Patent number: 8975168
    Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: March 10, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, Nicolas Loubet
  • Publication number: 20150064883
    Abstract: Methods and systems to manufacture a semi-conducting backplane are described. According to one set of implementations, semi-conducting particles are positioned in a supporting material of the semi-conducting backplane utilizing perforations in the supporting material or perforations in a removable support member upon which the semi-conducting backplane is constructed. For example, semi-conducting particles are deposited in perforations on a supporting member such that a portion of the semi-conducting particles protrudes from the supporting member. Suction is applied to the semi-conducting particles to retain the semi-conducting particles in the perforations and a layer of encapsulant material is applied onto the supporting member to cover the protruding portion. The supporting member is then removed from the semi-conducting particles and the layer of encapsulant material, which together form an assembly of the semi-conducting particles and the layer of encapsulant material.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 5, 2015
    Inventor: Douglas R. DYKAAR
  • Publication number: 20150062691
    Abstract: A tunable metamaterial has a two dimensional array of resonant annular ring elements; and a plurality of voltage controllable electrical tuning elements disposed in or adjacent openings in each of said ring elements, each of said voltage controllable electrical tuning element ohmically contacting portions of only one of said ring elements. The voltage controllable electrical tuning elements may comprise highly doped semiconductor tunnel diodes, or the charge accumulation layer at the semiconductor/insulator interface of a metal-insulator-semiconductor structure, or nanoelectromechanical (NEMs) capacitors. The tunable metamaterial may be used, for example, in an optical beam steering device using the aforementioned tunable optical metamaterial in which a free-space optical beam is coupled into a receiving portion of a plane of the optical metamaterial and is steered out of a transmitter portion of the plane of the optical metamaterial in controllable azimuthal and elevational directions.
    Type: Application
    Filed: November 4, 2014
    Publication date: March 5, 2015
    Inventors: Keyvan Sayyah, James H. Schaffner, Pamela R. Patterson
  • Publication number: 20150060874
    Abstract: A flexible electric device includes a first electrode on a flexible member, at least one semiconductor element on the first electrode, at least one filling region adjacent to the semiconductor element and a second electrode on the semiconductor element.
    Type: Application
    Filed: March 6, 2014
    Publication date: March 5, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-hee CHOI, Yun-seong LEE
  • Patent number: 8969145
    Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar
  • Patent number: 8969171
    Abstract: A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the at least one HM layer and the semiconductor layer, and depositing a spacer layer in the trench. The spacer layer comprises a bottom surface portion over the bottom surface of the trench, and a side wall portion along the side wall of the trench. The method further comprises etching the bottom surface portion of the spacer layer while the side wall portion of the spacer layer remains, and etching the insulator layer to extend the trench into the insulator layer.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Patent number: 8969867
    Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10?5 ?·m or more and 4.8×10?3 ?·m or less.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yutaka Okazaki
  • Publication number: 20150054079
    Abstract: A field-effect transistor (FET) on bulk substrate and a method of fabricating the same is discussed herein. The FET includes a dielectric layer disposed on the bulk substrate and a fin structure and a gate structure disposed on the dielectric layer. The dielectric layer includes alternating first and second dielectric regions. The fin structure includes a channel region interposed between a source region and a drain region. The gate structure is capacitively coupled to the fin structure and positioned between the source region and the drain region. Improved performance characteristics of FET is primarily achieved with the dielectric layer providing electrical isolation of the fin structure from the bulk substrate.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Broadcom Corporation
    Inventor: Chang Seo PARK