On Insulating Substrate Or Layer Patents (Class 438/479)
  • Publication number: 20150055912
    Abstract: An optical device may include a waveguide converter that couples an external light-carrying medium to a waveguide embedded within the optical device. In one embodiment, the optical signal emitted from the light-carrying medium enters the converter which focuses the signal (e.g., shrinks the mode of the optical signal) to better match the physical dimensions of the waveguide. Using the converter may improve transmission efficiency relative to directly coupling (e.g., butt-coupling) the light-carrying medium to the waveguide. Specifically, the converter may enable the light-carrying medium to transmit the optical signal directly into the optical device without the use of any external lenses, even if the waveguide is a sub-micron waveguide.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: CISCO TECHNOLOGY, INC.
    Inventor: Ravinder KACHRU
  • Publication number: 20150056791
    Abstract: A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate is provided. The depression penetrating the insulating film is configured so as to extend to the semiconductor substrate. The method includes: forming a thin film of a semiconductor material along a wall surface that defines the depression; annealing the workpiece to cause the semiconductor material of the thin film to move toward a bottom of the depression and to form an epitaxial region corresponding to crystals of the semiconductor substrate; and etching the thin film.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 26, 2015
    Inventors: Satoshi ONODERA, Daisuke SUZUKI, Akinobu KAKIMOTO
  • Patent number: 8962458
    Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-soo Park, Moon-sang Lee
  • Patent number: 8962398
    Abstract: A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of a conductivity type opposite to the body region of the semiconductor fin. A metal semiconductor alloy portion is formed directly on the two source regions and the top surface of the exposed body region between the two source regions. The doping concentration of the exposed top portion of the body region may be increased by ion implantation to provide a low-resistance contact to the body region, or a recombination region having a high-density of crystalline defects may be formed. A hybrid surface semiconductor-on-insulator (HSSOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) thus formed has a body region that is electrically tied to the source region.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8963164
    Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Sanae Shimizu, Kenji Imanishi, Atsushi Yamada, Toyoo Miyajima
  • Patent number: 8962386
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Tetsuhiro Tanaka
  • Patent number: 8962457
    Abstract: A transistor comprises an active layer of an oxide containing at least one element selected from In, Ga and Zn. The active layer is formed such that a desorption gas monitored as a water molecule by a temperature programmed desorption analysis is 1.4/nm3 or less.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomohiro Watanabe
  • Patent number: 8963295
    Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 24, 2015
    Assignee: Tsinghua University
    Inventors: Jing Wang, Renrong Liang, Lei Guo, Jun Xu
  • Patent number: 8962418
    Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Hoshino
  • Publication number: 20150048450
    Abstract: A protective diode has a basic structure including an n+ layer, an n? layer, a p+ layer, and an n? layer in this order. A p-type layer forming the protective diode is the p+ layer with high impurity concentration. Therefore, the spreading of a depletion layer is suppressed and it is possible to reduce the area of the protective diode. In addition, phosphorus ions with a large diffusion coefficient are implanted to form the n? layer with low impurity concentration in the polysilicon layer forming the protective diode. A heat treatment is performed at a temperature of 1000° C. or higher to diffuse the phosphorus ions implanted into the polysilicon layer. Therefore, the impurity profile of the n? layer in the depth direction can be uniformized in the depth direction.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventor: Tatsuya NAITO
  • Patent number: 8956929
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 8956951
    Abstract: A method for manufacturing an SOI wafer includes performing a flattening heat treatment on an SOI wafer under an atmosphere containing an argon gas, in which conditions of SOI wafer preparation are set so that a thickness of an SOI layer of the SOI wafer to be subjected to the flattening heat treatment is 1.4 or more times thicker than that of a BOX layer, and the thickness of the SOI layer is reduced to less than a thickness 1.4 times the thickness of the BOX layer by performing a sacrificial oxidation treatment on the SOI layer of the SOI wafer after the flattening heat treatment.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 17, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Isao Yokokawa, Masahiro Kato, Masayuki Imai
  • Patent number: 8956959
    Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after the first monocrystalline layer has been formed; transferring the second monocrystalline layer overlying the isolation layer; and then performing a second lithography step patterning portions of the first monocrystalline layer as part of forming at least one transistor in the first monocrystalline layer.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: February 17, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 8957426
    Abstract: Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: February 17, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 8951894
    Abstract: A structure of the plasma treatment apparatus is employed in which an upper electrode has projected portions provided with first introduction holes and recessed portions provided with second introduction holes, the first introduction hole of the upper electrode is connected to a first cylinder filled with a gas which is not likely to be dissociated, the second introduction hole is connected to a second cylinder filled with a gas which is likely to be dissociated, the gas which is not likely to be dissociated is introduced into a reaction chamber from an introduction port of the first introduction hole provided on a surface of the projected portion of the upper electrode, and the gas which is likely to be dissociated is introduced into the reaction chamber from an introduction port of the second introduction hole provided on a surface of the recessed portion.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Inoue, Erumu Kikuchi, Hiroto Inoue
  • Publication number: 20150037965
    Abstract: A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.
    Type: Application
    Filed: October 15, 2014
    Publication date: February 5, 2015
    Inventors: Robert Beach, Michael A. Briere, Paul Bridger
  • Patent number: 8946061
    Abstract: In one embodiment, a method of producing a porous semiconductor film on a workpiece includes generating semiconductor precursor ions that comprise one or more of: germanium precursor ions and silicon precursor ions in a plasma of a plasma chamber, in which the semiconductor precursor ions are operative to form a porous film on the workpiece. The method further includes directing the semiconductor precursor ions to the workpiece over a range of angles.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Varian Semiconductor Equiptment Associates, Inc.
    Inventors: Blake Darby, Ludovic Godet, Xianfeng Lu
  • Patent number: 8946062
    Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Guardian Industries Corp.
    Inventors: Vijayen S. Veerasamy, Martin D. Bracamonte
  • Patent number: 8946063
    Abstract: A method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Ali Khakifirooz, Pranita Kerber, Alexander Reznicek
  • Patent number: 8946009
    Abstract: A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Pouya Hashemi
  • Patent number: 8940624
    Abstract: A method of manufacturing a p type nitride semiconductor layer doped with carbon in a highly reproducible manner with an increased productivity is provided. The method includes supplying an III-group material gas for a predetermined time period T1, supplying a V-group material gas containing a carbon source for a predetermined time period T2 when a predetermined time period t1 (t1+T2>T1) elapses after the supply of the III-group material gas begins, repeating the step of supplying the III-group material gas and the step of supplying the V-group material gas when a predetermined time period t2 (t1+T2?t2>T1) elapses after the supply of the V-group material gas begins, and thus forming an AlxGa1-xN semiconductor layer (0<x?1) at a growth temperature of 1190° C.˜1370° C. or a growth temperature at which a substrate temperature is 1070° C.˜1250° C. using a chemical vapor deposition method or a vacuum evaporation method. Nitrogen sites within the semiconductor layer are doped with carbon.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 27, 2015
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Hideo Kawanishi
  • Patent number: 8941095
    Abstract: An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: January 27, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Hyok J. Song, James H. Schaffner, Jeong-Sun Moon, Kyung-Ah Son
  • Patent number: 8940579
    Abstract: Disclosed are new methods of fabricating metal oxide thin films and nanomaterial-derived metal composite thin films via solution processes at low temperatures (<400° C.). The present thin films are useful as thin film semiconductors, thin film dielectrics, or thin film conductors, and can be implemented into semiconductor devices such as thin film transistors and thin film photovoltaic devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignees: Northwestern University, Polyera Corporation
    Inventors: Antonio Facchetti, Tobin J. Marks, Mercouri G. Kanatzidis, Myung-Gil Kim, William Christopher Sheets, He Yan, Yu Xia
  • Patent number: 8940554
    Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Toshiharu Furukawa, Douglas C. La Tulipe, Jr., William R. Tonti
  • Publication number: 20150021692
    Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
    Type: Application
    Filed: March 20, 2014
    Publication date: January 22, 2015
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic Boeuf, Olivier Weber
  • Patent number: 8937313
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. In one embodiment, the semiconductor device includes a substrate, a first silicon nitride layer formed over the substrate, a first silicon oxide layer formed directly on the first silicon nitride layer and having a thickness of about 1000 ? or less, and a hydrogenated polycrystalline silicon layer formed directly on the first silicon oxide layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: January 20, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Mo Chung, Ki-Yong Lee, Jin-Wook Seo, Jong-Ryuk Park
  • Patent number: 8932941
    Abstract: The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from each other, forming a graphene layer having a portion defined as an active area between the first and second metal pads on the insulating material layer, forming third and fourth metal pads on the graphene layer spaced apart from each other with the active area therebetween, the third and fourth metal pads extending above the first metal pad and the second metal pad, respectively, forming a first protection layer to cover all the first and second metal pads, the graphene layer, and the third and fourth metal pads, and etching an entire surface of the first protection layer until only a residual layer made of a material for forming the first protection layer remains on the active area.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-ho Lee, Tae-han Jeon, Yong-sung Kim, Chang-seung Lee, Yong-seok Jung
  • Patent number: 8927329
    Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Yuhei Sato
  • Patent number: 8927387
    Abstract: A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B Doris, Balasubramanian S Haran, Sanjay Mehta, Stefan Schmitz
  • Patent number: 8927432
    Abstract: Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Yang Liu, Chengwen Pei, Yue Tan
  • Patent number: 8927397
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20150004776
    Abstract: The present disclosure discloses a method of preparing the polysilicon layer, wherein by the depositions of the amorphous silicon thin film in batches for many times and the implementation of the excimer laser process after each deposition, it can not only convert the amorphous silicon thin film into the polysilicon thin film completely, but also control the uniformity of the polysilicon thin film, thereby gaining the polysilicon layer of good uniformity which composed of the polysilicon thin films stacked in sequence, improving the performance of the product while effectively avoiding the chromatism problems of the display device, and significantly improving the yield of products.
    Type: Application
    Filed: June 4, 2014
    Publication date: January 1, 2015
    Inventors: YuChun YEH, MinChing HSU
  • Patent number: 8921824
    Abstract: A three-dimensional graphene structure, and methods of manufacturing and transferring the same including forming at least one layer of graphene having a periodically repeated three-dimensional shape. The three-dimensional graphene structure is formed by forming a pattern having a three-dimensional shape on a surface of a substrate, and forming the three-dimensional graphene structure having the three-dimensional shape of the pattern by growing graphene on the substrate on which the pattern is formed. The three-dimensional graphene structure is transferred by injecting a gas between the three-dimensional graphene structure and the substrate, separating the three-dimensional graphene structure from the substrate by bonding the three-dimensional graphene structure to an adhesive support, combining the three-dimensional graphene structure with an insulating substrate, and removing the adhesive support.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: December 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-jin Shin, Jae-young Choi, Ji-hoon Park, Joung-real Ahn
  • Patent number: 8921208
    Abstract: A method for fabricating a semiconductor device includes forming a first insulating layer in a first area of the semiconductor substrate, lowering a height of the semiconductor substrate in a second area and a height of the first insulating layer in the first area, selectively forming a sacrificial layer in the second area using the first insulating layer as a growth prevention layer, and forming a first semiconductor layer on the semiconductor substrate including the sacrificial layer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seung Beom Baek, Bo Min Park, Young Ho Lee, Jong Chul Lee
  • Publication number: 20140377939
    Abstract: Provided is a carrier for a flexible substrate which is capable of handling a flexible substrate during a flexible substrate processing process, while allowing the flexible substrate to be easily separated. Also provided is a substrate processing apparatus, including the carrier, and a method of manufacturing a flexible display apparatus. The carrier includes a substrate supporting portion having a top surface including a mounting surface, an outer circumferential surface, surrounding the mounting surface, and a first heat cutting portion. The first heat cutting portion is located outside the mounting surface so as to be exposed on the top surface and generates heat when a current flows through the first heat cutting portion.
    Type: Application
    Filed: November 25, 2013
    Publication date: December 25, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hayk Khachatryan
  • Patent number: 8916455
    Abstract: Inexpensive semiconductors are produced by depositing a single crystal or large grained silicon on an inexpensive substrate. These semiconductors are produced at low enough temperatures such as temperatures below the melting point of glass. Semiconductors produced are suitable for semiconductor devices such as photovoltaics or displays.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 23, 2014
    Assignees: Solar Tectic LLC, Trustees of Dartmouth College
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Publication number: 20140367632
    Abstract: There are provided a fabricating method of a carbon nanotube-based field effect transistor having an improved binding force with a substrate and a carbon nanotube-based field effect transistor fabricated by the fabricating method. The method includes forming an oxide film on a substrate, forming a photoresist pattern on the oxide film, forming a metal film on the entire surface of the oxide film having the photoresist pattern, removing the photoresist by lifting off, adsorbing carbon nanotubes on the substrate from which the photoresist is removed, performing an annealing process to the substrate to which the carbon nanotubes are adsorbed, and removing the metal film. Since an adhesive strength between a substrate and carbon nanotubes increases, stability and reliability of a field effect transistor can be improved. If the field effect transistor is applied to a liquid sensor or the like, a lifespan of the sensor can be extended and reliability of a measurement result obtained by the sensor can be improved.
    Type: Application
    Filed: October 8, 2013
    Publication date: December 18, 2014
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLGOY
    Inventors: Young Tae BYUN, Sun Ho KIM, Young Min JHON, Eun Gyeong KIM, Jae Seong KIM, Deok Ha WOO
  • Patent number: 8912080
    Abstract: The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8912625
    Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Publication number: 20140363953
    Abstract: A method for manufacturing components on an SOI layer coated with a silicon-germanium layer formed by epitaxial deposition, wherein the heat balance of the anneals performed after the epitaxial deposition is such that the germanium concentration remains higher in the silicon-germanium layer than in the SOI layer.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventor: Didier Dutartre
  • Patent number: 8907333
    Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 9, 2014
    Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbH
    Inventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
  • Patent number: 8906785
    Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 9, 2014
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fumitake Mieno
  • Patent number: 8906768
    Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Hoong Shing Wong, Min-hwa Chi
  • Publication number: 20140353804
    Abstract: A first side surface of post of the first stripe is formed so that a plane which is most parallel to the first side surface among low-index planes of the growing Group III nitride semiconductor is a m-plane (10-10), and a first angle between the first lateral vector obtained by orthogonally projecting a normal vector of the first side surfaces to the main surface and a m-axis projected vector obtained by orthogonally projecting a normal vector of the m-plane of the growing semiconductor to the main surface is from 0.5° to 6°. A second side surface of post of the second stripe is formed so that a plane which is most parallel to the second side surface among low-index planes of the growing semiconductor is an a-plane (11-20), and a second angle between the second lateral vector and an a-axis projected vector of the a-plane is from 0° to 10°.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 4, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Koji Okuno, Takahide Oshio, Naoki Shibata, Hiroshi Amano
  • Publication number: 20140357060
    Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Qing Liu, Nicolas Loubet
  • Publication number: 20140357062
    Abstract: A method of fabricating a semiconductor device, the method including forming a trench on a substrate; forming an insulating layer pattern within the trench; depositing an amorphous material on the substrate and the insulating layer pattern; planarizing the amorphous material; removing a portion of the amorphous material, the removed portion of the amorphous material being on an area of the substrate where the trench has been formed; crystallizing remaining portions of the amorphous material into a single crystal material; and planarizing the single crystal material.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joong-Han SHIN, Bong-Jin KUH, Tae-Gon KIM, Han-Mei CHOI, Jeong-Meung KIM
  • Publication number: 20140357061
    Abstract: Provided are a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises, providing an active fin and a field insulating film including a first trench disposed on the active fin; forming a second trench through performing first etching of the field insulating film that is disposed on side walls and a lower portion of the first trench; forming a first region and a second region in the field insulating film through performing second etching of the field insulating film that is disposed on side walls and a lower portion of the second trench, the first region is disposed adjacent to the active fin and has a first thickness, and the second region is disposed spaced apart from the active fin as compared with the first region and has a second thickness that is thicker than the first thickness; and forming a gate structure on the active fin and the field insulating film.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 4, 2014
    Inventors: Sung-Min Kim, Ji-Su Kang, Dong-Kyu Lee, Dong-Ho Cha
  • Patent number: 8900934
    Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Veeraraghavan S. Basker, Jinghong Li, Chung-Hsun Lin, Sebastian Naczas, Alexander Reznicek, Tenko Yamashita
  • Patent number: 8900959
    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20140346573
    Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan