On Insulating Substrate Or Layer Patents (Class 438/479)
  • Publication number: 20140349468
    Abstract: The present disclosure provides a method for filling a trench formed on an insulating film of a workpiece. The method includes forming a first impurity-containing amorphous silicon film on a wall surface which defines the trench, forming a second amorphous silicon film on the first amorphous silicon film, and annealing the workpiece after the second amorphous silicon film is formed.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 27, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Daisuke SUZUKI, Kazuya TAKAHASHI, Mitsuhiro OKADA, Katsuhiko KOMORI, Satoshi ONODERA
  • Patent number: 8896063
    Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Veeraraghavan S. Basker, Jinghong Li, Chung-Hsun Lin, Sebastian Naczas, Alexander Reznicek, Tenko Yamashita
  • Patent number: 8895371
    Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Patent number: 8896067
    Abstract: Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of fins with a second dielectric material, the bottom second portion of the first group and the second group of fins having a same height; exposing a middle third portion of the first and second groups of fins to an oxidizing environment to create an oxide section that separates the top first portion from the bottom second portion of the first and second groups of fins; and forming one or more fin-type field-effect-transistors (FinFETs) using the top first portion of the first and second groups of fins as fins under gates of the one or more FinFETs.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc Adam Bergendahl, David Vaclav Horak, Shom Ponoth, Chih-Chao Yang, Charles William Koburger, III
  • Patent number: 8889494
    Abstract: A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: November 18, 2014
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Elgin Quek
  • Patent number: 8884297
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 11, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Patent number: 8883573
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Uday Shah, Benjamin Chu-Kung, Been-Yih Jin, Ravi Pillarisetty, Marko Radosavljevic, Willy Rachmady
  • Patent number: 8877615
    Abstract: A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, David V. Horak, Hemanth Jagannathan, Charles W. Koburger, III
  • Publication number: 20140319655
    Abstract: The present disclosure regards a method for coupling a graphene layer to a substrate having at least one hydrophilic surface, the method comprising the steps of providing the substrate having at least one hydrophilic surface, depositing on the hydrophilic surface a layer of a solvent selected in the group constituted by acetone, ethyl lactate, isopropyl alcohol, methylethyl ketone and mixtures thereof and depositing on the solvent layer a graphene layer. It moreover regards an electronic device comprising the graphene/substrate structure obtained.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 30, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Noemi Graziana Sparta', Cristina Tringali, Stella Loverso, Sebastiano Ravesi, Corrado Accardi, Filippo Giannazzo
  • Patent number: 8871608
    Abstract: A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 28, 2014
    Assignee: GTAT Corporation
    Inventors: Venkatesan Murali, Arvind Chari, Gopal Prabhu, Christopher J. Petti
  • Patent number: 8872172
    Abstract: Semiconductor structures having embedded source/drains with oxide underlayers and methods for forming the same. Embodiments include semiconductor structures having a channel in a substrate, and a source/drain region adjacent to the channel including an embedded oxide region and an embedded semiconductor region located above the embedded oxide region. Embodiments further include methods of forming a transistor structure including forming a gate on a substrate, etching a source/drain recess in the substrate, filling a bottom portion of the source/drain recess with an oxide layer, and filling a portion of the source/drain recess not filled by the oxide layer with a semiconductor layer.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Thomas N. Adam
  • Patent number: 8871615
    Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Mori
  • Publication number: 20140312424
    Abstract: A method of producing a silicon-on-insulator article, the method including: forming a first aluminium nitride layer thermally coupled to a first silicon substrate; forming a second aluminium nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminium nitride layers of the first and second substrates together so that the first and second aluminium nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminium nitride layers.
    Type: Application
    Filed: November 2, 2012
    Publication date: October 23, 2014
    Inventors: Andrew John Brawley, Petar Branko Atanackovic, Andrew John Black, Yong Cheow Gary Lim
  • Patent number: 8865576
    Abstract: A method of producing a transistor includes providing a substrate including an electrically conductive material layer stack positioned on the substrate. A first electrically insulating material layer is deposited so that the first electrically insulating material layer contacts a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally deposited so that the second electrically insulating material contacts the first electrically insulating layer, and contacts a second portion of the electrically conductive material layer stack, and contacts at least a portion of the substrate.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 21, 2014
    Assignee: Eastman Kodak Company
    Inventors: Shelby F. Nelson, Lee W. Tutt
  • Patent number: 8859400
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Publication number: 20140299975
    Abstract: This invention relates to a method and board for forming a graphene layer, and more particularly, to a method of forming a high-quality graphene layer using high pressure annealing and to a board used therein. The method of forming the graphene layer includes forming a reaction barrier layer on a substrate layer, forming a metal catalyst layer which functions as a catalyst for forming the graphene layer on the reaction barrier layer, subjecting a board including a stack of the layers to high pressure annealing, and growing the graphene layer on the metal catalyst layer. This board is subjected to high pressure annealing before growth of the graphene layer, and the reaction barrier layer is formed using a material having high adhesion energy to the metal catalyst layer so as to suppress migration of metal catalyst atoms.
    Type: Application
    Filed: December 18, 2013
    Publication date: October 9, 2014
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Byung Jin Cho, Jeong Hun Mun
  • Publication number: 20140291692
    Abstract: A low temperature GaN based super semiconductor comprising a GaN supercell having equal percentages of Cu and at least one material from the family of P, As, or Sb. The GaN supercell is doped in accordance with the formula Ga1-2xCuxAsxN, wherein x is from about 6.25% to about 25%. The supercell is deposited on GaN grown on silicon substrate.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Inventor: Elbadawy Elsharawy
  • Patent number: 8847234
    Abstract: A thin-film transistor array substrate and a fabrication method thereof according to an embodiment of the present invention are disclosed to form an interlayer insulating layer, thereby reducing a failure occurred during the process subsequent to a gate electrode. The thin-film transistor disclosed according to the present invention may include a substrate, a gate electrode formed on the substrate, a planarized insulating layer formed at a lateral surface portion of the gate electrode and at an upper portion of the substrate, a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode, an active layer formed at an upper portion of the planarized insulating layer located at an upper side of the gate electrode, and a source electrode and a drain electrode formed on the active layer and separated from each other based on a channel region.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 30, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Tae-Young Oh, Heung-Lyul Cho, Ji-Eun Jung
  • Publication number: 20140284769
    Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Inventors: Aomar Halimaoui, Jean-Michel Hartmann
  • Publication number: 20140283901
    Abstract: The application discloses a technique for fabricating gallium-arsenide-phosphorous (GaAsP) nanostructures using gallium-assisted (Ga-assisted) Vapour-Liquid-Solid (VLS) growth, i.e. without requiring gold catalyst particles. The resulting Ga-assisted GaAsP nanostructures are free of gold particles, which renders them useful for optoelectronic applications, e.g. as a junction in a solar cell. The Ga-assisted GaAsP nanostructures can be fabricated with a band gap in the range 1.6 to 1.8 eV (e.g. at and around 1.7 eV).
    Type: Application
    Filed: July 17, 2012
    Publication date: September 25, 2014
    Applicant: GASP Solar APS
    Inventors: Martin Aagesen, Henrik Ingerslev Jorgensen, Jeppe Vilstrup Holm, Morten Schaldemose
  • Patent number: 8841756
    Abstract: Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be patterned to expose a portion of the substrate and to form a substrate-dielectric film boundary substantially parallel to a <110> direction. A {110} type sidewall facet can then be formed by epitaxially growing a semiconductor layer on the exposed portion of the substrate and the dielectric film.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 23, 2014
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Patent number: 8841205
    Abstract: A manufacturing method for a semiconductor device, comprising: performing first processing on a plurality of wafers in a first processing order in a first processing apparatus; obtaining a processed amount with respect to each of the plurality of wafers in the first processing; obtaining a processed amount with respect to each of the plurality of wafers by second processing in a second processing apparatus after the first processing; deciding a second processing order, which is different from the first processing order, from the processed amount with respect to each of the plurality of wafers by the first processing and the processed amount with respect to each of the plurality of wafers by the second processing; and performing the second processing on the plurality of wafers in the second processing order in the second processing apparatus.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Kamimura, Takashi Shimizu, Kunihiro Miyazaki
  • Publication number: 20140269047
    Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Mike N. Nguyen
  • Publication number: 20140273418
    Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a set of doped regions in a substrate; forming a crystalline dielectric layer on the substrate, the crystalline dielectric layer including an epitaxial oxide; forming a semiconductor layer on the crystalline dielectric layer, the semiconductor layer and the crystalline dielectric layer forming an extremely thin semiconductor-on-insulator (ETSOI) structure; and forming a set of devices on the semiconductor layer, wherein at least one device in the set of devices is formed over a doped region.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan
  • Publication number: 20140264602
    Abstract: Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon.
    Type: Application
    Filed: September 19, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. BASKER, Bruce DORIS, Ali KHAKIFIROOZ, Tenko YAMASHITA, Chun-chen YEH
  • Publication number: 20140264344
    Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventor: Wen-Shiang Liao
  • Publication number: 20140264282
    Abstract: A method of manufacturing a heterogeneous layered structure includes growing a hexagonal boron nitride sheet directly on a metal substrate in a chamber, increasing a temperature of the chamber to about 300° C. to about 1500° C., and forming a graphene sheet on the hexagonal boron nitride sheet by supplying a carbon source into the chamber while thermally treating the hexagonal boron nitride sheet at the increased temperature.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-joo LEE, Young-jae SONG, Min WANG, Sung-kyu JANG, Jae-young CHOI
  • Patent number: 8835955
    Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Rytis Dargis, Andrew Clark, Michael Lebby
  • Patent number: 8835330
    Abstract: A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Chen, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni
  • Publication number: 20140252566
    Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A first polymer having a high thermal conductivity and a high electrical resistivity is disposed on the first surface of the semiconductor stack structure. An exemplary method includes providing the semiconductor stack structure with the second surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the second surface of the semiconductor stack structure. A following step includes disposing a second polymer having high thermal conductivity and high electrical resistivity directly onto the second surface of the semiconductor stack structure. Additional methods apply silicon nitride layers on the first surface and second surface of the semiconductor stack structure before disposing the first polymer and second polymer to realize the semiconductor device.
    Type: Application
    Filed: April 24, 2014
    Publication date: September 11, 2014
    Applicant: RF Micro Devices, Inc.
    Inventors: Daniel Charles Kerr, Julio Costa, Michael Carroll, Don Willis, Elizabeth Glass
  • Publication number: 20140256116
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Publication number: 20140252567
    Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. One method for manufacturing the semiconductor device includes forming patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive.
    Type: Application
    Filed: April 24, 2014
    Publication date: September 11, 2014
    Applicant: RF Micro Devices, Inc.
    Inventors: Michael Carroll, Julio Costa, Daniel Charles Kerr, Don Willis, Elizabeth Glass
  • Publication number: 20140252415
    Abstract: Electronic devices and methods of forming an electronic device are disclosed herein. An electronic device may include a first 2D atomic crystal layer; a second 2D atomic crystal layer disposed atop the first 2D atomic crystal layer; and an interface comprising van-der-Waals bonds between the first 2D atomic crystal layer and the second 2D atomic crystal layer. A method of forming an electronic device may include depositing a first 2D atomic crystal layer; and depositing a second 2D atomic crystal layer atop the first 2D atomic crystal layer; wherein an interface is formed between the first 2D atomic crystal layer and the second 2D atomic crystal layer via van-der-Waals bonding.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: U.S. ARMY RESEARCH LABORATORY ATTN: RDRL-LOC-I
    Inventor: U.S. ARMY RESEARCH LABORATORY ATTN: RDRL-LOC-1
  • Patent number: 8828812
    Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: September 9, 2014
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy
    Inventors: Jiantao Bian, Zhongying Xue, Zengfeng Di, Miao Zhang
  • Patent number: 8828851
    Abstract: An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroeletronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 8828844
    Abstract: A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Tetsuya Kakehata, Akihisa Shimomura, Shinya Sasagawa, Motomu Kurata
  • Patent number: 8822995
    Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chun-Gi You, Kap-Soo Yoon, Gug-Rae Jo, Sung-Hoon Yang, Ki-Hun Jeong, Seung-Hwan Shim, Jae-Ho Choi
  • Patent number: 8824837
    Abstract: Improved integration of optoelectronic devices is provided by a spacer layer laterally sandwiched between distinct regions that are monolithically fabricated onto the same substrate (e.g., by selective epitaxy). An optical waveguide in one of the regions can optically couple to an optoelectronic device in another of the regions through the spacer layer, thereby providing a monolithically integrated form of butt-coupling. Preferably, the spacer layer thickness is less than about 50 nm, and is more preferably less than about 20 nm, to reduce optical loss. The spacer layer is preferably electrically insulating, to prevent shorting of devices grown by selective epitaxy.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 2, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Shen Ren, David A. B. Miller
  • Patent number: 8823025
    Abstract: III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Publication number: 20140242785
    Abstract: A method is disclosed for growing large grain to single crystalline semiconductor films on inexpensive glass substrates.
    Type: Application
    Filed: May 7, 2014
    Publication date: August 28, 2014
    Applicant: SOLAR-TECTIC, LLC
    Inventor: Ashok Chaudhari
  • Patent number: 8816324
    Abstract: Disclosed is a semiconductor device (10) which comprises a glass substrate (12), a lower electrode layer (14), an n-type doped polycrystalline silicon semiconductor layer (16), a low-temperature insulating film (20) in which openings (22, 23) that serve as nuclei for growth of a nanowire (32) are formed, the nanowire (32) that is grown over the low-temperature insulating film (20) and has a core-shell structure, an insulating layer (50) that surrounds the nanowire (32), and an upper electrode layer (52). The nanowire (32) comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 26, 2014
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Takashi Fukui, Katsuhiro Tomioka, Junichi Motohisa, Shinjiroh Hara
  • Patent number: 8815641
    Abstract: A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 26, 2014
    Assignee: Soitec
    Inventors: Rick C. Jerome, Francois Hebert, Craig McLachlan, Kevin Hoopingarner
  • Patent number: 8815654
    Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud A Mousa, Christopher S. Putnam
  • Patent number: 8809115
    Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Masashi Tsubuku
  • Patent number: 8809906
    Abstract: A semiconductor optical device includes a first clad layer, a second clad layer and an optical waveguide layer sandwiched between the first clad layer and the second clad layer, wherein the optical waveguide layer includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer and extending in one direction, and a third semiconductor layer covering a top surface of the second semiconductor layer, and wherein the first semiconductor layer includes an n-type region disposed on one side of the second semiconductor layer, a p-type region disposed on the other side of the second semiconductor layer, and an i-type region disposed between the n-type region and the p-type region, and wherein the second semiconductor layer has a band gap narrower than band gaps of the first semiconductor layer and the third semiconductor layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Lei Zhu, Shigeaki Sekiguchi, Shinsuke Tanaka, Kenichi Kawaguchi
  • Publication number: 20140227527
    Abstract: PVD and HPHT methods and apparatus for producing materials, for example nitrides, are disclosed.
    Type: Application
    Filed: September 27, 2012
    Publication date: August 14, 2014
    Applicant: Nitride Solutions Inc.
    Inventors: Daniel Brors, Richard Ernest De-Maray, David Slutz
  • Publication number: 20140225153
    Abstract: A method of stably manufacturing a p type nitride semiconductor layer using a carbon dopant is provided. A crystal plane substrate is prepared having a main surface which has an offset angle in a range of +/?0.1% with respect to a C-plane or a crystal plane equivalent to the C-plane; and during a time period in which a III-source gas and a V-source gas are supplied to grow a III-V group nitride semiconductor layer, carbon tetrabromide (CBr4), which is a carbon source gas, is supplied so as to introduce carbon into a V-group atom layer.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 14, 2014
    Applicant: Seoul Semiconductor Co., Ltd.
    Inventor: Hideo KAWANISHI
  • Patent number: 8802534
    Abstract: A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshihiro Komatsu, Tomoaki Moriwaka, Kojiro Takahashi
  • Patent number: 8796742
    Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20140213044
    Abstract: A method for producing periodic crystalline silicon nanostructures of large surface area by: generating a periodic structure having a lattice constant of between 100 nm and 2 ?m on a substrate, the substrate used being a material which is stable at up to at least 570° C., and the structure being produced with periodically repeating shallow and steep areas/flanks, and, subsequently, depositing silicon by directed deposition onto the periodically structured substrate, with a thickness in the range from 0.2 to 3 times the lattice constant, or 40 nm to 6 ?m, at a substrate temperature of up to 400° C., followed by thermally treating the deposited Si layer to effect solid-phase crystallization, at temperatures between 570° C. and 1400° C., over a few minutes up to several days, and optionally subsequently wet-chemically selective etching to remove resultant porous regions of the Si layer.
    Type: Application
    Filed: August 22, 2012
    Publication date: July 31, 2014
    Applicant: HELMHOLTZ-ZENTRUM BERLIN FUER MATERIALIEN UND ENERGIE GMBH
    Inventors: Christiane Becker, Tobias Sontheimer, Matthias Bockmeyer, Eveline Rudigier-Voigt, Bernd Rech